--- /dev/null
+#!/usr/bin/perl
+###########################################
+# Script file to run the flow
+#
+###########################################
+#
+# Command line for synplify_pro
+#
+
+#export SYNPLIFY_LICENSE_FILE=1709@depc159
+use FileHandle;
+
+
+$ENV{LM_LICENSE_FILE}="1709@depc140";
+
+
+
+$PLD_DEVICE="xc4vlx40-10-ff1148";
+$TOPNAME="rpc_trb_v2_fpga";
+
+
+
+#set -e
+#set -o errexit
+
+$c="/opt/Synplicity/fpga_861/bin/synplify_pro -batch $TOPNAME"."_syn.prj";
+$r=execute($c, "do_not_exit" );
+
+
+chdir "workdir";
+my $fh = new FileHandle("<rpc_trb_v2_fpga.srr");
+my @a = <$fh>;
+$fh -> close;
+
+#if ($r) {
+#$c="cat $TOPNAME.srr";
+#system($c);
+#exit 129;
+#}
+
+foreach (@a)
+{
+ if(/Parse errors/)
+ {
+ $c="cat $TOPNAME.srr";
+ system($c);
+ print "bdabdhsadbhjasdhasldhbas";
+ exit 129;
+ }
+}
+#
+# Command line to synthesize
+#
+
+#chdir "..";
+#$c="xst -intstyle xflow -ifn $TOPNAME.xst -ofn $TOPNAME.syr";
+#execute($c);
+#chdir "workdir";
+
+#
+# Command line for ngdbuild
+#
+#$c="ngdbuild -p $PLD_DEVICE -nt timestamp -intstyle xflow -uc ../$TOPNAME.ucf ../$TOPNAME.ngc $TOPNAME.ngd";
+$c="ngdbuild -p $PLD_DEVICE -nt timestamp -intstyle xflow -uc ../$TOPNAME.ucf $TOPNAME.edf $TOPNAME.ngd";
+execute($c);
+#
+# Command line for fpgafit
+#
+$c="map -detail -u -p $PLD_DEVICE -cm speed -pr b -k 4 -c 100 -tx off -intstyle xflow -o $TOPNAME"."_map.ncd $TOPNAME.ngd $TOPNAME.pcf";
+execute($c);
+
+#
+# Command line for Place & Route
+#
+
+$c="par -w -intstyle xflow -ol std -t 1 $TOPNAME"."_map.ncd $TOPNAME.ncd $TOPNAME.pcf";
+execute($c);
+
+#
+# Command line for genarate programming file (.bit)
+#
+
+#$c="bitgen -w -intstyle ise -g DebugBitstream:No -g Binary:no -g Gclkdel0:11111 -g Gclkdel1:11111 -g Gclkdel2:11111 -g Gclkdel3:11111 -g ConfigRate:4 -g CclkPin:PullUp -g M0Pin:PullUp -g M1Pin:PullUp -g M2Pin:PullUp -g ProgPin:PullUp -g DonePin:PullUp -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullUp -g TmsPin:PullUp -g UnusedPin:PullDown -g UserID:0xFFFFFFFF -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GSR_cycle:6 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Security:None -g DonePipe:No -g DriveDone:No $TOPNAME";
+$c="bitgen -intstyle ise -w -g DebugBitstream:No -g Binary:no -g CRC:Enable -g ConfigRate:4 -g CclkPin:PullUp -g M0Pin:PullUp -g M1Pin:PullUp -g M2Pin:PullUp -g ProgPin:PullUp -g DonePin:PullUp -g InitPin:Pullup -g CsPin:Pullup -g DinPin:Pullup -g BusyPin:Pullup -g RdWrPin:Pullup -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullUp -g TmsPin:PullUp -g UnusedPin:PullDown -g UserID:0xFFFFFFFF -g DCMShutdown:Disable -g DisableBandgap:No -g DCIUpdateMode:AsRequired -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Security:None -g DonePipe:No -g DriveDone:No -g Encrypt:No $TOPNAME.ncd";
+
+execute($c);
+#
+# Command line for generate .stapl file
+#
+
+$c="XIL_IMPACT_ENV_LPT_COMPATIBILITY_MODE=true impact -batch ../impact_batch.txt";
+
+execute($c);
+
+
+#ssh depc152 'cd ~/files/vhdl/xilinx; . ~/bin/xilinx_setup; XIL_IMPACT_ENV_LPT_COMPATIBILITY_MODE=true impact -batch conf_xilinx_impact.txt '
+
+#
+#to download file on ETRAX chip
+#
+
+#$c="lftp root:pass@hades18;put RPCBoardContrller;exit";
+#execute($c)
+
+chdir "..";
+
+sub execute {
+ my ($c, $op) = @_;
+ #print "option: $op \n";
+
+ print "\n\ncommand to execute: $c \n";
+ $r=system($c);
+ if($r) {
+ print "$!";
+ if($op ne "do_not_exit") {
+ exit;
+ }
+ }
+
+ return $r;
+
+}
--- /dev/null
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_ARITH.all;
+use IEEE.STD_LOGIC_UNSIGNED.all;
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+library UNISIM;
+use UNISIM.VComponents.all;
+entity dsp_interface is
+ port (
+-- signal to/from dsp
+ HBR_OUT : out std_logic; -- Host Bus Request to DSP
+ HBG_IN : in std_logic; -- Host Bus Grant from DSP
+ RD_OUT : out std_logic; -- read/write enable of DSP
+ DSP_DATA : inout std_logic_vector(31 downto 0);
+ ADDRESS_DSP : out std_logic_vector(31 downto 0);
+ WRL : inout std_logic; --when dsp slave is output
+ WRH : inout std_logic; --when dsp slave is output
+ BM_IN : in std_logic; --Bus Master. For debug
+ DSP_RESET : out std_logic;
+ BRST : inout std_logic;
+ ACK : in std_logic;
+--internal data and address bus
+ CLK : in std_logic;
+ RESET : in std_logic;
+ R_W_ENABLE : in std_logic;
+ TRIGGER : in std_logic;
+ INTERNAL_DATA : inout std_logic_vector(31 downto 0); --63 downto 0
+ INTERNAL_ADDRESS : in std_logic_vector(31 downto 0);
+ VALID_DATA_SENT : out std_logic;
+ ACKNOWLEDGE : in std_logic;
+ DEBUGSTATE_MACHINE : out std_logic_vector(31 downto 0)
+ );
+end dsp_interface;
+
+architecture dsp_interface of dsp_interface is
+
+--signal delaration
+ type state_type is (IDLE, WRITE_DSP_MEMORY, READ_DSP_MEMORY,
+ READ_DSP_MEMORY_NEXT,
+ WRITE_DSP_DATA, READ_DSP_WAIT1,
+ READ_DSP_WAIT2, READ_DSP_WAIT3,
+ READ_DSP_DATA, READ_DSP_WAIT_FOR_HBR,
+ WRITE_DSP_WAIT_FOR_HBR, WRITE_DSP_DUMMY,
+ SENT_DATA_TO_INTERNAL_ENTITY,
+ WRITE_DSP_MEMORY_NEXT, WAIT_ACKNOWLEDGMENT);
+ signal current_state, next_state : state_type;
+ signal debug_register : std_logic_vector(2 downto 0);
+ signal reg_address_dsp, next_address_dsp : std_logic_vector(31 downto 0);
+ signal reg_write_dsp_data, next_write_dsp_data : std_logic_vector(31 downto 0);
+ signal reg_read_dsp_data, next_read_dsp_data : std_logic_vector(31 downto 0);
+
+
+begin -- behavioural
+
+ DEBUGSTATE_MACHINE(2 downto 0) <= debug_register;
+
+
+
+ REGISTER_ADDR_DATA_MODE : process (CLK) --in this way the reset is syn with the
+ --incoming clock
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ reg_write_dsp_data <= (others => '0');
+ reg_address_dsp <= (others => '0');
+ reg_read_dsp_data <= (others => '0');
+ current_state <= IDLE;
+ else
+ reg_write_dsp_data <= next_write_dsp_data;--INTERNAL_DATA;
+ reg_address_dsp <= next_address_dsp;--INTERNAL_ADDRESS;
+ reg_read_dsp_data <= next_read_dsp_data;
+ current_state <= next_state;
+ end if;
+ end if;
+ end process REGISTER_ADDR_DATA_MODE;
+
+ process (R_W_ENABLE, TRIGGER, current_state, HBG_IN, ACKNOWLEDGE, reg_read_dsp_data)
+ begin
+--!!default vaue!!that i can change in
+--another state, they are default for all the machine
+
+--INOUT
+ DSP_DATA <= (others => 'Z');
+ INTERNAL_DATA <= (others => 'Z');
+ WRH <= 'Z';
+ WRL <= 'Z'; --in for virtex to read dsp(it's out =0 if I
+ --write into dsp)
+--OUT
+ HBR_OUT <= '1';
+ ADDRESS_DSP <= (others => 'Z');
+ VALID_DATA_SENT <= '0';
+ RD_OUT <= 'Z';
+ debug_register <= "000";
+ BRST <= '1'; --write in main entity TLD !!!!
+
+ next_read_dsp_data <= reg_read_dsp_data;
+ next_address_dsp <= reg_address_dsp;
+ next_write_dsp_data <= reg_write_dsp_data;
+ next_state <= IDLE;
+
+
+ case current_state is
+ when IDLE =>
+ debug_register <= "000";
+ HBR_OUT <= '1';
+ if TRIGGER = '1' and R_W_ENABLE = '1' then --read when high
+ next_address_dsp <= INTERNAL_ADDRESS;
+ next_state <= READ_DSP_WAIT_FOR_HBR;
+ elsif TRIGGER = '1' and R_W_ENABLE = '0'then --write into the dsp bus
+ next_state <= WRITE_DSP_WAIT_FOR_HBR;
+ next_address_dsp <= INTERNAL_ADDRESS;
+ next_write_dsp_data <= INTERNAL_DATA;
+ else
+ next_state <= IDLE;
+ end if;
+
+ when READ_DSP_WAIT_FOR_HBR =>
+ debug_register <= "001";
+ HBR_OUT <= '0';
+ if HBG_IN = '0' then
+ next_state <= READ_DSP_MEMORY_NEXT;
+ else
+ next_state <= READ_DSP_WAIT_FOR_HBR;
+ end if;
+
+ when READ_DSP_MEMORY_NEXT =>
+ debug_register <= "010";
+ ADDRESS_DSP <= reg_address_dsp;
+ DSP_DATA <= (others => 'Z');
+ RD_OUT <= '0';
+ --WRL <= '1';
+ WRL <= '1';
+ HBR_OUT <= '0';
+ next_state <= READ_DSP_WAIT1;
+
+ when READ_DSP_WAIT1 =>
+ debug_register <= "011";
+ ADDRESS_DSP <= reg_address_dsp;
+
+ RD_OUT <= '1';
+-- WRL <= '1';
+ WRL <= '1';
+ HBR_OUT <= '0';
+ next_state <= READ_DSP_WAIT2;
+
+ when READ_DSP_WAIT2 =>
+
+ RD_OUT <= '1';
+ WRL <= '1';
+ WRL <= '1';
+ HBR_OUT <= '0';
+ next_state <= READ_DSP_WAIT3;
+
+ when READ_DSP_WAIT3 =>
+ debug_register <= "100";
+
+ RD_OUT <= '1';
+ WRL <= '1';
+ WRL <= '1';
+ HBR_OUT <= '0';
+ next_state <= READ_DSP_MEMORY;
+ when READ_DSP_MEMORY =>
+ debug_register <= "101";
+ RD_OUT <= '1';
+ WRL <= '1';
+ WRL <= '1';
+ HBR_OUT <= '0';
+ if ACK = '0' then
+ next_state <= READ_DSP_MEMORY;
+ else
+
+ next_read_dsp_data <= DSP_DATA;
+ next_state <= SENT_DATA_TO_INTERNAL_ENTITY;
+ end if;
+
+
+ when SENT_DATA_TO_INTERNAL_ENTITY =>
+ debug_register <= "110";
+ VALID_DATA_SENT <= '1';
+ INTERNAL_DATA <= reg_read_dsp_data;
+ next_state <= IDLE;
+
+ -----------------------------------------------------------------------
+ -- WRITING part
+ -----------------------------------------------------------------------
+ when WRITE_DSP_WAIT_FOR_HBR =>
+ debug_register <= "001";
+ HBR_OUT <= '0';
+ if HBG_IN = '0' then
+ next_state <= WRITE_DSP_DUMMY;
+ else
+ next_state <= WRITE_DSP_WAIT_FOR_HBR;
+ end if;
+
+ when WRITE_DSP_DUMMY =>
+ debug_register <= "111";
+ HBR_OUT <= '0';
+ ADDRESS_DSP <= (others => '0');
+ WRL <= '1';
+ WRH <= '1';
+ RD_OUT <= '1';
+ next_state <= WRITE_DSP_MEMORY_NEXT;
+
+ when WRITE_DSP_MEMORY_NEXT =>
+ debug_register <= "010";
+ ADDRESS_DSP <= reg_address_dsp;
+ WRL <= '0';
+ WRH <= '1';
+ HBR_OUT <= '0';
+ RD_OUT <= '1';
+ next_state <= WRITE_DSP_MEMORY;
+
+ when WRITE_DSP_MEMORY =>
+ debug_register <= "011";
+ DSP_DATA <= reg_write_dsp_data;
+ WRL <= '1';
+ WRH <= '1';
+ HBR_OUT <= '0';
+ RD_OUT <= '1';
+
+ if ACK = '1' then
+ next_state <= WAIT_ACKNOWLEDGMENT;
+ else
+ next_state <= WRITE_DSP_MEMORY;
+ end if;
+
+ when WAIT_ACKNOWLEDGMENT =>
+ VALID_DATA_SENT <= '1';
+ next_state <= IDLE;
+
+ when others =>
+ next_state <= IDLE;
+
+ end case;
+ end process;
+
+ ------------------------------------------------------------------------------
+ -- SINCRONISE WITH OTHER ENTITY OF MAREK --------------------------------------
+ ------------------------------------------------------------------------------
+ ------------------------------------------------------------------------------
+-- clock_output: process (CLK, RESET)
+-- begin -- process clocke_output
+-- if rising_edge(CLK) then -- rising clock edge
+-- if RESET = '1' then
+-- INTERNAL_DATA <= "0000";
+-- else
+-- reg_internal_data <= next_internal_data;
+-- end if;
+-- end if;
+-- end process clock_output;
+
+end dsp_interface;
+
+
+
+
+
+
--- /dev/null
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use IEEE.NUMERIC_STD.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.all;
+
+-- Uncomment the following lines to use the declarations that are
+-- provided for instantiating Xilinx primitive components.
+
+
+entity etrax_interface is
+ port (
+ CLK : in std_logic;
+ RESET : in std_logic;
+ DATA_BUS : in std_logic_vector(31 downto 0);
+ ETRAX_DATA_BUS_B : out std_logic_vector(17 downto 0);
+ ETRAX_DATA_BUS_C : inout std_logic_vector(17 downto 0);
+ DATA_VALID : in std_logic;
+ ETRAX_BUS_BUSY : out std_logic;
+ ETRAX_READ_ONE_kW : in std_logic;
+ ETRAX_HAS_TO_READ_EVENT : in std_logic;
+ ETRAX_IS_READY_TO_READ : in std_logic;
+ TDC_TCK : out std_logic;
+ TDC_TDI : out std_logic;
+ TDC_TMS : out std_logic;
+ TDC_TRST : out std_logic;
+ TDC_TDO : in std_logic;
+ TDC_RESET : out std_logic;
+ EXTERNAL_ADDRESS : out std_logic_vector(31 downto 0);
+ EXTERNAL_DATA : inout std_logic_vector(31 downto 0);
+ EXTERNAL_ACK : out std_logic;
+ EXTERNAL_VALID : in std_logic;
+ EXTERNAL_MODE : out std_logic_vector(15 downto 0);
+ FPGA_REGISTER_00 : in std_logic_vector(31 downto 0);
+ FPGA_REGISTER_01 : in std_logic_vector(31 downto 0);
+ FPGA_REGISTER_02 : in std_logic_vector(31 downto 0);
+ FPGA_REGISTER_03 : in std_logic_vector(31 downto 0);
+ FPGA_REGISTER_04 : in std_logic_vector(31 downto 0);
+ FPGA_REGISTER_05 : in std_logic_vector(31 downto 0);
+ FPGA_REGISTER_06 : in std_logic_vector(31 downto 0);
+ FPGA_REGISTER_07 : in std_logic_vector(31 downto 0);
+ FPGA_REGISTER_08 : in std_logic_vector(31 downto 0);
+ FPGA_REGISTER_09 : in std_logic_vector(31 downto 0);
+ FPGA_REGISTER_10 : in std_logic_vector(31 downto 0);
+ FPGA_REGISTER_11 : in std_logic_vector(31 downto 0);
+ FPGA_REGISTER_12 : in std_logic_vector(31 downto 0);
+ FPGA_REGISTER_13 : in std_logic_vector(31 downto 0);
+ FPGA_REGISTER_14 : in std_logic_vector(31 downto 0);
+ FPGA_REGISTER_15 : in std_logic_vector(31 downto 0);
+ FPGA_REGISTER_16 : out std_logic_vector(31 downto 0);
+ FPGA_REGISTER_17 : out std_logic_vector(31 downto 0);
+ FPGA_REGISTER_18 : out std_logic_vector(31 downto 0);
+ FPGA_REGISTER_19 : out std_logic_vector(31 downto 0);
+ FPGA_REGISTER_20 : out std_logic_vector(31 downto 0);
+ FPGA_REGISTER_21 : out std_logic_vector(31 downto 0);
+ FPGA_REGISTER_22 : out std_logic_vector(31 downto 0);
+ FPGA_REGISTER_23 : out std_logic_vector(31 downto 0);
+ FPGA_REGISTER_24 : out std_logic_vector(31 downto 0);
+ FPGA_REGISTER_25 : out std_logic_vector(31 downto 0);
+ FPGA_REGISTER_26 : out std_logic_vector(31 downto 0);
+ FPGA_REGISTER_27 : out std_logic_vector(31 downto 0);
+ FPGA_REGISTER_28 : out std_logic_vector(31 downto 0);
+ FPGA_REGISTER_29 : out std_logic_vector(31 downto 0);
+ FPGA_REGISTER_30 : out std_logic_vector(31 downto 0);
+ FPGA_REGISTER_31 : out std_logic_vector(31 downto 0);
+ EXTERNAL_RESET : out std_logic
+ );
+end etrax_interface;
+architecture etrax_interface of etrax_interface is
+ component edge_to_pulse
+ port (
+ clock : in std_logic;
+ en_clk : in std_logic;
+ signal_in : in std_logic;
+ pulse : out std_logic);
+ end component;
+ component up_counter_17bit
+ port (
+ QOUT : out std_logic_vector(16 downto 0);
+ UP : in std_logic;
+ CLK : in std_logic;
+ CLR : in std_logic);
+ end component;
+ type ETRAX_RW_STATE_MACHINE is (IDLE, SAVE_ADDRESS_1, SAVE_ADDRESS_2, SAVE_DATA_1 ,SAVE_DATA_2 , SEND_DATA_1, SEND_ZERO, SEND_DATA_2, WAIT_FOR_DATA, SAVING_EXTERNAL_DATA, SEND_VALID, SEND_EXTERNAL_TRIGGER );
+ signal ETRAX_RW_STATE_currentstate,ETRAX_RW_STATE_nextstate : ETRAX_RW_STATE_MACHINE;
+
+ signal etrax_trigger_pulse : std_logic;
+ signal rw_operation_finished_pulse : std_logic;
+ signal saved_rw_mode : std_logic_vector(17 downto 0);
+ signal saved_address : std_logic_vector (31 downto 0);
+ signal saved_data : std_logic_vector(31 downto 0);
+ signal saved_data_fpga : std_logic_vector(31 downto 0);
+
+ signal data_to_etrax_valid : std_logic;
+ signal fpga_register_00_i : std_logic_vector(31 downto 0);
+ signal fpga_register_01_i : std_logic_vector(31 downto 0);
+ signal fpga_register_02_i : std_logic_vector(31 downto 0);
+ signal fpga_register_03_i : std_logic_vector(31 downto 0);
+ signal fpga_register_04_i : std_logic_vector(31 downto 0);
+ signal fpga_register_05_i : std_logic_vector(31 downto 0);
+ signal fpga_register_06_i : std_logic_vector(31 downto 0);
+ signal fpga_register_07_i : std_logic_vector(31 downto 0);
+ signal fpga_register_08_i : std_logic_vector(31 downto 0);
+ signal fpga_register_09_i : std_logic_vector(31 downto 0);
+ signal fpga_register_10_i : std_logic_vector(31 downto 0);
+ signal fpga_register_11_i : std_logic_vector(31 downto 0);
+ signal fpga_register_12_i : std_logic_vector(31 downto 0);
+ signal fpga_register_13_i : std_logic_vector(31 downto 0);
+ signal fpga_register_14_i : std_logic_vector(31 downto 0);
+ signal fpga_register_15_i : std_logic_vector(31 downto 0);
+ signal fpga_register_16_i : std_logic_vector(31 downto 0);
+ signal fpga_register_17_i : std_logic_vector(31 downto 0);
+ signal fpga_register_18_i : std_logic_vector(31 downto 0);
+ signal fpga_register_19_i : std_logic_vector(31 downto 0);
+ signal fpga_register_20_i : std_logic_vector(31 downto 0);
+ signal fpga_register_21_i : std_logic_vector(31 downto 0);
+ signal fpga_register_22_i : std_logic_vector(31 downto 0);
+ signal fpga_register_23_i : std_logic_vector(31 downto 0);
+ signal fpga_register_24_i : std_logic_vector(31 downto 0);
+ signal fpga_register_25_i : std_logic_vector(31 downto 0);
+ signal fpga_register_26_i : std_logic_vector(31 downto 0);
+ signal fpga_register_27_i : std_logic_vector(31 downto 0);
+ signal fpga_register_28_i : std_logic_vector(31 downto 0);
+ signal fpga_register_29_i : std_logic_vector(31 downto 0);
+ signal fpga_register_30_i : std_logic_vector(31 downto 0);
+ signal fpga_register_31_i : std_logic_vector(31 downto 0);
+ signal counter_for_test : std_logic_vector(16 downto 0);
+ signal saved_external_data : std_logic_vector(31 downto 0);
+ signal debug_reg_00 : std_logic_vector(3 downto 0);
+ signal debug_reg_01 : std_logic_vector(3 downto 0);
+ signal debug_reg_02 : std_logic_vector(3 downto 0);
+ signal debug_reg_03 : std_logic_vector(3 downto 0);
+ signal etrax_data_pulse_0 : std_logic;
+ signal etrax_data_pulse_1 : std_logic;
+ signal etrax_data_pulse_2 : std_logic;
+ signal etrax_data_pulse_3: std_logic;
+ signal debug_reg_04 : std_logic_vector(15 downto 0);
+begin
+
+-- ACK_PULSER : edge_to_pulse
+-- port map (
+-- clock => CLK,
+-- en_clk => '1',
+-- signal_in => ETRAX_DATA_BUS_C(16),
+-- pulse => etrax_ack_pulse);
+
+ ETRAX_TRIGG_PULSER : edge_to_pulse
+ port map (
+ clock => CLK,
+ en_clk => '1',
+ signal_in => ETRAX_DATA_BUS_C(16),
+ pulse => etrax_trigger_pulse);
+ RW_FINISHED_PULSER : edge_to_pulse
+ port map (
+ clock => CLK,
+ en_clk => '1',
+ signal_in => EXTERNAL_VALID,
+ pulse => rw_operation_finished_pulse);
+ DELAY_COUNTER : up_counter_17bit
+ port map (
+ CLK => CLK,
+ UP => etrax_trigger_pulse,
+ CLR => RESET,
+ QOUT => counter_for_test
+ );
+ TDC_TRST <= not fpga_register_18_i(0);--etrax_trigger_pulse and ETRAX_DATA_BUS_C(17);
+ TDC_RESET <= not fpga_register_17_i(0);
+ EXTERNAL_RESET <= etrax_trigger_pulse and ETRAX_DATA_BUS_C(17);
+ REGISTERS: process (CLK)
+ begin
+ if rising_edge(CLK) then
+-- if RESET = '1' then
+-- fpga_register_16_i <= (others => '0');
+-- fpga_register_17_i <= (others => '0');
+-- fpga_register_18_i <= (others => '0');
+-- fpga_register_19_i <= (others => '0');
+-- fpga_register_10_i <= (others => '0');
+-- fpga_register_20_i <= (others => '0');
+-- fpga_register_21_i <= (others => '0');
+-- fpga_register_22_i <= (others => '0');
+-- fpga_register_23_i <= (others => '0');
+-- fpga_register_24_i <= (others => '0');
+-- fpga_register_25_i <= (others => '0');
+-- fpga_register_26_i <= (others => '0');
+-- fpga_register_27_i <= (others => '0');
+-- fpga_register_28_i <= (others => '0');
+-- fpga_register_29_i <= (others => '0');
+-- fpga_register_30_i <= (others => '0');
+-- fpga_register_31_i <= (others => '0');
+-- else
+-- fpga_register_00_i <= FPGA_REGISTER_00;
+ fpga_register_01_i <= FPGA_REGISTER_01;
+ fpga_register_02_i <= FPGA_REGISTER_02;
+ fpga_register_03_i <= FPGA_REGISTER_03;
+ fpga_register_04_i <= FPGA_REGISTER_04;
+ fpga_register_05_i <= FPGA_REGISTER_05;
+ fpga_register_06_i <= FPGA_REGISTER_06;
+ fpga_register_07_i <= FPGA_REGISTER_07;
+ fpga_register_08_i <= FPGA_REGISTER_08;
+ fpga_register_09_i <= FPGA_REGISTER_09;
+ fpga_register_10_i <= FPGA_REGISTER_10;
+ fpga_register_11_i <= FPGA_REGISTER_11;
+ fpga_register_12_i <= FPGA_REGISTER_12;
+ fpga_register_13_i <= FPGA_REGISTER_13;
+ fpga_register_14_i <= FPGA_REGISTER_14;
+ fpga_register_15_i <= FPGA_REGISTER_15;
+ FPGA_REGISTER_16 <= fpga_register_16_i; --this used for TDCjtag enable(0)
+ FPGA_REGISTER_17 <= fpga_register_17_i; --this is used for TDC reset(0)
+ FPGA_REGISTER_18 <= fpga_register_18_i; --this is used for jatgTDC
+ --reset
+ FPGA_REGISTER_19 <= fpga_register_19_i;
+ FPGA_REGISTER_20 <= fpga_register_20_i;
+ FPGA_REGISTER_21 <= fpga_register_21_i;
+ FPGA_REGISTER_22 <= fpga_register_22_i;
+ FPGA_REGISTER_23 <= fpga_register_23_i;
+ FPGA_REGISTER_24 <= fpga_register_24_i;
+ FPGA_REGISTER_25 <= fpga_register_25_i;
+ FPGA_REGISTER_26 <= fpga_register_26_i;
+ FPGA_REGISTER_27 <= fpga_register_27_i;
+ FPGA_REGISTER_28 <= fpga_register_28_i;
+ FPGA_REGISTER_29 <= fpga_register_29_i;
+ FPGA_REGISTER_30 <= fpga_register_30_i;
+ FPGA_REGISTER_31 <= fpga_register_31_i;
+-- end if;
+ end if;
+ end process REGISTERS;
+ ETRAX_FPGA_COMUNICATION_CLOCK : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' or (ETRAX_DATA_BUS_C(16)='1' and ETRAX_DATA_BUS_C(17)='1') then
+ ETRAX_RW_STATE_currentstate <= IDLE;
+ else
+ ETRAX_RW_STATE_currentstate <= ETRAX_RW_STATE_nextstate;
+ end if;
+ end if;
+ end process ETRAX_FPGA_COMUNICATION_CLOCK;
+ ETRAX_FPGA_COMUNICATION: process (ETRAX_RW_STATE_currentstate,etrax_trigger_pulse,saved_rw_mode(15),rw_operation_finished_pulse)
+ begin
+ fpga_register_00_i <= x"00000001";
+ case ETRAX_RW_STATE_currentstate is
+ when IDLE =>
+ fpga_register_00_i <= x"00000001";
+ if etrax_trigger_pulse = '1' then
+ -- saved_rw_mode(17 downto 0) <= ETRAX_DATA_BUS_C;
+ ETRAX_RW_STATE_nextstate <= SAVE_ADDRESS_1;
+ else
+ ETRAX_RW_STATE_nextstate <= IDLE;
+ end if;
+ when SAVE_ADDRESS_1 =>
+ fpga_register_00_i <= x"00000002";
+ if etrax_trigger_pulse = '1' then
+-- saved_address(31 downto 16) <= ETRAX_DATA_BUS_C(15 downto 0);
+ ETRAX_RW_STATE_nextstate <= SAVE_ADDRESS_2;
+ else
+ ETRAX_RW_STATE_nextstate <= SAVE_ADDRESS_1;
+ end if;
+ when SAVE_ADDRESS_2 =>
+ fpga_register_00_i <= x"00000003";
+ if etrax_trigger_pulse = '1' then
+ -- saved_address(15 downto 0) <= ETRAX_DATA_BUS_C(15 downto 0);
+ if saved_rw_mode(15) = '1' then
+ ETRAX_RW_STATE_nextstate <= SEND_EXTERNAL_TRIGGER;
+ else
+ ETRAX_RW_STATE_nextstate <= SAVE_DATA_1;
+ end if;
+ else
+ ETRAX_RW_STATE_nextstate <= SAVE_ADDRESS_2;
+ end if;
+ when SAVE_DATA_1 =>
+ fpga_register_00_i <= x"00000004";
+ if etrax_trigger_pulse = '1' then
+ -- saved_data(31 downto 16) <= ETRAX_DATA_BUS_C(15 downto 0);
+ ETRAX_RW_STATE_nextstate <= SAVE_DATA_2;
+ else
+ ETRAX_RW_STATE_nextstate <= SAVE_DATA_1;
+ end if;
+ when SAVE_DATA_2 =>
+ fpga_register_00_i <= x"00000005";
+ if etrax_trigger_pulse = '1' then
+ -- saved_data(15 downto 0) <= ETRAX_DATA_BUS_C(15 downto 0);
+ ETRAX_RW_STATE_nextstate <= SEND_EXTERNAL_TRIGGER;
+ else
+ ETRAX_RW_STATE_nextstate <= SAVE_DATA_2;
+ end if;
+ when SEND_EXTERNAL_TRIGGER =>
+ ETRAX_RW_STATE_nextstate <= WAIT_FOR_DATA;
+ when WAIT_FOR_DATA =>
+ fpga_register_00_i <= x"00000006";
+ if saved_rw_mode(15) = '0' then
+ ETRAX_RW_STATE_nextstate <= SEND_VALID;
+ elsif rw_operation_finished_pulse = '1' or saved_rw_mode(7 downto 0) = x"00" then
+ ETRAX_RW_STATE_nextstate <= SAVING_EXTERNAL_DATA;
+ else
+ ETRAX_RW_STATE_nextstate <= WAIT_FOR_DATA;
+ end if;
+ when SEND_VALID =>
+ fpga_register_00_i <= x"00000007";
+ if etrax_trigger_pulse = '1' then
+ ETRAX_RW_STATE_nextstate <= IDLE;
+ else
+ ETRAX_RW_STATE_nextstate <= SEND_VALID;
+ end if;
+ when SAVING_EXTERNAL_DATA =>
+ ETRAX_RW_STATE_nextstate <= SEND_DATA_1;
+ when SEND_DATA_1 =>
+ fpga_register_00_i <= x"00000008";
+ if etrax_trigger_pulse = '1' then
+ ETRAX_RW_STATE_nextstate <= SEND_ZERO;
+ else
+ ETRAX_RW_STATE_nextstate <= SEND_DATA_1;
+ end if;
+ when SEND_ZERO =>
+ fpga_register_00_i <= x"0000000a";
+ if etrax_trigger_pulse = '1' then
+ ETRAX_RW_STATE_nextstate <= SEND_DATA_2;
+ else
+ ETRAX_RW_STATE_nextstate <= SEND_ZERO;
+ end if;
+
+ when SEND_DATA_2 =>
+ fpga_register_00_i <= x"00000009";
+ if etrax_trigger_pulse = '1' then
+ ETRAX_RW_STATE_nextstate <= IDLE;
+ else
+ ETRAX_RW_STATE_nextstate <= SEND_DATA_2;
+ end if;
+ when others =>
+ ETRAX_RW_STATE_nextstate <= IDLE;
+ end case;
+ end process ETRAX_FPGA_COMUNICATION;
+
+ REGISTER_ETRAX_BUS: process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ saved_rw_mode <= (others => '0');
+ saved_address <= (others => '0');
+ saved_data <= (others => '0');
+ elsif ETRAX_RW_STATE_currentstate = IDLE and etrax_trigger_pulse = '1' then
+ saved_rw_mode <= ETRAX_DATA_BUS_C;
+ elsif ETRAX_RW_STATE_currentstate = SAVE_ADDRESS_1 and etrax_trigger_pulse = '1' then
+ saved_address(31 downto 16) <= ETRAX_DATA_BUS_C(15 downto 0);
+ elsif ETRAX_RW_STATE_currentstate = SAVE_ADDRESS_2 and etrax_trigger_pulse = '1' then
+ saved_address(15 downto 0) <= ETRAX_DATA_BUS_C(15 downto 0);
+ elsif ETRAX_RW_STATE_currentstate = WAIT_FOR_DATA and rw_operation_finished_pulse = '1' then
+ saved_external_data <= EXTERNAL_DATA;
+ elsif ETRAX_RW_STATE_currentstate = SAVE_DATA_1 and etrax_trigger_pulse = '1' then
+ saved_data(31 downto 16) <= ETRAX_DATA_BUS_C(15 downto 0);
+ elsif ETRAX_RW_STATE_currentstate = SAVE_DATA_2 and etrax_trigger_pulse = '1' then
+ saved_data(15 downto 0) <= ETRAX_DATA_BUS_C(15 downto 0);
+ else
+ saved_rw_mode <= saved_rw_mode;
+ saved_address <= saved_address;
+ saved_data <= saved_data;
+ end if;
+ end if;
+ end process REGISTER_ETRAX_BUS;
+ EXTERNAL_ADDRESS <= saved_address;
+ EXTERNAL_MODE <= saved_rw_mode(15 downto 0);
+ EXTERNAL_DATA_LOGIC: process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ EXTERNAL_DATA <= (others => 'Z');
+ elsif ETRAX_RW_STATE_currentstate = SEND_EXTERNAL_TRIGGER and saved_rw_mode(15) = '1' then
+ EXTERNAL_DATA <= (others => 'Z');
+ EXTERNAL_ACK <= '1';
+ elsif ETRAX_RW_STATE_currentstate = SEND_EXTERNAL_TRIGGER and saved_rw_mode(15) = '0' then
+ EXTERNAL_DATA <= saved_data;
+ EXTERNAL_ACK <= '1';
+ -- elsif ETRAX_RW_STATE_currentstate = SAVING_EXTERNAL_DATA then --or
+-- (ETRAX_RW_STATE_currentstate = SEND_VALID and etrax_trigger_pulse ='1')then
+-- EXTERNAL_ACK <= '1';
+-- EXTERNAL_DATA <= (others => 'Z');
+ else
+ EXTERNAL_ACK <= '0';
+ EXTERNAL_DATA <= (others => 'Z');
+ end if;
+ end if;
+ end process EXTERNAL_DATA_LOGIC;
+ ETRAX_DATA_BUS_CHOOSE : process (CLK, RESET,ETRAX_RW_STATE_currentstate)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ ETRAX_DATA_BUS_B <= "00"& x"FF00";--(others => 'Z');
+ elsif ETRAX_RW_STATE_currentstate = SEND_DATA_1 then
+ ETRAX_DATA_BUS_B(15 downto 0) <= saved_data_fpga(31 downto 16);--fpga_register_07_i(15 downto 0);--
+ ETRAX_DATA_BUS_B(16) <= '1';
+ ETRAX_DATA_BUS_B(17) <= '0';
+ elsif ETRAX_RW_STATE_currentstate = SEND_DATA_2 or ETRAX_RW_STATE_currentstate = SEND_VALID then
+ ETRAX_DATA_BUS_B(15 downto 0) <= saved_data_fpga(15 downto 0);--fpga_register_07_i(15 downto 0);--
+ ETRAX_DATA_BUS_B(16) <= '1';
+ ETRAX_DATA_BUS_B(17) <= '0';
+ else
+ ETRAX_DATA_BUS_B(15 downto 0) <= fpga_register_07_i(15 downto 0);
+ ETRAX_DATA_BUS_B(17 downto 16) <= "00";
+ end if;
+ end if;
+ end process ETRAX_DATA_BUS_CHOOSE;
+ TDC_JAM_SIGNALS : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ TDC_TMS <= '0';
+ TDC_TCK <= '0';
+ TDC_TDI <= '0';
+ ETRAX_DATA_BUS_C <= (others => 'Z');
+ elsif fpga_register_16_i(0) = '1' then
+ ETRAX_DATA_BUS_C <= (others => 'Z');
+ TDC_TMS <= ETRAX_DATA_BUS_C(1);
+ TDC_TCK <= ETRAX_DATA_BUS_C(2);
+ TDC_TDI <= ETRAX_DATA_BUS_C(3);
+ ETRAX_DATA_BUS_C(0) <= TDC_TDO;
+ ETRAX_DATA_BUS_C(17 downto 1) <= (others => 'Z');
+-- ETRAX_DATA_BUS_C(13 downto 0) <= (others => 'Z');
+ else
+ TDC_TMS <= '1';
+ TDC_TCK <= '1';
+ TDC_TDI <= '1';
+ ETRAX_DATA_BUS_C <= (others => 'Z');
+ end if;
+ end if;
+ end process TDC_JAM_SIGNALS;
+
+-- TDC_TMS <= '0';
+-- TDC_TCK <= '0';
+-- TDC_TDI <= '0';
+-- ETRAX_DATA_BUS_B <= "11" & x"abba";
+-- ETRAX_DATA_BUS_B <= RESET & RESET & x"abb" & '0' & '0' & RESET & '0';
+-- ETRAX_DATA_BUS_C <= "11" & x"baca";
+ DATA_SOURCE_SELECT : process (CLK)
+ begin
+ if rising_edge(CLK) then
+ if RESET ='1' or (ETRAX_DATA_BUS_C(16) = '1' and ETRAX_DATA_BUS_C(17) = '1') then
+ fpga_register_16_i <= x"00000000";
+ fpga_register_19_i <= (others => '0');
+ else
+ case saved_rw_mode(7 downto 0) is
+ when "00000000" =>
+ if saved_rw_mode(15) = '1' then
+ case saved_address(31 downto 0) is
+ when x"00000000" => saved_data_fpga <= fpga_register_00_i;
+ when x"00000001" => saved_data_fpga <= fpga_register_01_i;
+ when x"00000002" => saved_data_fpga <= fpga_register_02_i;
+ when x"00000003" => saved_data_fpga <= fpga_register_03_i;
+ when x"00000004" => saved_data_fpga <= fpga_register_04_i;
+ when x"00000005" => saved_data_fpga <= fpga_register_05_i;
+ when x"00000006" => saved_data_fpga <= fpga_register_06_i;
+ when x"00000007" => saved_data_fpga <= fpga_register_07_i;
+ when x"00000008" => saved_data_fpga <= fpga_register_08_i;
+ when x"00000009" => saved_data_fpga <= fpga_register_09_i;
+ when x"00000010" => saved_data_fpga <= fpga_register_10_i;
+ when x"00000011" => saved_data_fpga <= fpga_register_11_i;
+ when x"00000012" => saved_data_fpga <= fpga_register_12_i;
+ when x"00000013" => saved_data_fpga <= fpga_register_13_i;
+ when x"00000014" => saved_data_fpga <= fpga_register_14_i;
+ when x"00000015" => saved_data_fpga <= fpga_register_15_i;
+ when x"00000016" => saved_data_fpga <= fpga_register_16_i;
+ when x"00000017" => saved_data_fpga <= fpga_register_17_i;
+ when x"00000018" => saved_data_fpga <= fpga_register_18_i;
+ when x"00000019" => saved_data_fpga <= fpga_register_19_i;
+ when x"00000020" => saved_data_fpga <= fpga_register_20_i;
+ when x"00000021" => saved_data_fpga <= fpga_register_21_i;
+ when x"00000022" => saved_data_fpga <= fpga_register_22_i;
+ when x"00000023" => saved_data_fpga <= fpga_register_23_i;
+ when x"00000024" => saved_data_fpga <= fpga_register_24_i;
+ when x"00000025" => saved_data_fpga <= fpga_register_25_i;
+ when x"00000026" => saved_data_fpga <= fpga_register_26_i;
+ when x"00000027" => saved_data_fpga <= fpga_register_27_i;
+ when x"00000028" => saved_data_fpga <= fpga_register_28_i;
+ when x"00000029" => saved_data_fpga <= fpga_register_29_i;
+ when x"00000030" => saved_data_fpga <= fpga_register_30_i;
+ when x"00000031" => saved_data_fpga <= fpga_register_31_i;
+ when others => saved_data_fpga <= x"deadface";
+ end case;
+ elsif saved_rw_mode(15) = '0' and ETRAX_RW_STATE_currentstate = WAIT_FOR_DATA then
+ case saved_address(31 downto 0) is
+ when x"00000016" => fpga_register_16_i <= saved_data;
+ when x"00000017" => fpga_register_17_i <= saved_data;
+ when x"00000018" => fpga_register_18_i <= saved_data;
+ when x"00000019" => fpga_register_19_i <= saved_data;
+ when x"00000020" => fpga_register_20_i <= saved_data;
+ when x"00000021" => fpga_register_21_i <= saved_data;
+ when x"00000022" => fpga_register_22_i <= saved_data;
+ when x"00000023" => fpga_register_23_i <= saved_data;
+ when x"00000024" => fpga_register_24_i <= saved_data;
+ when x"00000025" => fpga_register_25_i <= saved_data;
+ when x"00000026" => fpga_register_26_i <= saved_data;
+ when x"00000027" => fpga_register_27_i <= saved_data;
+ when x"00000028" => fpga_register_28_i <= saved_data;
+ when x"00000029" => fpga_register_29_i <= saved_data;
+ when x"00000030" => fpga_register_30_i <= saved_data;
+ when x"00000031" => fpga_register_31_i <= saved_data;
+ when others => null;
+ end case;
+ end if;
+ when "00000001" => --DSP write read
+ saved_data_fpga <= saved_external_data;
+ when others => --ADDON board write read
+ saved_data_fpga <= x"deadface";
+ end case;
+ end if;
+ end if;
+ end process DATA_SOURCE_SELECT;
+ -----------------------------------------------------------------------------
+ -- test counetrs
+ -----------------------------------------------------------------------------
+-- ETRAX_DATA_BUS_PULSER_00 : edge_to_pulse
+-- port map (
+-- clock => CLK,
+-- en_clk => '1',
+-- signal_in => ETRAX_DATA_BUS_C(17),
+-- pulse => etrax_data_pulse_0 );
+-- ETRAX_DATA_BUS_PULSER_01 : edge_to_pulse
+-- port map (
+-- clock => CLK,
+-- en_clk => '1',
+-- signal_in => ETRAX_DATA_BUS_C(16),
+-- pulse => etrax_data_pulse_1 );
+-- ETRAX_DATA_BUS_PULSER_02 : edge_to_pulse
+-- port map (
+-- clock => CLK,
+-- en_clk => '1',
+-- signal_in => ETRAX_DATA_BUS_C(12),
+-- pulse => etrax_data_pulse_2 );
+-- ETRAX_DATA_BUS_PULSER_03 : edge_to_pulse
+-- port map (
+-- clock => CLK,
+-- en_clk => '1',
+-- signal_in => ETRAX_DATA_BUS_C(5),
+-- pulse => etrax_data_pulse_3 );
+
+-- DEBUG_COUNTERS: process (CLK, RESET)
+-- begin
+-- if rising_edge(CLK) then
+-- if RESET = '1' then
+-- debug_reg_00 <= (others => '0');
+-- debug_reg_01 <= (others => '0');
+-- debug_reg_02 <= (others => '0');
+-- debug_reg_03 <= (others => '0');
+-- elsif etrax_data_pulse_0 = '1' then
+-- debug_reg_00 <= debug_reg_00 + 1;
+-- elsif etrax_data_pulse_1 = '1' then
+-- debug_reg_01 <= debug_reg_01 + 1;
+-- elsif etrax_data_pulse_2 = '1' then
+-- debug_reg_02 <= debug_reg_02 + 1;
+-- elsif etrax_data_pulse_3 = '1' then
+-- debug_reg_03 <= debug_reg_03 + 1;
+-- else
+-- debug_reg_00 <= debug_reg_00;
+-- debug_reg_01 <= debug_reg_01;
+-- debug_reg_02 <= debug_reg_02;
+-- debug_reg_03 <= debug_reg_03;
+-- end if;
+-- end if;
+-- end process DEBUG_COUNTERS;
+-- -- ETRAX_DATA_BUS_B(15 downto 0) <= debug_reg_03 & debug_reg_02 & debug_reg_01 & debug_reg_00;
+-- -- ETRAX_DATA_BUS_B(16) <= '1' when debug_reg_00 /= debug_reg_01 or
+-- -- debug_reg_00 /= debug_reg_02 or
+-- -- debug_reg_00 /= debug_reg_03 or
+-- -- debug_reg_01 /= debug_reg_02 or
+-- -- debug_reg_01 /= debug_reg_03 or
+-- -- debug_reg_02 /= debug_reg_03 else '0';
+-- DEBUG_COUNT_OUT: process (CLK, RESET)
+-- begin -- process DEBUG_COUNT_OUT
+-- if rising_edge(CLK) then -- rising clock edge
+-- if RESET = '1' then -- asynchronous reset (active low)
+-- debug_reg_04 <= (others => '0');
+-- else
+
+-- debug_reg_04 <= debug_reg_04 + 1;
+-- end if;
+-- end if;
+-- end process DEBUG_COUNT_OUT;
+-- EXTERNAL_DEBUG <= '1' when debug_reg_04 < x"00ff" else '0';
+ end etrax_interface;
--- /dev/null
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_arith.all;
+use IEEE.STD_LOGIC_unsigned.all;
+
+
+entity f_divider is
+
+ generic(
+ cnt : integer := 4000 -- Der Teiler teilt durch "cnt" , wenn Test = 0 ist. --
+ );
+
+ port (
+ clk : in std_logic;
+ ena_cnt : in std_logic;
+ f_div : out std_logic
+ );
+
+end f_divider;
+
+
+
+architecture arch_f_divider of f_divider is
+
+ function How_many_Bits (int : integer) return integer is
+ variable i, tmp : integer;
+ begin
+ tmp := int;
+ i := 0;
+ while tmp > 0 loop
+ tmp := tmp / 2;
+ i := i + 1;
+ end loop;
+ return i;
+ end How_many_bits;
+
+
+ --+
+ --| Wie Breit muss der Teiler sein, um durch "cnt" teilen zu können? |
+ --+
+ constant c_counter_width : integer := How_many_Bits(cnt - 2);
+
+ --+ ---------------------------------------------------------------------------------------------+
+ --| Des Zähler "s_counter" muss ein Bit breiter definiert werden, als zur Abarbeitung des "cnt" |
+ --| nötig wäre. Dieses Bit wird beim Zählerunterlauf '1'. Der Zählerablauf wird dadurch ohne |
+ --| Komparator erkannt, er steht als getaktetes physikalisches Signal zur Verfügung. |
+ --+ ---------------------------------------------------------------------------------------------+
+ signal s_counter : std_logic_vector(c_counter_width downto 0) := conv_std_logic_vector(0, c_counter_width+1);
+
+ --+ ---------------------------------------------------------------------------------------------+
+ --| Teiler muss mit einen um -2 geringeren Wert geladen werden. Da das Neuladen erst durch dem |
+ --| Unterlauf Zählers erfolgt. D.h. die Null und minus Eins werden mitgezählt. |
+ --+ ---------------------------------------------------------------------------------------------+
+ constant c_ld_value : integer := cnt - 2;
+
+begin
+ p_f_divider : process (clk)
+ begin
+ if clk'event and clk = '1' then
+ if s_counter(s_counter'high) = '1' then -- Bei underflow wird neu geladen --
+ s_counter <= conv_std_logic_vector(c_ld_value, s_counter'length);
+ elsif ena_cnt = '1' then
+ if s_counter(s_counter'high) = '0' then -- Kein underflow erreicht weiter --
+ s_counter <= s_counter - 1; -- subtrahieren. --
+ end if;
+ end if;
+ end if;
+ end process p_f_divider;
+
+ f_div <= s_counter(s_counter'high);
+
+end arch_f_divider;
+
+
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_ARITH.all;
+use IEEE.STD_LOGIC_UNSIGNED.all;
+
+
+--library synplify;
+--use synplify.attributes.all;
+
+
+entity edge_to_pulse is
+
+ port (
+ clock : in std_logic;
+ en_clk : in std_logic;
+ signal_in : in std_logic;
+ pulse : out std_logic);
+
+end edge_to_pulse;
+
+architecture arch_edge_to_pulse of edge_to_pulse is
+ signal signal_sync : std_logic;
+ signal old_sync : std_logic;
+ type state is (idle, high, wait_for_low); -- state
+ signal current_state, next_state : state;
+
+begin -- arch_edge_to_pulse
+
+ fsm : process (clock)
+ begin -- process fsm
+ if clock'event and clock = '1' then -- rising clock edge
+ if en_clk = '1' then
+ current_state <= next_state;
+ signal_sync <= signal_in;
+ end if;
+ end if;
+ end process fsm;
+
+
+ fsm_comb : process (current_state, signal_sync)
+ begin -- process fsm_comb
+ case current_state is
+ when idle =>
+ pulse <= '0';
+ if signal_sync = '1' then
+ next_state <= high;
+ else
+ next_state <= idle;
+ end if;
+ when high =>
+ pulse <= '1';
+ next_state <= wait_for_low;
+-- when wait_for_low_1 =>
+-- pulse <= '1';
+-- next_state <= wait_for_low;
+ when wait_for_low =>
+ pulse <= '0';
+ if signal_sync = '0' then
+ next_state <= idle;
+ else
+ next_state <= wait_for_low;
+ end if;
+ when others =>
+ next_state <= idle;
+ end case;
+ end process fsm_comb;
+
+
+end arch_edge_to_pulse;
+
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+package support is
+
+ component f_divider
+ generic (
+ cnt : integer);
+ port (
+ clk : in std_logic;
+ ena_cnt : in std_logic;
+ f_div : out std_logic);
+ end component;
+
+ component edge_to_pulse
+ port (
+ clock : in std_logic;
+ en_clk : in std_logic;
+ signal_in : in std_logic;
+ pulse : out std_logic);
+ end component;
+
+
+end support;
+
--- /dev/null
+setMode -bs
+setMode -bs
+setCable -port stapl -file "/home/marek/rpc_trb_v2_fpga/trbv2_fpga.stapl"
+addDevice -p 1 -file "/home/marek/rpc_trb_v2_fpga/workdir/rpc_trb_v2_fpga.bit"
+Program -p 1 -defaultVersion 0
+quit
\ No newline at end of file
--- /dev/null
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_ARITH.all;
+use IEEE.STD_LOGIC_UNSIGNED.all;
+use IEEE.NUMERIC_STD.all;
+library UNISIM;
+use UNISIM.VComponents.all;
+entity lvl1_and_lvl2_busy is
+ port (
+ CLK : in std_logic;
+ RESET : in std_logic;
+ LVL1_BUSY : out std_logic;
+ LVL2_BUSY : out std_logic;
+ TDC_LVL1_BUSY : in std_logic;
+ TDC_LVL2_BUSY : in std_logic;
+ LVL1_TRIGG : in std_logic;
+ LVL2_TRIGG : in std_logic;
+ TRIGGER_CODE : in std_logic_vector(3 downto 0);
+ TDC_READOUT_COMPLETED : in std_logic
+ );
+end lvl1_and_lvl2_busy;
+architecture lvl1_and_lvl2_busy of lvl1_and_lvl2_busy is
+ component up_down_counter_16_bit
+ port (
+ QOUT : out std_logic_vector(15 downto 0);
+ UP : in std_logic;
+ DOWN : in std_logic;
+ CLK : in std_logic;
+ CLR : in std_logic
+ );
+ end component;
+ component edge_to_pulse
+ port (
+ clock : in std_logic;
+ en_clk : in std_logic;
+ signal_in : in std_logic;
+ pulse : out std_logic);
+ end component;
+ signal count_lvl1_lvl2_diff : std_logic_vector(15 downto 0);
+ signal lvl1_count_pulse : std_logic;
+ signal lvl2_count_pulse : std_logic;
+ signal write_busy_lvl1 : std_logic;
+ signal count_busy_lvl2 : std_logic;
+ signal write_busy_lvl1_pulse : std_logic;
+begin
+-------------------------------------------------------------------------------
+-- LVL1 start pulse for count (up)
+-------------------------------------------------------------------------------
+ LVL1_COUNT_PULSER : edge_to_pulse
+ port map (
+ clock => CLK,
+ en_clk => '1',
+ signal_in => LVL1_TRIGG,
+ pulse => lvl1_count_pulse);
+-------------------------------------------------------------------------------
+-- LVL2 start pulse for count(down)
+-------------------------------------------------------------------------------
+ LVL2_COUNT_PULSER : edge_to_pulse
+ port map (
+ clock => CLK,
+ en_clk => '1',
+ signal_in => LVL2_TRIGG,
+ pulse => lvl2_count_pulse);
+-----------------------------------------------------------------------------
+-- UP PULSE
+-----------------------------------------------------------------------------
+ LVL1_UP_PULSER : edge_to_pulse
+ port map (
+ clock => CLK,
+ en_clk => '1',
+ signal_in => write_busy_lvl1,
+ pulse => write_busy_lvl1_pulse);
+-------------------------------------------------------------------------------
+-- up down counter(difference)
+-------------------------------------------------------------------------------
+ DIFF_LVL1_LVL2_COUNT : up_down_counter_16_bit
+ port map (
+ QOUT => count_lvl1_lvl2_diff,
+ UP => write_busy_lvl1_pulse,
+ DOWN => lvl2_count_pulse,
+ CLK => CLK,
+ CLR => RESET);
+-----------------------------------------------------------------------------
+-- LEVEL 1 BUSY LOGIC
+-----------------------------------------------------------------------------
+
+ BUSY_LVL1 : process (CLK)
+ begin
+ if rising_edge(CLK) then
+ if TDC_READOUT_COMPLETED = '1' or RESET = '1' then
+ write_busy_lvl1 <= '0';
+ elsif lvl1_count_pulse = '1' and TRIGGER_CODE /= x"d" then
+ write_busy_lvl1 <= '1';
+ end if;
+ end if;
+ end process BUSY_LVL1;
+ LVL1_BUSY <= write_busy_lvl1 or TDC_LVL1_BUSY;
+----------------------------------------------------------------------------
+-- LEVEL 2 BUSY LOGIC
+----------------------------------------------------------------------------
+ LVL1_BUSY <= write_busy_lvl1 or TDC_LVL1_BUSY;
+ count_busy_lvl2 <= write_busy_lvl1 when count_lvl1_lvl2_diff = x"01" else '0';
+ LVL2_BUSY <= TDC_LVL2_BUSY or count_busy_lvl2;
+-------------------------------------------------------------------------------
+-- End of LVL2 TRIGGER LOGIC
+-------------------------------------------------------------------------------
+end lvl1_and_lvl2_busy;
--- /dev/null
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+-- Uncomment the following lines to use the declarations that are
+-- provided for instantiating Xilinx primitive components.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity simpleupcounter_10bit is
+ Port ( QOUT : out std_logic_vector(9 downto 0);
+ UP : in std_logic;
+ CLK : in std_logic;
+ CLR : in std_logic);
+end simpleupcounter_10bit;
+
+architecture Behavioral of simpleupcounter_10bit is
+
+signal counter: std_logic_vector (9 downto 0);
+
+begin
+
+ process (CLR, UP, CLK)
+
+ begin
+ if CLR = '1' then
+ counter <= ( others => '0');
+ elsif clk'event and clk = '1' then
+ if UP = '1' then
+ counter <= counter + 1;
+ else
+ counter <= counter;
+ end if;
+end if;
+end process;
+
+QOUT <= counter;
+
+end Behavioral;
--- /dev/null
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+-- Uncomment the following lines to use the declarations that are
+-- provided for instantiating Xilinx primitive components.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity simpleupcounter_16bit is
+ Port ( QOUT : out std_logic_vector(15 downto 0);
+ UP : in std_logic;
+ CLK : in std_logic;
+ CLR : in std_logic);
+end simpleupcounter_16bit;
+
+architecture Behavioral of simpleupcounter_16bit is
+
+signal counter: std_logic_vector (15 downto 0);
+
+begin
+
+ process (CLR, UP, CLK)
+
+ begin
+ if CLR = '1' then
+ counter <= "0000000000000000";
+ elsif clk'event and clk = '1' then
+ if UP = '1' then
+ counter <= counter + 1;
+ else
+ counter <= counter;
+ end if;
+end if;
+end process;
+
+QOUT <= counter;
+
+end Behavioral;
--- /dev/null
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use IEEE.NUMERIC_STD.all;
+
+library UNISIM;
+use UNISIM.VComponents.all;
+entity tdc_interface is
+ port (
+ CLK : in std_logic;
+ TDC_CLK : in std_logic; -- for input clock should be
+ -- through clock buffer
+ RESET : in std_logic;
+ TDC_DATA_IN : in std_logic_vector (31 downto 0);
+ --data from TDC
+ START_TDC_READOUT : in std_logic;
+ --signal from rpc_trb_v2_fpga - trigger has arrived,one pulse (40MHz long)
+ --or 100MHz long - but make 25 ns from this !!!
+ A_TDC_READY : in std_logic;
+ B_TDC_READY : in std_logic;
+ C_TDC_READY : in std_logic;
+ D_TDC_READY : in std_logic;
+ SEND_TDC_TOKEN : out std_logic;
+ RECEIVED_TDC_TOKEN : in std_logic;
+ GET_TDC_DATA : out std_logic; --Signal to TDC chip
+ TO_MANY_TDC_DATA : in std_logic;
+--TDC state mechines had to cut data
+--but this should be in FIFO entity and should goes to tdc_interface.vhd (
+--to stop writing to fifo just finish read out)
+--copyt to internal FIFO
+ TDC_READOUT_COMPLETED : out std_logic;
+ LVL1_TAG : in std_logic_vector(7 downto 0);
+ LVL1_CODE : in std_logic_vector(3 downto 0);
+ HOW_MANY_ADD_DATA : in std_logic_vector(7 downto 0);
+ COUNTER_a : in std_logic_vector(31 downto 0);
+ COUNTER_b : in std_logic_vector(31 downto 0);
+ COUNTER_c : in std_logic_vector(31 downto 0);
+ COUNTER_d : in std_logic_vector(31 downto 0);
+ COUNTER_e : in std_logic_vector(31 downto 0);
+ COUNTER_f : in std_logic_vector(31 downto 0);
+ COUNTER_g : in std_logic_vector(31 downto 0);
+ COUNTER_h : in std_logic_vector(31 downto 0);
+ COUNTER_i : in std_logic_vector(31 downto 0);
+ COUNTER_j : in std_logic_vector(31 downto 0);
+ COUNTER_k : in std_logic_vector(31 downto 0);
+ COUNTER_l : in std_logic_vector(31 downto 0);
+ COUNTER_m : in std_logic_vector(31 downto 0);
+ LVL2_TRIGGER : in std_logic_vector(1 downto 0);
+ TDC_DATA_OUT : out std_logic_vector (31 downto 0); --data to RAM (LVL2)
+ TDC_DATA_VALID : out std_logic; -- The TDC_DATA_OUT can be written
+ -- to RAM
+ ETRAX_READ_ONE_kW : in std_logic;
+ ETRAX_HAS_TO_READ_EVENT : out std_logic; --this signal has to be used in
+ --LVL2 busy !!!!
+ ETRAX_IS_READY_TO_READ : in std_logic;
+ TDC_LVL1_BUSY : out std_logic;
+ TDC_LVL2_BUSY : out std_logic
+ );
+end tdc_interface;
+architecture tdc_interface of tdc_interface is
+ component edge_to_pulse
+ port (
+ clock : in std_logic;
+ en_clk : in std_logic;
+ signal_in : in std_logic;
+ pulse : out std_logic);
+ end component;
+ component lvl1_fifo
+ port (
+ RESET : in std_logic;
+ WRITE_ADDRESS : in std_logic_vector (19 downto 0);
+ READ_ADDRESS : in std_logic_vector (19 downto 0);
+ DATA_IN : in std_logic_vector (31 downto 0);
+ DATA_OUT : out std_logic_vector (31 downto 0);
+ CLK_IN : in std_logic;
+ CLK_OUT : in std_logic;
+ TDC_DATA_VALID : in std_logic;
+ END_EVENT_MARKER_IN : in std_logic;
+ END_EVENT_MARKER_OUT : out std_logic);
+ end component;
+ component up_down_counter_16_bit
+ port (
+ QOUT : out std_logic_vector(15 downto 0);
+ UP : in std_logic;
+ DOWN : in std_logic;
+ CLK : in std_logic;
+ CLR : in std_logic
+ );
+ end component;
+ signal tdc_ready : std_logic;
+ signal write_eneble_and_tdc_ready : std_logic_vector(23 downto 0);
+ signal write_address : std_logic_vector(19 downto 0);
+ signal write_address_tdc_data : std_logic_vector(19 downto 0);
+ signal read_address : std_logic_vector(19 downto 0);
+ signal data_to_lvl1_fifo : std_logic_vector (31 downto 0);
+ signal tdc_ready_or_add_word : std_logic;
+ signal counter_a_i : std_logic_vector(31 downto 0);
+ signal counter_b_i : std_logic_vector(31 downto 0);
+ signal counter_c_i : std_logic_vector(31 downto 0);
+ signal counter_d_i : std_logic_vector(31 downto 0);
+ signal counter_e_i : std_logic_vector(31 downto 0);
+ signal counter_f_i : std_logic_vector(31 downto 0);
+ signal counter_g_i : std_logic_vector(31 downto 0);
+ signal counter_h_i : std_logic_vector(31 downto 0);
+ signal counter_i_i : std_logic_vector(31 downto 0);
+ signal counter_j_i : std_logic_vector(31 downto 0);
+ signal counter_k_i : std_logic_vector(31 downto 0);
+ signal counter_l_i : std_logic_vector(31 downto 0);
+ signal counter_m_i : std_logic_vector(31 downto 0);
+ signal add_data_counter : std_logic_vector(7 downto 0);
+ signal add_data_pulse : std_logic;
+ signal received_tdc_token_pulse : std_logic;
+ signal data_selector : std_logic_vector(4 downto 0);
+ signal saved_address : std_logic_vector(19 downto 0);
+ signal first_header : std_logic_vector(31 downto 0);
+ signal second_header : std_logic_vector(31 downto 0);
+ signal words_in_event : std_logic_vector(15 downto 0);
+ signal read_data_address_up : std_logic;
+ signal not_how_many_words_in_ram: std_logic;
+ signal next_kW_in_ram_pulse : std_logic;
+ signal etrax_read_one_kW_pulse : std_logic;
+ signal how_many_kW_in_ram : std_logic_vector(15 downto 0);
+ signal word_count_up : std_logic;
+ signal word_count_up_pulse : std_logic;
+ signal how_many_words_in_fifo : std_logic_vector(15 downto 0);
+ signal end_event_marker_in_i : std_logic;
+ signal end_event_marker_out_i : std_logic;
+ signal etrax_have_to_read_ram_i : std_logic;
+ signal how_many_words_in_ram : std_logic_vector(9 downto 0);
+ signal tdc_data_valid_i : std_logic;
+begin
+ SEND_TDC_TOKEN <= START_TDC_READOUT;
+ tdc_ready <= A_TDC_READY or B_TDC_READY or C_TDC_READY or D_TDC_READY;
+ GET_TDC_DATA <= '1';
+ LVL1_FIFO_16k_WORD : lvl1_fifo
+ port map (
+ RESET => RESET,
+ WRITE_ADDRESS => write_address,
+ READ_ADDRESS => read_address,
+ DATA_IN => data_to_lvl1_fifo,
+ DATA_OUT => TDC_DATA_OUT,
+ CLK_IN => TDC_CLK,
+ CLK_OUT => CLK,
+ TDC_DATA_VALID => tdc_ready_or_add_word,
+ END_EVENT_MARKER_IN => end_event_marker_in_i,
+ END_EVENT_MARKER_OUT => end_event_marker_out_i );
+ -----------------------------------------------------------------------------
+ ----------------------------------------------------------------------------
+ -- LVL1 logic only TDC_CLK domain
+ -----------------------------------------------------------------------------
+ -----------------------------------------------------------------------------
+ WRITE_ADDRESS_CHANGE : process (TDC_CLK, RESET)
+ begin
+ if rising_edge(TDC_CLK) then
+ if RESET = '1' then
+ write_address_tdc_data <= "000000000000" & HOW_MANY_ADD_DATA + 1; --+1_beacause_data_selector_count_to_0_!
+ elsif tdc_ready = '1' or add_data_pulse = '1' then
+ write_address_tdc_data <= write_address_tdc_data + 1;
+ else
+ write_address_tdc_data <= write_address_tdc_data;
+ end if;
+ end if;
+ end process WRITE_ADDRESS_CHANGE;
+ SAVE_DATA : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ counter_a_i <= (others => '0');
+ counter_b_i <= (others => '0');
+ counter_c_i <= (others => '0');
+ counter_d_i <= (others => '0');
+ counter_e_i <= (others => '0');
+ counter_f_i <= (others => '0');
+ counter_g_i <= (others => '0');
+ counter_h_i <= (others => '0');
+ counter_i_i <= (others => '0');
+ counter_j_i <= (others => '0');
+ counter_k_i <= (others => '0');
+ counter_l_i <= (others => '0');
+ counter_m_i <= (others => '0');
+ elsif START_TDC_READOUT = '1' then
+ counter_a_i <= COUNTER_a;
+ counter_b_i <= COUNTER_b;
+ counter_c_i <= COUNTER_c;
+ counter_d_i <= COUNTER_d;
+ counter_e_i <= COUNTER_e;
+ counter_f_i <= COUNTER_f;
+ counter_g_i <= COUNTER_g;
+ counter_h_i <= COUNTER_h;
+ counter_i_i <= COUNTER_i;
+ counter_j_i <= COUNTER_j;
+ counter_k_i <= COUNTER_k;
+ counter_l_i <= COUNTER_l;
+ counter_m_i <= COUNTER_m;
+ end if;
+ end if;
+ end process SAVE_DATA;
+
+ TOKEN_PULSE : edge_to_pulse
+ port map (
+ clock => TDC_CLK,
+ en_clk => '1',
+ signal_in => RECEIVED_TDC_TOKEN,
+ pulse => received_tdc_token_pulse);
+ ADD_DATA_PULSE_MAKE : process (TDC_CLK, RESET)
+ begin
+ if rising_edge(TDC_CLK) then
+ if RESET = '1' or add_data_counter = x"0" then
+ add_data_pulse <= '0';
+ elsif received_tdc_token_pulse = '1' then
+ add_data_pulse <= '1';
+ else
+ add_data_pulse <= add_data_pulse;
+ end if;
+ end if;
+ end process ADD_DATA_PULSE_MAKE;
+ data_selector <= add_data_pulse & add_data_counter(3 downto 0);
+ CHOOSE_DATA : process (TDC_CLK, RESET, data_selector)
+ begin
+-- if rising_edge(TDC_CLK) then
+ case data_selector is
+ when "10000" => data_to_lvl1_fifo <= first_header;
+ when "10001" => data_to_lvl1_fifo <= second_header;
+ when "10010" => data_to_lvl1_fifo <= counter_a_i;
+ when "10011" => data_to_lvl1_fifo <= counter_b_i;
+ when "10100" => data_to_lvl1_fifo <= counter_c_i;
+ when "10101" => data_to_lvl1_fifo <= counter_d_i;
+ when "10110" => data_to_lvl1_fifo <= counter_e_i;
+ when "10111" => data_to_lvl1_fifo <= counter_f_i;
+ when "11000" => data_to_lvl1_fifo <= counter_g_i;
+ when "11001" => data_to_lvl1_fifo <= counter_h_i;
+ when "11010" => data_to_lvl1_fifo <= counter_i_i;
+ when "11011" => data_to_lvl1_fifo <= counter_j_i;
+ when "11100" => data_to_lvl1_fifo <= counter_k_i;
+ when "11101" => data_to_lvl1_fifo <= counter_l_i;
+ when "11110" => data_to_lvl1_fifo <= counter_m_i;
+ when others => data_to_lvl1_fifo <= TDC_DATA_IN;
+ end case;
+ -- end if;
+ end process CHOOSE_DATA;
+ end_event_marker_in_i <= '1' when data_selector = "10001" else '0';
+ TDC_READOUT_COMPLETED <= end_event_marker_in_i;
+ ADD_DATA_COUNTER_CONTROL : process (TDC_CLK, RESET)
+ begin
+ if rising_edge(TDC_CLK) then
+ if RESET = '1' or START_TDC_READOUT = '1' then
+ add_data_counter <= HOW_MANY_ADD_DATA + 1;
+ saved_address <= write_address_tdc_data;
+ elsif add_data_pulse = '1' then
+ add_data_counter <= add_data_counter - 1;
+ saved_address <= saved_address - 1;
+ else
+ add_data_counter <= add_data_counter;
+ saved_address <= saved_address;
+ end if;
+ end if;
+ end process ADD_DATA_COUNTER_CONTROL;
+ tdc_ready_or_add_word <= tdc_ready or add_data_pulse;
+
+ COUNT_WORDS_IN_EVENT : process (TDC_CLK, RESET)
+ begin
+ if rising_edge(TDC_CLK) then
+ if RESET = '1' or START_TDC_READOUT = '1' then
+ words_in_event <= x"0000";
+ elsif tdc_ready_or_add_word = '1' then
+ words_in_event <= words_in_event +1;
+ else
+ words_in_event <= words_in_event;
+ end if;
+ end if;
+ end process COUNT_WORDS_IN_EVENT;
+ first_header <= x"f" & LVL1_TAG & LVL1_CODE & words_in_event;
+ second_header <= x"00" & x"00" & x"00" & HOW_MANY_ADD_DATA;
+ write_address <= write_address_tdc_data when add_data_pulse = '0' else saved_address;
+ -----------------------------------------------------------------------------
+ ----------------------------------------------------------------------------
+ -- LVL2 logic (only CLK domain)
+ -----------------------------------------------------------------------------
+ -----------------------------------------------------------------------------
+
+ MAKE_LVL2_PULSE : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' or end_event_marker_out_i = '1' then
+ tdc_data_valid_i <= '0';
+ read_data_address_up <= '0';
+ elsif LVL2_TRIGGER = "11" and tdc_data_valid_i = '0' then
+ tdc_data_valid_i <= '1';
+ read_data_address_up <= '1';
+ elsif LVL2_TRIGGER = "10" and tdc_data_valid_i = '0' then
+ tdc_data_valid_i <= '0';
+ read_data_address_up <= '1';
+ else
+ tdc_data_valid_i <= tdc_data_valid_i;
+ read_data_address_up <= read_data_address_up;
+ end if;
+ end if;
+ end process MAKE_LVL2_PULSE;
+ TDC_DATA_VALID <= tdc_data_valid_i;
+ READ_ADDRESS_CHANGE : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ read_address <= (others => '0');
+ elsif read_data_address_up = '1' then
+ read_address <= read_address + 1;
+ else
+ read_address <= read_address;
+ end if;
+ end if;
+ end process READ_ADDRESS_CHANGE;
+ not_how_many_words_in_ram <= not how_many_words_in_ram(9);
+ COUNT_WORDS_IN_RAM: process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ how_many_words_in_ram <= (others => '0');
+ elsif tdc_data_valid_i = '1' then
+ how_many_words_in_ram <= how_many_words_in_ram +1;
+ end if;
+ end if;
+ end process COUNT_WORDS_IN_RAM;
+ NEXT_ONE_kW_IN_RAM_PULSE : edge_to_pulse
+ port map (
+ clock => CLK,
+ en_clk => '1',
+ signal_in => not_how_many_words_in_ram,
+ pulse => next_kW_in_ram_pulse);
+ ETRAX_HAS_READ_kW : edge_to_pulse
+ port map (
+ clock => CLK,
+ en_clk => '1',
+ signal_in => ETRAX_READ_ONE_kW,
+ pulse => etrax_read_one_kW_pulse);
+ DIFF_kW_WRITE_READ : up_down_counter_16_bit
+ port map (
+ QOUT => how_many_kW_in_ram,
+ UP => next_kW_in_ram_pulse,
+ DOWN => etrax_read_one_kW_pulse,
+ CLK => CLK,
+ CLR => RESET);
+ etrax_have_to_read_ram_i <= '1' when how_many_kW_in_ram /= x"0000" and ETRAX_IS_READY_TO_READ = '1' and read_data_address_up = '0' else '0';
+ ETRAX_HAS_TO_READ_EVENT <= etrax_have_to_read_ram_i;
+ TDC_LVL2_BUSY_ETRAX_ACCESS : process (CLK, RESET) --create lvl2 fifo trigg
+ --if there is no lvl2 fifo
+ --!!! ??
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' or etrax_read_one_kW_pulse = '1' then
+ TDC_LVL2_BUSY <= '0';
+ elsif etrax_have_to_read_ram_i = '1' then
+ TDC_LVL2_BUSY <= '1';
+ end if;
+ end if;
+ end process TDC_LVL2_BUSY_ETRAX_ACCESS;
+ -----------------------------------------------------------------------------
+ ----------------------------------------------------------------------------
+ -- Mixed LVL1 and LVL2
+ -----------------------------------------------------------------------------
+ -----------------------------------------------------------------------------
+ word_count_up <= TDC_CLK and tdc_ready_or_add_word;
+ NEXT_ONE_WORD_IN_LVL1_FIFO : edge_to_pulse
+ port map (
+ clock => CLK,
+ en_clk => '1',
+ signal_in => word_count_up,
+ pulse => word_count_up_pulse);
+ DIFF_WORD_WRITE_READ : up_down_counter_16_bit
+ port map (
+ QOUT => how_many_words_in_fifo,
+ UP => word_count_up,
+ DOWN => read_data_address_up,
+ CLK => CLK,
+ CLR => RESET);
+ TDC_LVL1_BUSY <= '1' when how_many_words_in_fifo > "0011111111111111" else '0';
+ --set
+ --to
+ --max
+ --value
+ --!!!!!!! and cut data funktion should
+ --be implemented - with busy or max
+ --size or last event ? or both
+
+ -----------------------------------------------------------------------------
+ -- end writing to fifo when TDC_LVL1_BUSY and read all data and send finish signal
+ -----------------------------------------------------------------------------
+
+
+end tdc_interface;
--- /dev/null
+ # NET ADDON_TO_TRB_CLKINN LOC = G16;
+ # NET ADDON_TO_TRB_CLKINP LOC = G17;
+ # NET ADO_LV<0> LOC = N19;
+ # NET ADO_LV<1> LOC = N18;
+ # NET ADO_LV<2> LOC = L15;
+ # NET ADO_LV<3> LOC = L14;
+ # NET ADO_LV<4> LOC = E21;
+ # NET ADO_LV<5> LOC = D21;
+ # NET ADO_LV<6> LOC = J14;
+ # NET ADO_LV<7> LOC = K14;
+ # NET ADO_LV<8> LOC = N20;
+ # NET ADO_LV<9> LOC = M20;
+ # NET ADO_LV<10> LOC = H14;
+ # NET ADO_LV<11> LOC = H13;
+ # NET ADO_LV<12> LOC = H22;
+ # NET ADO_LV<13> LOC = J21;
+ # NET ADO_LV<14> LOC = K16;
+ # NET ADO_LV<15> LOC = L16;
+ # NET ADO_LV<16> LOC = J20;
+ # NET ADO_LV<17> LOC = L19;
+ # NET ADO_LV<18> LOC = H15;
+ # NET ADO_LV<19> LOC = J15;
+ # NET ADO_LV<20> LOC = G21;
+ # NET ADO_LV<21> LOC = H20;
+ # NET ADO_LV<22> LOC = G15;
+ # NET ADO_LV<23> LOC = F14;
+ # NET ADO_LV<24> LOC = F21;
+ # NET ADO_LV<25> LOC = F20;
+ # NET ADO_LV<26> LOC = A15;
+ # NET ADO_LV<27> LOC = B15;
+ # NET ADO_LV<28> LOC = AE3;
+ # NET ADO_LV<29> LOC = AE2;
+ # NET ADO_LV<30> LOC = AD6;
+ # NET ADO_LV<31> LOC = AD5;
+ # NET ADO_LV<32> LOC = AC7;
+ # NET ADO_LV<33> LOC = AB8;
+ # NET ADO_LV<34> LOC = Y16;
+ # NET ADO_LV<35> LOC = AA15;
+ # NET ADO_LV<36> LOC = AE4;
+ # NET ADO_LV<37> LOC = AD4;
+ # NET ADO_LV<38> LOC = AH3;
+ # NET ADO_LV<39> LOC = AH2;
+ # NET ADO_LV<40> LOC = AG2;
+ # NET ADO_LV<41> LOC = AG1;
+ # NET ADO_LV<42> LOC = AK3;
+ # NET ADO_LV<43> LOC = AK2;
+ # NET ADO_LV<44> LOC = AF8;
+ # NET ADO_LV<45> LOC = AE8;
+ # NET ADO_LV<46> LOC = AH5;
+ # NET ADO_LV<47> LOC = AH4;
+ # NET ADO_LV<48> LOC = AB13;
+ # NET ADO_LV<49> LOC = AB12;
+ # NET ADO_LV<50> LOC = AM2;
+ # NET ADO_LV<51> LOC = AM1;
+ # NET ADO_LV<52> LOC = AG8;
+ # NET ADO_LV<53> LOC = AG7;
+ # NET ADO_LV<54> LOC = AM3;
+ # NET ADO_LV<55> LOC = AL3;
+ # NET ADO_LV<56> LOC = AC5;
+ # NET ADO_LV<57> LOC = AC4;
+ # NET ADO_LV<58> LOC = AF1;
+ # NET ADO_LV<59> LOC = AE1;
+ # NET ADO_LV<60> LOC = AA9;
+ # NET ADO_LV<61> LOC = AA8;
+ NET ADO_TTL<0> LOC = "AL11"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<1> LOC = "AL10"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<2> LOC = "AE11"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<3> LOC = "AF11"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<4> LOC = "AM12"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<5> LOC = "AM11"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<6> LOC = "AL9"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<7> LOC = "AK9"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<8> LOC = "AP11"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<9> LOC = "AP10"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<10> LOC = "AH10"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<11> LOC = "AG10"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<12> LOC = "AN12"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<13> LOC = "AP12"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<14> LOC = "AP9"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<15> LOC = "AN9"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<16> LOC = "AH12"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<17> LOC = "AG11"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<18> LOC = "AN7"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<19> LOC = "AM7"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<20> LOC = "AN10"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<21> LOC = "AM10"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<22> LOC = "AF10"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<23> LOC = "AE9"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<24> LOC = "AJ12"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<25> LOC = "L33"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<26> LOC = "L34"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<27> LOC = "M32"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<28> LOC = "M33"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<29> LOC = "G6"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<30> LOC = "E14"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<31> LOC = "D14"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<32> LOC = "B3"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<33> LOC = "B2"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<34> LOC = "AL20"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<35> LOC = "AJ15"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<36> LOC = "AJ14"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<37> LOC = "AG20"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<38> LOC = "AH20"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<39> LOC = "AG15"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<40> LOC = "AH14"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<41> LOC = "AD19"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<42> LOC = "AE19"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<43> LOC = "C28"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<44> LOC = "L26"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<45> LOC = "B32"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<46> LOC = "B33"| IOSTANDARD = "LVTTL";
+ # NET A_CS1B LOC = P9;
+ # NET A_CS<1> LOC = P10;
+# NET A_DATA_READY LOC = "B12";
+ NET A_RESERVED LOC = "J11" | IOSTANDARD = "LVTTL";
+ # NET A_SCK LOC = H3;
+ # NET A_SCKB LOC = H2;
+ # NET A_SDI LOC = F1;
+ # NET A_SDIB LOC = G1;
+ # NET A_SDO LOC = J4;
+ # NET A_SDOB LOC = K4;
+# NET A_TDC_ERROR LOC = "F11";
+# NET A_TDC_POWERUP LOC = "H8";
+ NET A_TEMP LOC = "B7" | IOSTANDARD = "LVTTL";
+ # NET A_TEST1B LOC = N7;
+ # NET A_TEST2B LOC = L4;
+ # NET A_TEST1 LOC = M7;
+ # NET A_TEST2 LOC = L5;
+# NET A_TRIGGER LOC = "J6";
+# NET A_TRIGGERB LOC = "J5";
+ # NET B_CS1B LOC = G5;
+ # NET B_CS<1> LOC = F5;
+# NET B_DATA_READY LOC = "A8";
+ NET B_RESERVED LOC = "C7" | IOSTANDARD = "LVTTL";
+ # NET B_SCK LOC = C4;
+ # NET B_SCKB LOC = C3;
+ # NET B_SDI LOC = R11;
+ # NET B_SDIB LOC = T11;
+ # NET B_SDO LOC = J2;
+ # NET B_SDOB LOC = J1;
+# NET B_TDC_ERROR LOC = "A6";
+# NET B_TDC_POWERUP LOC = "H7";
+ NET B_TEMP LOC = "A10" | IOSTANDARD = "LVTTL";
+ # NET B_TEST2B LOC = L9;
+ # NET B_TEST1B LOC = E4;
+ # NET B_TEST1 LOC = D4;
+ # NET B_TEST2 LOC = M10;
+# NET B_TRIGGER LOC = "H5";
+# NET B_TRIGGERB LOC = "H4";
+ # NET C_CS1B LOC = R9;
+ # NET C_CS<1> LOC = T10;
+# NET C_DATA_READY LOC = "B8";
+ NET C_RESERVED LOC = "F8" | IOSTANDARD = "LVTTL";
+ # NET C_SCK LOC = P7;
+ # NET C_SCKB LOC = P6;
+ # NET C_SDI LOC = D1;
+ # NET C_SDIB LOC = E1;
+ # NET C_SDO LOC = F4;
+ # NET C_SDOB LOC = F3;
+# NET C_TDC_ERROR LOC = "B6";
+# NET C_TDC_POWERUP LOC = "K8";
+ NET C_TEMP LOC = "A9" | IOSTANDARD = "LVTTL";
+ # NET C_TEST2B LOC = N12;
+ # NET C_TEST1B LOC = D2;
+ # NET C_TEST1 LOC = C2;
+ # NET C_TEST2 LOC = N13;
+# NET C_TOKEN_OUT_TTL LOC = "F6";
+# NET C_TRIGGER LOC = "N10";
+# NET C_TRIGGERB LOC = "N9";
+ NET DBAD LOC = "M28" | IOSTANDARD = "LVTTL";
+ NET DGOOD LOC = "H34" | IOSTANDARD = "LVTTL";
+ NET DINT LOC = "L31" | IOSTANDARD = "LVTTL";
+# NET DSPADDR<0> LOC = "AA23"| IOSTANDARD = "LVTTL";
+# NET DSPADDR<1> LOC = "AA24"| IOSTANDARD = "LVTTL";
+# NET DSPADDR<2> LOC = "AJ34"| IOSTANDARD = "LVTTL";
+# NET DSPADDR<3> LOC = "AH34"| IOSTANDARD = "LVTTL";
+# NET DSPADDR<4> LOC = "AD27"| IOSTANDARD = "LVTTL";
+# NET DSPADDR<5> LOC = "AC27"| IOSTANDARD = "LVTTL";
+# NET DSPADDR<6> LOC = "AB25"| IOSTANDARD = "LVTTL";
+# NET DSPADDR<7> LOC = "AB26"| IOSTANDARD = "LVTTL";
+# NET DSPADDR<8> LOC = "AG30"| IOSTANDARD = "LVTTL";
+# NET DSPADDR<9> LOC = "AG31"| IOSTANDARD = "LVTTL";
+# NET DSPADDR<10> LOC = "AH32"| IOSTANDARD = "LVTTL";
+# NET DSPADDR<11> LOC = "AH33"| IOSTANDARD = "LVTTL";
+# NET DSPADDR<12> LOC = "AC25"| IOSTANDARD = "LVTTL";
+# NET DSPADDR<13> LOC = "AD26"| IOSTANDARD = "LVTTL";
+# NET DSPADDR<14> LOC = "AF29"| IOSTANDARD = "LVTTL";
+# NET DSPADDR<15> LOC = "AF30"| IOSTANDARD = "LVTTL";
+# NET DSPADDR<16> LOC = "AA28"| IOSTANDARD = "LVTTL";
+# NET DSPADDR<17> LOC = "AA29"| IOSTANDARD = "LVTTL";
+# NET DSPADDR<18> LOC = "W24"| IOSTANDARD = "LVTTL";
+# NET DSPADDR<19> LOC = "Y24"| IOSTANDARD = "LVTTL";
+# NET DSPADDR<20> LOC = "AB30"| IOSTANDARD = "LVTTL";
+# NET DSPADDR<21> LOC = "AA30"| IOSTANDARD = "LVTTL";
+# NET DSPADDR<22> LOC = "W25"| IOSTANDARD = "LVTTL";
+# NET DSPADDR<23> LOC = "Y26"| IOSTANDARD = "LVTTL";
+# NET DSPADDR<24> LOC = "AE33"| IOSTANDARD = "LVTTL";
+# NET DSPADDR<25> LOC = "AE34"| IOSTANDARD = "LVTTL";
+# NET DSPADDR<26> LOC = "AC32"| IOSTANDARD = "LVTTL";
+# NET DSPADDR<27> LOC = "AC33"| IOSTANDARD = "LVTTL";
+# NET DSPADDR<28> LOC = "AC29"| IOSTANDARD = "LVTTL";
+# NET DSPADDR<29> LOC = "AC30"| IOSTANDARD = "LVTTL";
+# NET DSPADDR<30> LOC = "AD34"| IOSTANDARD = "LVTTL";
+# NET DSPADDR<31> LOC = "AC34"| IOSTANDARD = "LVTTL";
+# NET DSPDAT<0> LOC = "AA25"| IOSTANDARD = "LVTTL";
+# NET DSPDAT<1> LOC = "AA26"| IOSTANDARD = "LVTTL";
+# NET DSPDAT<2> LOC = "AE32"| IOSTANDARD = "LVTTL";
+# NET DSPDAT<3> LOC = "AD32"| IOSTANDARD = "LVTTL";
+# NET DSPDAT<4> LOC = "AC28"| IOSTANDARD = "LVTTL";
+# NET DSPDAT<5> LOC = "AB28"| IOSTANDARD = "LVTTL";
+# NET DSPDAT<6> LOC = "AD30"| IOSTANDARD = "LVTTL";
+# NET DSPDAT<7> LOC = "AD31"| IOSTANDARD = "LVTTL";
+# NET DSPDAT<8> LOC = "AG32"| IOSTANDARD = "LVTTL";
+# NET DSPDAT<9> LOC = "AG33"| IOSTANDARD = "LVTTL";
+# NET DSPDAT<10> LOC = "AF33"| IOSTANDARD = "LVTTL";
+# NET DSPDAT<11> LOC = "AF34"| IOSTANDARD = "LVTTL";
+# NET DSPDAT<12> LOC = "AE29"| IOSTANDARD = "LVTTL";
+# NET DSPDAT<13> LOC = "AD29"| IOSTANDARD = "LVTTL";
+# NET DSPDAT<14> LOC = "AF31"| IOSTANDARD = "LVTTL";
+# NET DSPDAT<15> LOC = "AE31"| IOSTANDARD = "LVTTL";
+# NET DSPDAT<16> LOC = "AK31"| IOSTANDARD = "LVTTL";
+# NET DSPDAT<17> LOC = "AK32"| IOSTANDARD = "LVTTL";
+# NET DSPDAT<18> LOC = "AK33"| IOSTANDARD = "LVTTL";
+# NET DSPDAT<19> LOC = "AK34"| IOSTANDARD = "LVTTL";
+# NET DSPDAT<20> LOC = "AM32"| IOSTANDARD = "LVTTL";
+# NET DSPDAT<21> LOC = "AM33"| IOSTANDARD = "LVTTL";
+# NET DSPDAT<22> LOC = "AJ31"| IOSTANDARD = "LVTTL";
+# NET DSPDAT<23> LOC = "AJ32"| IOSTANDARD = "LVTTL";
+# NET DSPDAT<24> LOC = "AB22"| IOSTANDARD = "LVTTL";
+# NET DSPDAT<25> LOC = "AB23"| IOSTANDARD = "LVTTL";
+# NET DSPDAT<26> LOC = "AL33"| IOSTANDARD = "LVTTL";
+# NET DSPDAT<27> LOC = "AL34"| IOSTANDARD = "LVTTL";
+# NET DSPDAT<28> LOC = "AM31"| IOSTANDARD = "LVTTL";
+# NET DSPDAT<29> LOC = "AL31"| IOSTANDARD = "LVTTL";
+# NET DSPDAT<30> LOC = "AJ30"| IOSTANDARD = "LVTTL";
+# NET DSPDAT<31> LOC = "AH30"| IOSTANDARD = "LVTTL";
+ NET DSP_ACK LOC = "AB15" | IOSTANDARD = "LVTTL";
+ NET DSP_BM LOC = "AL16" | IOSTANDARD = "LVTTL";
+ # NET DSP_BMS LOC = AF15;
+ # NET DSP_BOFF LOC = AK14;
+ NET DSP_BRST LOC = "AN20" | IOSTANDARD = "LVTTL";
+ # NET DSP_BUSLOCK LOC = AC19;
+ # NET DSP_DMAR<0> LOC = AD17;
+ # NET DSP_DMAR<1> LOC = AC17;
+ # NET DSP_DMAR<2> LOC = AM20;
+ # NET DSP_DMAR<3> LOC = AL19;
+ # NET DSP_FLAG<0> LOC = AE21;
+ # NET DSP_FLAG<1> LOC = AF21;
+ # NET DSP_FLAG<2> LOC = AP15;
+ # NET DSP_FLAG<3> LOC = AN15;
+ NET DSP_HBG LOC = "AD16" | IOSTANDARD = "LVTTL";
+ NET DSP_HBR LOC = "AB18" | IOSTANDARD = "LVTTL";
+ # NET DSP_IOEN LOC = AL18;
+ # NET DSP_IORD LOC = AB16;
+ # NET DSP_IOWR LOC = AB17;
+ # NET DSP_IRQ<0> LOC = AG21;
+ # NET DSP_IRQ<1> LOC = AF20;
+ # NET DSP_IRQ<2> LOC = AF14;
+ # NET DSP_IRQ<3> LOC = AG13;
+ # NET DSP_L1DATIP<0> LOC = AK29;
+ # NET DSP_L0ACKI LOC = AM18;
+ # NET DSP_L1ACKO LOC = AM15;
+ # NET DSP_L0BCMPI LOC = AM16;
+ # NET DSP_L0BCMPO LOC = AD21;
+ # NET DSP_L1DATIN<0> LOC = AJ29;
+ # NET DSP_L1BCMPO LOC = AJ20;
+ # NET DSP_L1DATOP<0> LOC = AK21;
+ # NET DSP_L0DATON<0> LOC = AM23;
+ # NET DSP_L0ACKO LOC = AM17;
+ # NET DSP_L1CLKINN LOC = AL30;
+ # NET DSP_L1CLKOUTP LOC = AM21;
+ # NET DSP_L0DATIN<0> LOC = AM25;
+ # NET DSP_L0CLKINP LOC = AP29;
+ # NET DSP_L1CLKOUTN LOC = AM22;
+ # NET DSP_L1BCMPI LOC = AL15;
+ # NET DSP_L0CLKOUTN LOC = AL25;
+ # NET DSP_L1CLKINP LOC = AM30;
+ # NET DSP_L0DATOP<0> LOC = AL23;
+ # NET DSP_L1ACKI LOC = AD20;
+ # NET DSP_L0CLKINN LOC = AN29;
+ # NET DSP_L0DATIP<0> LOC = AN25;
+ # NET DSP_L1DATON<0> LOC = AL21;
+ # NET DSP_L0CLKOUTP LOC = AL24;
+ # NET DSP_L0DATIN<1> LOC = AN24;
+ # NET DSP_L1DATIP<1> LOC = AF28;
+ # NET DSP_L1DATIN<1> LOC = AE27;
+ # NET DSP_L0DATON<1> LOC = AN23;
+ # NET DSP_L0DATOP<1> LOC = AN22;
+ # NET DSP_L1DATOP<1> LOC = AH28;
+ # NET DSP_L0DATIP<1> LOC = AP24;
+ # NET DSP_L1DATON<1> LOC = AH29;
+ # NET DSP_L0DATON<2> LOC = AH25;
+ # NET DSP_L0DATOP<2> LOC = AJ25;
+ # NET DSP_L1DATIP<2> LOC = AF26;
+ # NET DSP_L1DATOP<2> LOC = AP30;
+ # NET DSP_L0DATIP<2> LOC = AM26;
+ # NET DSP_L1DATIN<2> LOC = AE26;
+ # NET DSP_L1DATON<2> LOC = AN30;
+ # NET DSP_L0DATIN<2> LOC = AM27;
+ # NET DSP_L1DATIP<3> LOC = AN32;
+ # NET DSP_L0DATIP<3> LOC = AP21;
+ # NET DSP_L0DATOP<3> LOC = AL26;
+ # NET DSP_L0DATIN<3> LOC = AP22;
+ # NET DSP_L1DATON<3> LOC = AG28;
+ # NET DSP_L1DATOP<3> LOC = AG27;
+ # NET DSP_L1DATIN<3> LOC = AN33;
+ # NET DSP_L0DATON<3> LOC = AK26;
+ # NET DSP_MSH LOC = AL14;
+ NET DSP_RD LOC = "AJ22" | IOSTANDARD = "LVTTL";
+ NET DSP_RESET LOC = "AG22"| IOSTANDARD = "LVTTL";
+ # NET DSP_RESET_OUT LOC = AH22;
+ # NET DSP_TMROE LOC = AP20;
+ NET DSP_WRH LOC = "AJ21"| IOSTANDARD = "LVTTL";
+ NET DSP_WRL LOC = "AC15"| IOSTANDARD = "LVTTL";
+ NET DWAIT LOC = "H33" | IOSTANDARD = "LVTTL";
+ # NET D_CS1B LOC = M2;
+ # NET D_CS<1> LOC = M3;
+# NET D_DATA_READY LOC = "E11";
+ NET D_RESERVED LOC = "G8" | IOSTANDARD = "LVTTL";
+ # NET D_SCK LOC = M6;
+ # NET D_SCKB LOC = M5;
+ # NET D_SDI LOC = K3;
+ # NET D_SDIB LOC = L3;
+ # NET D_SDO LOC = K2;
+ # NET D_SDOB LOC = K1;
+# NET D_TDC_ERROR LOC = "H12";
+# NET D_TDC_POWERUP LOC = "J7";
+ NET D_TEMP LOC = "C14" | IOSTANDARD = "LVTTL";
+ # NET D_TEST1B LOC = M1;
+ # NET D_TEST2B LOC = P5;
+ # NET D_TEST1 LOC = L1;
+ # NET D_TEST2 LOC = N5;
+# NET D_TRIGGER LOC = "P12";
+# NET D_TRIGGERB LOC = "P11";
+ NET ETRAX_IRQ LOC = "AK12" | IOSTANDARD = "LVTTL";
+ NET FS_PB<0> LOC = "AL5" | IOSTANDARD = "LVTTL";
+ NET FS_PB<1> LOC = "AL4" | IOSTANDARD = "LVTTL";
+ NET FS_PB<2> LOC = "AK4" | IOSTANDARD = "LVTTL";
+ NET FS_PB<3> LOC = "AJ4" | IOSTANDARD = "LVTTL";
+ NET FS_PB<4> LOC = "AP4" | IOSTANDARD = "LVTTL";
+ NET FS_PB<5> LOC = "AN4" | IOSTANDARD = "LVTTL";
+ NET FS_PB<6> LOC = "AD10" | IOSTANDARD = "LVTTL";
+ NET FS_PB<7> LOC = "AD9" | IOSTANDARD = "LVTTL";
+ NET FS_PB<8> LOC = "AN14" | IOSTANDARD = "LVTTL";
+ NET FS_PB<9> LOC = "AP14" | IOSTANDARD = "LVTTL";
+ NET FS_PB<10> LOC = "AJ6" | IOSTANDARD = "LVTTL";
+ NET FS_PB<11> LOC = "AJ5" | IOSTANDARD = "LVTTL";
+ NET FS_PB<12> LOC = "AK7" | IOSTANDARD = "LVTTL";
+ NET FS_PB<13> LOC = "AJ7" | IOSTANDARD = "LVTTL";
+ NET FS_PB<14> LOC = "AN3" | IOSTANDARD = "LVTTL";
+ NET FS_PB<15> LOC = "AN2" | IOSTANDARD = "LVTTL";
+ NET FS_PB<16> LOC = "AK13" | IOSTANDARD = "LVTTL";
+ NET FS_PB<17> LOC = "AL13" | IOSTANDARD = "LVTTL";
+ NET FS_PC<0> LOC = "AL6" | IOSTANDARD = "LVTTL";
+ NET FS_PC<1> LOC = "AK6" | IOSTANDARD = "LVTTL";
+ NET FS_PC<2> LOC = "AL8" | IOSTANDARD = "LVTTL";
+ NET FS_PC<3> LOC = "AK8" | IOSTANDARD = "LVTTL";
+ NET FS_PC<4> LOC = "AH8" | IOSTANDARD = "LVTTL";
+ NET FS_PC<5> LOC = "AH7" | IOSTANDARD = "LVTTL";
+ NET FS_PC<6> LOC = "AM13" | IOSTANDARD = "LVTTL";
+ NET FS_PC<7> LOC = "AN13" | IOSTANDARD = "LVTTL";
+ NET FS_PC<8> LOC = "AM6" | IOSTANDARD = "LVTTL";
+ NET FS_PC<9> LOC = "AM5" | IOSTANDARD = "LVTTL";
+ NET FS_PC<10> LOC = "AJ10" | IOSTANDARD = "LVTTL";
+ NET FS_PC<11> LOC = "AJ9" | IOSTANDARD = "LVTTL";
+ NET FS_PC<12> LOC = "AP5" | IOSTANDARD = "LVTTL";
+ NET FS_PC<13> LOC = "AN5" | IOSTANDARD = "LVTTL";
+ NET FS_PC<14> LOC = "AP6" | IOSTANDARD = "LVTTL";
+ NET FS_PC<15> LOC = "AP7" | IOSTANDARD = "LVTTL";
+ NET FS_PC<16> LOC = "AM8" | IOSTANDARD = "LVTTL";
+ NET FS_PC<17> LOC = "AN8" | IOSTANDARD = "LVTTL";
+ # NET FS_PE<0> LOC = V18;
+ # NET FS_PE<1> LOC = V13;
+ # NET FS_PE<2> LOC = V14;
+ # NET FS_PE<3> LOC = W17;
+# NET GET_DATA LOC = "B13";
+ # NET GND LOC = V22;
+# NET REF_TDC_CLK LOC = "F18";
+# NET REF_TDC_CLKB LOC = "G18";
+ NET RESET_VIRT LOC = "AK16"| IOSTANDARD = "LVTTL";
+ # NET SFP_LOS LOC = M27;
+ # NET SFP_MOD<0> LOC = R23;
+ # NET SFP_MOD<1> LOC = K32;
+ # NET SFP_MOD<2> LOC = K33;
+ # NET SFP_RATE_SEL LOC = P27;
+ NET SFP_TX_DIS LOC = "N27"| IOSTANDARD = "LVTTL";
+ # NET SFP_TX_FAULT LOC = J32;
+# NET TDC_BU_RESET LOC = "AK27";
+# NET TDC_BU_RESETB LOC = "AK28";
+# NET TDC_EV_RESET LOC = "K6";
+# NET TDC_EV_RESETB LOC = "L6";
+# NET TDC_OUT<0> LOC = "D12";
+# NET TDC_OUT<1> LOC = "C12";
+# NET TDC_OUT<2> LOC = "B10";
+# NET TDC_OUT<3> LOC = "C10";
+# NET TDC_OUT<4> LOC = "A11";
+# NET TDC_OUT<5> LOC = "B11";
+# NET TDC_OUT<6> LOC = "C9";
+# NET TDC_OUT<7> LOC = "C8";
+# NET TDC_OUT<8> LOC = "G12";
+# NET TDC_OUT<9> LOC = "G11";
+# NET TDC_OUT<10> LOC = "F10";
+# NET TDC_OUT<11> LOC = "G10";
+# NET TDC_OUT<12> LOC = "D11";
+# NET TDC_OUT<13> LOC = "D10";
+# NET TDC_OUT<14> LOC = "H10";
+# NET TDC_OUT<15> LOC = "H9";
+# NET TDC_OUT<16> LOC = "A14";
+# NET TDC_OUT<17> LOC = "A13";
+# NET TDC_OUT<18> LOC = "D7";
+# NET TDC_OUT<19> LOC = "D6";
+# NET TDC_OUT<20> LOC = "D9";
+# NET TDC_OUT<21> LOC = "E9";
+# NET TDC_OUT<22> LOC = "A4";
+# NET TDC_OUT<23> LOC = "A3";
+# NET TDC_OUT<24> LOC = "E13";
+# NET TDC_OUT<25> LOC = "E12";
+# NET TDC_OUT<26> LOC = "A5";
+# NET TDC_OUT<27> LOC = "B5";
+# NET TDC_OUT<28> LOC = "E8";
+# NET TDC_OUT<29> LOC = "E7";
+# NET TDC_OUT<30> LOC = "J9";
+# NET TDC_OUT<31> LOC = "K9";
+ NET TDC_RESET LOC = "C5" | IOSTANDARD = "LVTTL";
+ NET TLK_CLK LOC = "R22" | IOSTANDARD = "LVTTL";
+# NET "TLK_CLK" TNM_NET = "TLK_CLK";
+# TIMESPEC "TS_TLK_CLK" = PERIOD "TLK_CLK" 10 ns HIGH 50 %;
+ NET TLK_ENABLE LOC = "R24" | IOSTANDARD = "LVTTL";
+ NET TLK_LCKREFN LOC = "L28" | IOSTANDARD = "LVTTL";
+ NET TLK_LOOPEN LOC = "R19" | IOSTANDARD = "LVTTL";
+ NET TLK_PRBSEN LOC = "H32" | IOSTANDARD = "LVTTL";
+ NET TLK_RXD<0> LOC = "G30" | IOSTANDARD = "LVTTL";
+ NET TLK_RXD<1> LOC = "G31" | IOSTANDARD = "LVTTL";
+ NET TLK_RXD<2> LOC = "J29" | IOSTANDARD = "LVTTL";
+ NET TLK_RXD<3> LOC = "J30" | IOSTANDARD = "LVTTL";
+ NET TLK_RXD<4> LOC = "E32" | IOSTANDARD = "LVTTL";
+ NET TLK_RXD<5> LOC = "E33" | IOSTANDARD = "LVTTL";
+ NET TLK_RXD<6> LOC = "N25" | IOSTANDARD = "LVTTL";
+ NET TLK_RXD<7> LOC = "P26" | IOSTANDARD = "LVTTL";
+ NET TLK_RXD<8> LOC = "P22" | IOSTANDARD = "LVTTL";
+ NET TLK_RXD<9> LOC = "R21" | IOSTANDARD = "LVTTL";
+ NET TLK_RXD<10> LOC = "F33" | IOSTANDARD = "LVTTL";
+ NET TLK_RXD<11> LOC = "F34" | IOSTANDARD = "LVTTL";
+ NET TLK_RXD<12> LOC = "K28" | IOSTANDARD = "LVTTL";
+ NET TLK_RXD<13> LOC = "K29" | IOSTANDARD = "LVTTL";
+ NET TLK_RXD<14> LOC = "G32" | IOSTANDARD = "LVTTL";
+ NET TLK_RXD<15> LOC = "G33" | IOSTANDARD = "LVTTL";
+ NET TLK_RX_CLK LOC = "L30" | IOSTANDARD = "LVTTL";
+# NET "TLK_RX_CLK" TNM_NET = "TLK_RX_CLK";
+# TIMESPEC "TS_TLK_RX_CLK" = PERIOD "TLK_RX_CLK" 10 ns HIGH 50 %;
+ NET TLK_RX_DV LOC = "M30" | IOSTANDARD = "LVTTL";
+ NET TLK_RX_ER LOC = "P20" | IOSTANDARD = "LVTTL";
+ NET TLK_TXD<0> LOC = "H27" | IOSTANDARD = "LVTTL";
+ NET TLK_TXD<1> LOC = "H28" | IOSTANDARD = "LVTTL";
+ NET TLK_TXD<2> LOC = "C32" | IOSTANDARD = "LVTTL";
+ NET TLK_TXD<3> LOC = "D32" | IOSTANDARD = "LVTTL";
+ NET TLK_TXD<4> LOC = "J27" | IOSTANDARD = "LVTTL";
+ NET TLK_TXD<5> LOC = "K27" | IOSTANDARD = "LVTTL";
+ NET TLK_TXD<6> LOC = "M25" | IOSTANDARD = "LVTTL";
+ NET TLK_TXD<7> LOC = "M26" | IOSTANDARD = "LVTTL";
+ NET TLK_TXD<8> LOC = "N22" | IOSTANDARD = "LVTTL";
+ NET TLK_TXD<9> LOC = "N23" | IOSTANDARD = "LVTTL";
+ NET TLK_TXD<10> LOC = "H29" | IOSTANDARD = "LVTTL";
+ NET TLK_TXD<11> LOC = "H30" | IOSTANDARD = "LVTTL";
+ NET TLK_TXD<12> LOC = "C33" | IOSTANDARD = "LVTTL";
+ NET TLK_TXD<13> LOC = "C34" | IOSTANDARD = "LVTTL";
+ NET TLK_TXD<14> LOC = "D34" | IOSTANDARD = "LVTTL";
+ NET TLK_TXD<15> LOC = "E34" | IOSTANDARD = "LVTTL";
+ NET TLK_TX_EN LOC = "L29" | IOSTANDARD = "LVTTL";
+ NET TLK_TX_ER LOC = "P24" | IOSTANDARD = "LVTTL";
+# NET TOKEN_IN LOC = "E6";
+# NET TOKEN_OUT LOC = "C13";
+ NET VIRT_CLK LOC = "AF18";
+
+ NET VIRT_CLKB LOC = "AE18";
+# NET "VIRT_CLK" TNM_NET = "VIRT_CLK";
+# TIMESPEC "TS_VIRT_CLK" = PERIOD "VIRT_CLK" 10 ns HIGH 50 %;
+# NET "VIRT_CLKB" TNM_NET = "VIRT_CLKB";
+# TIMESPEC "TS_VIRT_CLKB" = PERIOD "VIRT_CLKB" 10 ns HIGH 50 %;
+ NET VIRT_TCK LOC = K34 | IOSTANDARD = "LVTTL";
+ NET VIRT_TDI LOC = M31 | IOSTANDARD = "LVTTL";
+ NET VIRT_TDO LOC = N30 | IOSTANDARD = "LVTTL";
+ NET VIRT_TMS LOC = J34 | IOSTANDARD = "LVTTL";
+ NET VIRT_TRST LOC = N29 | IOSTANDARD = "LVTTL";
+ NET VIR_TRIG LOC = "E3"| IOSTANDARD = "LVDS_25";
+ NET VIR_TRIGB LOC = "E2"| IOSTANDARD = "LVDS_25";
+ # NET VSD_A<0> LOC = F23;
+ # NET VSD_A<1> LOC = E23;
+ # NET VSD_A<2> LOC = D26;
+ # NET VSD_A<3> LOC = E26;
+ # NET VSD_A<4> LOC = F24;
+ # NET VSD_A<5> LOC = E24;
+ # NET VSD_A<6> LOC = D27;
+ # NET VSD_A<7> LOC = E27;
+ # NET VSD_A<8> LOC = G23;
+ # NET VSD_A<9> LOC = H24;
+ # NET VSD_A<10> LOC = A28;
+ # NET VSD_A<11> LOC = A29;
+ # NET VSD_A<12> LOC = B25;
+ # NET VSD_BA<0> LOC = C25;
+ # NET VSD_BA<1> LOC = J25;
+ # NET VSD_CAS LOC = G28;
+ # NET VSD_CKE LOC = D30;
+ # NET VSD_CLOCK LOC = B28;
+ # NET VSD_CSEH LOC = G27;
+ # NET VSD_CSEL LOC = D31;
+ # NET VSD_D<0> LOC = B23;
+ # NET VSD_D<1> LOC = A23;
+ # NET VSD_D<2> LOC = A26;
+ # NET VSD_D<3> LOC = B26;
+ # NET VSD_D<4> LOC = A24;
+ # NET VSD_D<5> LOC = A25;
+ # NET VSD_D<6> LOC = G25;
+ # NET VSD_D<7> LOC = H25;
+ # NET VSD_D<8> LOC = C23;
+ # NET VSD_D<9> LOC = C24;
+ # NET VSD_D<10> LOC = F25;
+ # NET VSD_D<11> LOC = F26;
+ # NET VSD_D<12> LOC = D24;
+ # NET VSD_D<13> LOC = D25;
+ # NET VSD_D<14> LOC = B27;
+ # NET VSD_D<15> LOC = C27;
+ # NET VSD_D<16> LOC = C22;
+ # NET VSD_D<17> LOC = B22;
+ # NET VSD_D<18> LOC = A30;
+ # NET VSD_D<19> LOC = B30;
+ # NET VSD_D<20> LOC = K24;
+ # NET VSD_D<21> LOC = J24;
+ # NET VSD_D<22> LOC = C29;
+ # NET VSD_D<23> LOC = C30;
+ # NET VSD_D<24> LOC = B21;
+ # NET VSD_D<25> LOC = A21;
+ # NET VSD_D<26> LOC = E28;
+ # NET VSD_D<27> LOC = F28;
+ # NET VSD_D<28> LOC = A31;
+ # NET VSD_D<29> LOC = B31;
+ # NET VSD_D<30> LOC = E31;
+ # NET VSD_D<31> LOC = F31;
+ # NET VSD_DQML<0> LOC = F30;
+ # NET VSD_DQML<1> LOC = D29;
+ # NET VSD_DQML<2> LOC = E29;
+ # NET VSD_DQML<3> LOC = L25;
+ # NET VSD_RAS LOC = F29;
+ # NET VSD_WE LOC = K26;
+
--- /dev/null
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use IEEE.NUMERIC_STD.all;
+
+-- use work.support.all;
+ library UNISIM;
+ use UNISIM.VCOMPONENTS.all;
+
+-- -- Uncomment the following lines to use the declarations that are
+-- -- provided for instantiating Xilinx primitive components.
+-- library UNISIM;
+-- use UNISIM.VComponents.all;
+
+entity rpc_trb_v2_fpga is
+ port (
+ -------------------------------------------------------------------------
+ -- GENERAL
+ -------------------------------------------------------------------------
+ VIRT_CLK : in std_logic;
+ VIRT_CLKB : in std_logic;
+ RESET_VIRT : in std_logic;
+ DBAD : out std_logic; --diode
+ DGOOD : out std_logic; --diode
+ DINT : out std_logic; --diode
+ DWAIT : out std_logic; --diode
+ A_RESERVED : in std_logic; --TDC connector 75,76(line 3 from end)
+ A_TEMP : in std_logic; -- |
+ B_RESERVED : in std_logic; -- |
+ B_TEMP : in std_logic; -- V
+ C_RESERVED : in std_logic;
+ C_TEMP : in std_logic;
+ D_RESERVED : in std_logic;
+ D_TEMP : in std_logic;
+ VIR_TRIG : in std_logic; --fast trigger
+ VIR_TRIGB : in std_logic;
+ -------------------------------------------------------------------------
+ -- TDC connections
+ -------------------------------------------------------------------------
+-- A_TDC_ERROR : in std_logic;
+-- B_TDC_ERROR : in std_logic;
+-- C_TDC_ERROR : in std_logic;
+-- D_TDC_ERROR : in std_logic;
+-- A_TDC_POWERUP : out std_logic; --turn on TDC -should be one ?!
+-- B_TDC_POWERUP : out std_logic;
+-- C_TDC_POWERUP : out std_logic;
+-- D_TDC_POWERUP : out std_logic;
+-- TOKEN_IN : in std_logic;
+-- TOKEN_OUT : out std_logic;
+-- C_TOKEN_OUT_TTL : in std_logic;
+-- GET_DATA : out std_logic;
+-- A_DATA_READY : in std_logic;
+-- B_DATA_READY : in std_logic;
+-- C_DATA_READY : in std_logic;
+-- D_DATA_READY : in std_logic;
+-- REF_TDC_CLK : in std_logic;
+-- REF_TDC_CLKB : in std_logic;
+-- TDC_BU_RESET : out std_logic;
+-- TDC_BU_RESETB : out std_logic;
+-- TDC_EV_RESET : out std_logic;
+-- TDC_EV_RESETB : out std_logic;
+-- TDC_OUT : in std_logic_vector (31 downto 0);
+ TDC_RESET : out std_logic;
+-- A_TRIGGER : out std_logic;
+-- A_TRIGGERB : out std_logic;
+-- B_TRIGGER : out std_logic;
+-- B_TRIGGERB : out std_logic;
+-- C_TRIGGER : out std_logic;
+-- C_TRIGGERB : out std_logic;
+-- D_TRIGGER : out std_logic;
+-- D_TRIGGERB : out std_logic;
+ -------------------------------------------------------------------------
+ -- ETRAX connections
+ -------------------------------------------------------------------------
+ FS_PB : out std_logic_vector (17 downto 0);
+ FS_PC : inout std_logic_vector (17 downto 0);
+ ETRAX_IRQ : out std_logic; --check what is the correct value
+ -------------------------------------------------------------------------
+ -- SPI
+ -------------------------------------------------------------------------
+ -- A_SCK LOC = H3;
+ -- A_SCKB LOC = H2;
+ -- A_SDI LOC = F1;
+ -- A_SDIB LOC = G1;
+ -- A_SDO LOC = J4;
+ -- A_SDOB LOC = K4;
+ -- B_SCK LOC = C4;
+ -- B_SCKB LOC = C3;
+ -- B_SDI LOC = R11;
+ -- B_SDIB LOC = T11;
+ -- B_SDO LOC = J2;
+ -- B_SDOB LOC = J1;
+ -- C_SCK LOC = P7;
+ -- C_SCKB LOC = P6;
+ -- C_SDI LOC = D1;
+ -- C_SDIB LOC = E1;
+ -- C_SDO LOC = F4;
+ -- C_SDOB LOC = F3;
+ -- D_SCK LOC = M6;
+ -- D_SCKB LOC = M5;
+ -- D_SDI LOC = K3;
+ -- D_SDIB LOC = L3;
+ -- D_SDO LOC = K2;
+ -- D_SDOB LOC = K1;
+ -- A_CS1B : std_logic;
+ -- A_CS<1> LOC = P10;
+ -- B_CS1B LOC = G5;
+ -- B_CS<1> LOC = F5;
+ -- C_CS1B LOC = R9;
+ -- C_CS<1> LOC = T10;
+ -- D_CS1B LOC = M2;
+ -- D_CS<1> LOC = M3;
+ -------------------------------------------------------------------------
+ -- TEST SIGNALS - for RPC
+ -------------------------------------------------------------------------
+ -- A_TEST1B LOC = N7;
+ -- A_TEST2B LOC = L4;
+ -- A_TEST1 LOC = M7;
+ -- A_TEST2 LOC = L5;
+ -- B_TEST2B LOC = L9;
+ -- B_TEST1B LOC = E4;
+ -- B_TEST1 LOC = D4;
+ -- B_TEST2 LOC = M10;
+ -- C_TEST2B LOC = N12;
+ -- C_TEST1B LOC = D2;
+ -- C_TEST<1> LOC = C2;
+ -- C_TEST<2> LOC = N13;
+ -- D_TEST1B LOC = M1;
+ -- D_TEST2B LOC = P5;
+ -- D_TEST<1> LOC = L1;
+ -- D_TEST<2> LOC = N5;
+ -------------------------------------------------------------------------
+ -- SHARC
+ -------------------------------------------------------------------------
+ DSPADDR : out std_logic_vector (31 downto 0);
+ DSPDAT : inout std_logic_vector (31 downto 0);
+ DSP_ACK : in std_logic;
+ DSP_BM : in std_logic;
+ -- DSP_BMS LOC = AF15;
+ -- DSP_BOFF LOC = AK14;
+ DSP_BRST : inout std_logic;
+ -- DSP_BUSLOCK LOC = AC19;
+ -- DSP_DMAR : std_logic_vector (3 downto 0);
+ -- DSP_FLAG : std_logic_vector (3 downto 0);
+ DSP_HBG : in std_logic;
+ DSP_HBR : out std_logic;
+ -- DSP_IOEN LOC = AL18;
+ -- DSP_IORD LOC = AB16;
+ -- DSP_IOWR LOC = AB17;
+ -- DSP_IRQ : std_logic_vector (3 downto 0);
+ -- DSP_L1DATIP : std_logic_vector (3 downto 0);
+ -- DSP_L0ACKI LOC = AM18;
+ -- DSP_L1ACKO LOC = AM15;
+ -- DSP_L0BCMPI LOC = AM16;
+ -- DSP_L0BCMPO LOC = AD21;
+ -- DSP_L1DATIN : std_logic_vector (3 downto 0);
+ -- DSP_L1BCMPO LOC = AJ20;
+ -- DSP_L1DATOP : std_logic_vector (3 downto 0);
+ -- DSP_L0DATON : std_logic_vector (3 downto 0);
+ -- DSP_L0ACKO LOC = AM17;
+ -- DSP_L1CLKINN LOC = AL30;
+ -- DSP_L1CLKOUTP LOC = AM21;
+ -- DSP_L0DATIN : std_logic_vector (3 downto 0);
+ -- DSP_L0CLKINP LOC = AP29;
+ -- DSP_L1CLKOUTN LOC = AM22;
+ -- DSP_L1BCMPI LOC = AL15;
+ -- DSP_L0CLKOUTN LOC = AL25;
+ -- DSP_L1CLKINP LOC = AM30;
+ -- DSP_L0DATOP : std_logic_vector (3 downto 0);
+ -- DSP_L1ACKI LOC = AD20;
+ -- DSP_L0CLKINN LOC = AN29;
+ -- DSP_L0DATIP : std_logic_vector (3 downto 0);
+ -- DSP_L1DATON : std_logic_vector (3 downto 0);
+ -- DSP_L0CLKOUTP LOC = AL24;
+ -- DSP_MSH LOC = AL14;
+ DSP_RD : inout std_logic;
+ DSP_RESET : out std_logic;
+ -- DSP_RESET_OUT LOC = AH22;
+ -- DSP_TMROE LOC = AP20;
+ DSP_WRH :inout std_logic;
+ DSP_WRL :inout std_logic;
+ -------------------------------------------------------------------------
+ -- SDRAM
+ -------------------------------------------------------------------------
+ -- VSD_A std_logic_vector (12 downto 0);
+ -- VSD_BA std_logic_vector (1 downto 0);
+ -- VSD_CAS LOC = G28;
+ -- VSD_CKE LOC = D30;
+ -- VSD_CLOCK LOC = B28;
+ -- VSD_CSEH LOC = G27;
+ -- VSD_CSEL LOC = D31;
+ -- VSD_D std_logic_vector (31 downto 0);
+ -- VSD_DQML<0> std_logic_vector (3 downto 0);
+ -- VSD_RAS LOC = F29;
+ -- VSD_WE LOC = K26;
+ -------------------------------------------------------------------------
+ -- TLK
+ -------------------------------------------------------------------------
+ TLK_CLK : in std_logic;
+ TLK_ENABLE : out std_logic;
+ TLK_LCKREFN : out std_logic;
+ TLK_LOOPEN : out std_logic;
+ TLK_PRBSEN : out std_logic;
+ TLK_RXD : in std_logic_vector (15 downto 0);
+ TLK_RX_CLK : in std_logic;
+ TLK_RX_DV : in std_logic;
+ TLK_RX_ER : in std_logic;
+ TLK_TXD : out std_logic_vector (15 downto 0);
+ TLK_TX_EN : out std_logic;
+ TLK_TX_ER : out std_logic;
+ -------------------------------------------------------------------------
+ -- SFP
+ -------------------------------------------------------------------------
+ -- SFP_LOS LOC = M27;
+ -- SFP_MOD<0> LOC = R23;
+ -- SFP_MOD<1> LOC = K32;
+ -- SFP_MOD<2> LOC = K33;
+ -- SFP_RATE_SEL : out std_logic;
+ SFP_TX_DIS : out std_logic;
+ -- SFP_TX_FAULT LOC = J32;
+ -------------------------------------------------------------------------
+ -- ADDON board
+ -------------------------------------------------------------------------
+ -- ADDON_TO_TRB_CLKINN : std_logic;
+ -- ADDON_TO_TRB_CLKINP : std_logic;
+ -- ADO_LV : std_logic_vector(61 downto 0);lvds signal
+ ADO_TTL : out std_logic_vector(46 downto 0);
+ -------------------------------------------------------------------------------
+ --JTAG
+ -------------------------------------------------------------------------------
+ VIRT_TCK : out std_logic;
+ VIRT_TDI : out std_logic;
+ VIRT_TDO : in std_logic;
+ VIRT_TMS : out std_logic;
+ VIRT_TRST : out std_logic
+ );
+ end rpc_trb_v2_fpga;
+architecture rpc_trb_v2_fpga of rpc_trb_v2_fpga is
+ component tdc_interface
+ port (
+ CLK : in std_logic;
+ TDC_CLK : in std_logic;
+ RESET : in std_logic;
+ TDC_DATA_IN : in std_logic_vector (31 downto 0);
+ START_TDC_READOUT : in std_logic;
+ A_TDC_READY : in std_logic;
+ B_TDC_READY : in std_logic;
+ C_TDC_READY : in std_logic;
+ D_TDC_READY : in std_logic;
+ SEND_TDC_TOKEN : out std_logic;
+ RECEIVED_TDC_TOKEN : in std_logic;
+ GET_TDC_DATA : out std_logic;
+ TO_MANY_TDC_DATA : in std_logic;
+ TDC_READOUT_COMPLETED : out std_logic;
+ LVL1_TAG : in std_logic_vector(7 downto 0);
+ LVL1_CODE : in std_logic_vector(3 downto 0);
+ HOW_MANY_ADD_DATA : in std_logic_vector(7 downto 0);
+ COUNTER_a : in std_logic_vector(31 downto 0);
+ COUNTER_b : in std_logic_vector(31 downto 0);
+ COUNTER_c : in std_logic_vector(31 downto 0);
+ COUNTER_d : in std_logic_vector(31 downto 0);
+ COUNTER_e : in std_logic_vector(31 downto 0);
+ COUNTER_f : in std_logic_vector(31 downto 0);
+ COUNTER_g : in std_logic_vector(31 downto 0);
+ COUNTER_h : in std_logic_vector(31 downto 0);
+ COUNTER_i : in std_logic_vector(31 downto 0);
+ COUNTER_j : in std_logic_vector(31 downto 0);
+ COUNTER_k : in std_logic_vector(31 downto 0);
+ COUNTER_l : in std_logic_vector(31 downto 0);
+ COUNTER_m : in std_logic_vector(31 downto 0);
+ LVL2_TRIGGER : in std_logic_vector(1 downto 0);
+ TDC_DATA_OUT : out std_logic_vector(31 downto 0);
+ TDC_DATA_VALID : out std_logic;
+ ETRAX_READ_ONE_kW : in std_logic;
+ ETRAX_HAS_TO_READ_EVENT : out std_logic;
+ ETRAX_IS_READY_TO_READ : in std_logic;
+ TDC_LVL1_BUSY : out std_logic;
+ TDC_LVL2_BUSY : out std_logic);
+ end component;
+ component lvl1_and_lvl2_busy
+ port (
+ CLK : in std_logic;
+ RESET : in std_logic;
+ LVL1_BUSY : out std_logic;
+ LVL2_BUSY : out std_logic;
+ TDC_LVL1_BUSY : in std_logic;
+ TDC_LVL2_BUSY : in std_logic;
+ LVL1_TRIGG : in std_logic;
+ LVL2_TRIGG : in std_logic;
+ TRIGGER_CODE : in std_logic_vector(3 downto 0);
+ TDC_READOUT_COMPLETED : in std_logic
+ );
+ end component;
+ component trigger_logic
+ port (
+ CLK : in std_logic;
+ RESET : in std_logic;
+ LVL1_TRIGGER_CODE : in std_logic_vector(3 downto 0);
+ LVL1_TRIGGER_TAG : in std_logic_vector(7 downto 0);
+ TDC_CODE : out std_logic_vector(3 downto 0);
+ TDC_TAG : out std_logic_vector(7 downto 0);
+ LVL2_TRIGGER : in std_logic_vector(1 downto 0);
+ LVL1_TRIGGER : in std_logic;
+ LVL1_TDC_TRIGG : out std_logic;
+ LVL2_TDC_TRIGG : out std_logic_vector(1 downto 0);
+ TRIGG_WITHOUT_HADES : in std_logic;
+ TDC_CONTROL_REGISTER : in std_logic_vector(7 downto 0);
+ DELAY_TRIGGER : in std_logic_vector(7 downto 0);
+ LVL1_BUSY : in std_logic;
+ LVL2_BUSY : in std_logic;
+ TRB_ACK_LVL1 : out std_logic;
+ TRB_ACK_LVL2 : out std_logic);
+ end component;
+ component etrax_interface
+ port (
+ CLK : in std_logic;
+ RESET : in std_logic;
+ DATA_BUS : in std_logic_vector(31 downto 0);
+ ETRAX_DATA_BUS_B : out std_logic_vector(17 downto 0);
+ ETRAX_DATA_BUS_C : inout std_logic_vector(17 downto 0);
+ DATA_VALID : in std_logic;
+ ETRAX_BUS_BUSY : out std_logic;
+ ETRAX_READ_ONE_kW : in std_logic;
+ ETRAX_HAS_TO_READ_EVENT : in std_logic;
+ ETRAX_IS_READY_TO_READ : in std_logic;
+ TDC_TCK : out std_logic;
+ TDC_TDI : out std_logic;
+ TDC_TMS : out std_logic;
+ TDC_TRST : out std_logic;
+ TDC_TDO : in std_logic;
+ TDC_RESET : out std_logic;
+ EXTERNAL_ADDRESS : out std_logic_vector(31 downto 0);
+ EXTERNAL_DATA : inout std_logic_vector(31 downto 0);
+ EXTERNAL_ACK : out std_logic;
+ EXTERNAL_VALID : in std_logic;
+ EXTERNAL_MODE : out std_logic_vector(15 downto 0);
+ FPGA_REGISTER_00 : in std_logic_vector(31 downto 0);
+ FPGA_REGISTER_01 : in std_logic_vector(31 downto 0);
+ FPGA_REGISTER_02 : in std_logic_vector(31 downto 0);
+ FPGA_REGISTER_03 : in std_logic_vector(31 downto 0);
+ FPGA_REGISTER_04 : in std_logic_vector(31 downto 0);
+ FPGA_REGISTER_05 : in std_logic_vector(31 downto 0);
+ FPGA_REGISTER_06 : in std_logic_vector(31 downto 0);
+ FPGA_REGISTER_07 : in std_logic_vector(31 downto 0);
+ FPGA_REGISTER_08 : in std_logic_vector(31 downto 0);
+ FPGA_REGISTER_09 : in std_logic_vector(31 downto 0);
+ FPGA_REGISTER_10 : in std_logic_vector(31 downto 0);
+ FPGA_REGISTER_11 : in std_logic_vector(31 downto 0);
+ FPGA_REGISTER_12 : in std_logic_vector(31 downto 0);
+ FPGA_REGISTER_13 : in std_logic_vector(31 downto 0);
+ FPGA_REGISTER_14 : in std_logic_vector(31 downto 0);
+ FPGA_REGISTER_15 : in std_logic_vector(31 downto 0);
+ FPGA_REGISTER_16 : out std_logic_vector(31 downto 0);
+ FPGA_REGISTER_17 : out std_logic_vector(31 downto 0);
+ FPGA_REGISTER_18 : out std_logic_vector(31 downto 0);
+ FPGA_REGISTER_19 : out std_logic_vector(31 downto 0);
+ FPGA_REGISTER_20 : out std_logic_vector(31 downto 0);
+ FPGA_REGISTER_21 : out std_logic_vector(31 downto 0);
+ FPGA_REGISTER_22 : out std_logic_vector(31 downto 0);
+ FPGA_REGISTER_23 : out std_logic_vector(31 downto 0);
+ FPGA_REGISTER_24 : out std_logic_vector(31 downto 0);
+ FPGA_REGISTER_25 : out std_logic_vector(31 downto 0);
+ FPGA_REGISTER_26 : out std_logic_vector(31 downto 0);
+ FPGA_REGISTER_27 : out std_logic_vector(31 downto 0);
+ FPGA_REGISTER_28 : out std_logic_vector(31 downto 0);
+ FPGA_REGISTER_29 : out std_logic_vector(31 downto 0);
+ FPGA_REGISTER_30 : out std_logic_vector(31 downto 0);
+ FPGA_REGISTER_31 : out std_logic_vector(31 downto 0);
+ EXTERNAL_RESET : out std_logic);
+
+ end component;
+ component tlk_interface
+ port (
+ VIRT_CLK : in std_logic;
+ ENABLE : out std_logic;
+ LCKREFN : out std_logic;
+ LOOPEN : out std_logic;
+ PRBSEN : out std_logic;
+ RX_CLK : in std_logic;
+ RX_DV : in std_logic;
+ RX_ER : in std_logic;
+ TLK_CLK : in std_logic;
+ TLK_RXD : in std_logic_vector (15 downto 0);
+ TLK_TXD : out std_logic_vector (15 downto 0);
+ TX_EN : out std_logic;
+ TX_ER : out std_logic;
+ RESET_VIRT : in std_logic;
+ TLK_REGISTER_00 : out std_logic_vector(31 downto 0);
+ TLK_REGISTER_01 : out std_logic_vector(31 downto 0));
+ end component;
+ component dsp_interface
+ port (
+-- signal to/from dsp
+ HBR_OUT : out std_logic; -- Host Bus Request to DSP
+ HBG_IN : in std_logic; -- Host Bus Grant from DSP
+ RD_OUT : out std_logic; -- read/write enable of DSP
+ DSP_DATA : inout std_logic_vector(31 downto 0);
+ ADDRESS_DSP : out std_logic_vector(31 downto 0);
+ WRL : inout std_logic; --when dsp slave is output
+ WRH : inout std_logic; --when dsp slave is output
+ BM_IN : in std_logic; --Bus Master. For debug
+ DSP_RESET : out std_logic;
+ BRST : inout std_logic;
+ ACK : in std_logic;
+--internal data and address bus
+ CLK : in std_logic;
+ RESET : in std_logic;
+ R_W_ENABLE : in std_logic;
+ TRIGGER : in std_logic;
+ INTERNAL_DATA : inout std_logic_vector(31 downto 0); --63 downto 0
+ INTERNAL_ADDRESS : in std_logic_vector(31 downto 0);
+ VALID_DATA_SENT : out std_logic;
+ ACKNOWLEDGE : in std_logic;
+ DEBUGSTATE_MACHINE : out std_logic_vector(31 downto 0)
+ );
+ end component;
+ -----------------------------------------------------------------------------
+ -- SPI --component !!!
+ -----------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+-- SIGNALS
+-------------------------------------------------------------------------------
+ signal CLK : std_logic;
+ signal a_trigg : std_logic;
+ signal b_trigg : std_logic;
+ signal c_trigg : std_logic;
+ signal d_trigg : std_logic;
+ signal reference_signal : std_logic;
+ signal tdc_clk : std_logic;
+ signal to_many_tdc_data_i : std_logic;
+ signal tdc_readout_completed_i : std_logic;
+ signal how_many_add_data_i : std_logic_vector(7 downto 0);
+ signal tdc_data_out_i : std_logic_vector(31 downto 0);
+ signal tdc_data_valid_i : std_logic;
+ signal lvl1_busy_i : std_logic;
+ signal lvl2_busy_i : std_logic;
+ signal lvl1_tdc_trigg_i : std_logic;
+ signal lvl2_tdc_trigg_i : std_logic_vector(1 downto 0);
+ signal lvl1_trigger_code_i : std_logic_vector(3 downto 0);
+ signal lvl1_trigger_tag_i : std_logic_vector(7 downto 0);
+ signal tdc_code_i : std_logic_vector(3 downto 0);
+ signal tdc_tag_i : std_logic_vector(7 downto 0);
+ signal lvl2_trigger_i : std_logic_vector(1 downto 0);
+ signal lvl1_trigger_i : std_logic;
+ signal trigg_without_hades_i : std_logic;
+ signal tdc_control_register_i : std_logic_vector(7 downto 0);
+ signal delay_trigger_i : std_logic_vector(7 downto 0);
+ signal trb_ack_lvl1_i : std_logic;
+ signal trb_ack_lvl2_i : std_logic;
+ signal etrax_data_bus_i : std_logic_vector(35 downto 0);
+ signal etrax_bus_busy_i : std_logic; --should go to busy logic !?
+ signal tdc_lvl1_busy_i : std_logic;
+ signal tdc_lvl2_busy_i : std_logic;
+ signal etrax_read_one_kw_i : std_logic;
+ signal etrax_has_to_read_event_i : std_logic;
+ signal etrax_is_ready_to_read_i : std_logic;
+ signal tlk_rx_clk_io : std_logic;
+ signal tlk_clk_io : std_logic;
+ signal tlk_rx_clk_r : std_logic;
+ signal tlk_clk_r : std_logic;
+ signal tlk_register_00_i : std_logic_vector(31 downto 0);
+ signal tlk_register_01_i : std_logic_vector(31 downto 0);
+ signal fpga_register_18_i : std_logic_vector(31 downto 0);
+ signal dsp_register_00_i : std_logic_vector(31 downto 0);
+ signal external_address_i : std_logic_vector(31 downto 0);
+ signal external_data_i : std_logic_vector(31 downto 0);
+ signal external_ack_i : std_logic;
+ signal external_valid_i : std_logic;
+ signal external_mode_i : std_logic_vector(15 downto 0);
+ signal dsp_strobe_i : std_logic;
+ signal dsp_external_valid_i : std_logic;
+ signal reset_i : std_logic;
+ signal fpga_register_19_i : std_logic_vector(31 downto 0);
+ signal fpga_register_20_i : std_logic_vector(31 downto 0);
+ signal fpga_register_07_i : std_logic_vector(31 downto 0);
+
+ signal dsp_hbr_i : std_logic;
+ signal external_reset_i : std_logic;
+ signal dspdat_i : std_logic_vector(31 downto 0);
+ signal dspaddr_i : std_logic_vector(31 downto 0);
+ signal internal_clock : std_logic;
+ signal internal_clock_not : std_logic;
+ signal external_debug_i : std_logic;
+begin
+ -----------------------------------------------------------------------------
+ -- LVDS signals
+ -----------------------------------------------------------------------------
+ IBUFGDS_CLK : IBUFGDS
+ generic map (
+ IOSTANDARD => "LVDS_25_DCI")
+ port map (
+ O => internal_clock,--CLK,
+ I => VIRT_CLK,
+ IB => VIRT_CLKB -- Diff_n clock buffer input (connect to top-level port)
+ );
+ BUFG_CLK : BUFG
+ port map(
+ I => internal_clock,
+ O => CLK
+ );
+
+
+-- CLK <= tlk_clk_r;
+-- IBUFGDS_TDC_CLK : IBUFGDS
+-- generic map (
+-- IOSTANDARD => "LVDS_25")
+-- port map (
+-- O => tdc_clk,
+-- I => REF_TDC_CLK,
+-- IB => REF_TDC_CLKB-- Diff_n clock buffer input (connect to top-level port)
+-- );
+-- OBUFDS_TRIGG_A : OBUFDS
+-- generic map (
+-- -- DRIVE => 12,
+-- IOSTANDARD => "LVDS_25"
+-- -- SLEW => "SLOW"
+-- )
+-- port map (
+-- O => A_TRIGGER,
+-- OB => A_TRIGGERB,
+-- I => a_trigg
+-- );
+-- OBUFDS_TRIGG_B : OBUFDS
+-- generic map (
+-- IOSTANDARD => "LVDS_25"
+-- )
+-- port map (
+-- O => B_TRIGGER,
+-- OB => B_TRIGGERB,
+-- I => b_trigg
+-- );
+-- OBUFDS_TRIGG_C : OBUFDS
+-- generic map (
+-- IOSTANDARD => "LVDS_25"
+-- )
+-- port map (
+-- O => C_TRIGGER,
+-- OB => C_TRIGGERB,
+-- I => c_trigg
+-- );
+-- OBUFDS_TRIGG_D : OBUFDS
+-- generic map (
+-- IOSTANDARD => "LVDS_25"
+-- )
+-- port map (
+-- O => D_TRIGGER,
+-- OB => D_TRIGGERB,
+-- I => d_trigg
+-- );
+ IBUFDS_REFERENCE : IBUFGDS
+ generic map (
+ IOSTANDARD => "LVDS_25_DCI")
+ port map (
+ O => reference_signal,
+ I => VIR_TRIG,
+ IB => VIR_TRIGB
+ );
+ -----------------------------------------------------------------------------
+ -- Component Instance
+ -----------------------------------------------------------------------------
+ reset_i <= not RESET_VIRT;
+
+
+-- TDC_INT: tdc_interface
+-- port map (
+-- CLK => CLK,
+-- TDC_CLK => tdc_clk,
+-- RESET => not RESET_VIRT,
+-- TDC_RESET => TDC_RESET
+-- TDC_DATA_IN => TDC_OUT,
+-- START_TDC_READOUT => lvl1_tdc_trigg_i,
+-- A_TDC_READY => A_DATA_READY,
+-- B_TDC_READY => B_DATA_READY,
+-- C_TDC_READY => C_DATA_READY,
+-- D_TDC_READY => D_DATA_READY,
+-- SEND_TDC_TOKEN => TOKEN_OUT,
+-- RECEIVED_TDC_TOKEN => TOKEN_IN,
+-- GET_TDC_DATA => GET_DATA,
+-- TO_MANY_TDC_DATA => to_many_tdc_data_i,
+-- TDC_READOUT_COMPLETED => tdc_readout_completed_i,
+-- LVL1_TAG => tdc_tag_i,
+-- LVL1_CODE => tdc_code_i,
+-- HOW_MANY_ADD_DATA => how_many_add_data_i,
+-- COUNTER_a => x"12341234",
+-- COUNTER_b => x"12341234",
+-- COUNTER_c => x"12341234",
+-- COUNTER_d => x"12341234",
+-- COUNTER_e => x"12341234",
+-- COUNTER_f => x"12341234",
+-- COUNTER_g => x"12341234",
+-- COUNTER_h => x"12341234",
+-- COUNTER_i => x"12341234",
+-- COUNTER_j => x"12341234",
+-- COUNTER_k => x"12341234",
+-- COUNTER_l => x"12341234",
+-- COUNTER_m => x"12341234",
+-- LVL2_TRIGGER => lvl2_tdc_trigg_i,
+-- TDC_DATA_OUT => tdc_data_out_i,
+-- TDC_DATA_VALID => tdc_data_valid_i,
+-- ETRAX_READ_ONE_kW => etrax_read_one_kw_i,
+-- ETRAX_HAS_TO_READ_EVENT => etrax_has_to_read_event_i,
+-- ETRAX_IS_READY_TO_READ => etrax_is_ready_to_read_i,
+-- TDC_LVL1_BUSY => tdc_lvl1_busy_i,
+-- TDC_LVL2_BUSY => tdc_lvl2_busy_i);
+-- BUSY_LOGIC: lvl1_and_lvl2_busy
+-- port map (
+-- CLK => CLK,
+-- RESET => reset_i,
+-- LVL1_BUSY => lvl1_busy_i,
+-- LVL2_BUSY => lvl2_busy_i,
+-- TDC_LVL1_BUSY => tdc_lvl1_busy_i,
+-- TDC_LVL2_BUSY => tdc_lvl2_busy_i,
+-- LVL1_TRIGG => lvl1_trigger_i,
+-- LVL2_TRIGG => lvl2_trigger_i(0),
+-- TRIGGER_CODE => lvl1_trigger_code_i,
+-- TDC_READOUT_COMPLETED => tdc_readout_completed_i);
+-- TRIGG_LOGIC: trigger_logic
+-- port map (
+-- CLK => CLK,
+-- RESET => reset_i,
+-- LVL1_TRIGGER_CODE => lvl1_trigger_code_i,
+-- LVL1_TRIGGER_TAG => lvl1_trigger_tag_i,
+-- TDC_CODE => tdc_code_i,
+-- TDC_TAG => tdc_tag_i,
+-- LVL2_TRIGGER => lvl2_trigger_i,
+-- LVL1_TRIGGER => lvl1_trigger_i,
+-- LVL1_TDC_TRIGG => lvl1_tdc_trigg_i,
+-- LVL2_TDC_TRIGG => lvl2_tdc_trigg_i,
+-- TRIGG_WITHOUT_HADES => trigg_without_hades_i,
+-- TDC_CONTROL_REGISTER => tdc_control_register_i,
+-- DELAY_TRIGGER => x"00",--delay_trigger_i,
+-- LVL1_BUSY => lvl1_busy_i,
+-- LVL2_BUSY => lvl2_busy_i,
+-- TRB_ACK_LVL1 => trb_ack_lvl1_i,
+-- TRB_ACK_LVL2 => trb_ack_lvl2_i);
+ external_valid_i <= dsp_external_valid_i;
+ ETRAX_INTERFACE_LOGIC : etrax_interface
+ port map (
+ CLK => CLK,
+ RESET => reset_i,
+ DATA_BUS => tdc_data_out_i,
+ ETRAX_DATA_BUS_B => FS_PB,
+ ETRAX_DATA_BUS_C => FS_PC,
+ DATA_VALID => '0',--tdc_data_valid_i,
+ ETRAX_BUS_BUSY => etrax_bus_busy_i,
+ ETRAX_READ_ONE_kW => etrax_read_one_kw_i,
+ ETRAX_HAS_TO_READ_EVENT => etrax_has_to_read_event_i,
+ ETRAX_IS_READY_TO_READ => etrax_is_ready_to_read_i,
+ TDC_TCK => VIRT_TCK,
+ TDC_TDI => VIRT_TDI,
+ TDC_TMS => VIRT_TMS,
+ TDC_TRST => VIRT_TRST,
+ TDC_TDO => VIRT_TDO,
+ TDC_RESET => TDC_RESET,
+ EXTERNAL_ADDRESS => external_address_i,
+ EXTERNAL_DATA => external_data_i,
+ EXTERNAL_ACK => external_ack_i,
+ EXTERNAL_VALID => external_valid_i,
+ EXTERNAL_MODE => external_mode_i,
+ FPGA_REGISTER_00 => x"00000000",
+ FPGA_REGISTER_01 => tlk_register_00_i,
+ FPGA_REGISTER_02 => tlk_register_01_i,
+ FPGA_REGISTER_03 => x"abbaab02",
+ FPGA_REGISTER_04 => x"abbaab03",
+ FPGA_REGISTER_05 => x"abbaab04",
+ FPGA_REGISTER_06 => x"abbaab05",
+ FPGA_REGISTER_07 => fpga_register_07_i,
+ FPGA_REGISTER_08 => x"abbaab07",
+ FPGA_REGISTER_09 => x"abbaab08",
+ FPGA_REGISTER_10 => x"abbaab09",
+ FPGA_REGISTER_11 => x"abbaab10",
+ FPGA_REGISTER_12 => x"abbaab11",
+ FPGA_REGISTER_13 => x"abbaab12",
+ FPGA_REGISTER_14 => x"abbaab13",
+ FPGA_REGISTER_15 => dsp_register_00_i,
+ FPGA_REGISTER_16 => open,
+ FPGA_REGISTER_17 => open,
+ FPGA_REGISTER_18 => fpga_register_18_i,
+ FPGA_REGISTER_19 => fpga_register_19_i,
+ FPGA_REGISTER_20 => fpga_register_20_i,
+ FPGA_REGISTER_21 => open,
+ FPGA_REGISTER_22 => open,
+ FPGA_REGISTER_23 => open,
+ FPGA_REGISTER_24 => open,
+ FPGA_REGISTER_25 => open,
+ FPGA_REGISTER_26 => open,
+ FPGA_REGISTER_27 => open,
+ FPGA_REGISTER_28 => open,
+ FPGA_REGISTER_29 => open,
+ FPGA_REGISTER_30 => open,
+ FPGA_REGISTER_31 => open,
+ EXTERNAL_RESET => external_reset_i);
+ TLK_RX_CLK_BUFR: BUFR
+ port map(
+ CE => '1',
+ CLR => '0',
+ I => TLK_RX_CLK,
+ O => tlk_rx_clk_r
+ );
+
+
+
+ TLK_CLK_BUFR: BUFR
+ port map(
+ CE => '1',
+ CLR => '0',
+ I => TLK_CLK,
+ O => tlk_clk_r
+ );
+ tlk_interface_logic: tlk_interface
+ port map (
+ VIRT_CLK => CLK,
+ ENABLE => TLK_ENABLE,
+ LCKREFN => TLK_LCKREFN,
+ LOOPEN => TLK_LOOPEN,
+ PRBSEN => TLK_PRBSEN,
+ RX_CLK => tlk_rx_clk_r,
+ RX_DV => TLK_RX_DV,
+ RX_ER => TLK_RX_ER,
+ TLK_CLK => tlk_clk_r,
+ TLK_RXD => TLK_RXD,
+ TLK_TXD => TLK_TXD,
+ TX_EN => TLK_TX_EN,
+ TX_ER => TLK_TX_ER,
+ RESET_VIRT => reset_i,
+ TLK_REGISTER_00 => tlk_register_00_i,
+ TLK_REGISTER_01 => tlk_register_01_i
+ );
+ dsp_strobe_i <= '1' when external_mode_i(7 downto 0) = x"01" and external_ack_i = '1' else '0';
+
+
+ DSP_INTERFACE_LOGIC: dsp_interface
+ port map (
+ HBR_OUT => dsp_hbr_i,
+ HBG_IN => DSP_HBG,
+ RD_OUT => DSP_RD,
+ DSP_DATA => dspdat_i,--DSPDAT,
+ ADDRESS_DSP => dspaddr_i,--DSPADDR,
+ WRL => DSP_WRL,
+ WRH => DSP_WRH,
+ BM_IN => DSP_BM,
+ DSP_RESET => open,
+ BRST => DSP_BRST,
+ ACK => DSP_ACK,
+ CLK => CLK,
+ RESET => external_reset_i,
+ R_W_ENABLE => external_mode_i(15),
+ TRIGGER => dsp_strobe_i,
+ INTERNAL_DATA => external_data_i,
+ INTERNAL_ADDRESS => external_address_i,
+ VALID_DATA_SENT => dsp_external_valid_i,
+ ACKNOWLEDGE => dsp_strobe_i,
+ DEBUGSTATE_MACHINE => dsp_register_00_i);
+
+ SFP_TX_DIS <= '0';
+ ETRAX_IRQ <= '1';
+ DBAD <= '0';
+ DGOOD <= '1';
+ DINT <= '1';
+ DWAIT <= fpga_register_20_i(0); --'0'enable clock for TDC
+
+ DSP_RESET <= fpga_register_19_i(1);
+ DSP_HBR <= dsp_hbr_i;
+ DSPDAT <= dspdat_i;
+-- DSP_HBR <= '1';
+ fpga_register_07_i <= x"000000" &"0"& DSP_ACK & dsp_register_00_i(2 downto 0)& DSP_HBG & dsp_hbr_i&dsp_strobe_i;
+
+ --ADO_TTL <= dspdat_i(15 downto 0) & DSPADDR(15 downto 0) &
+ --CLK & fpga_register_07_i(6 downto 0);
+ DSPADDR <= dspaddr_i;
+ ADO_TTL <= "000" & x"0000000" & external_debug_i& dspdat_i(2 downto 0) & dspaddr_i(3 downto 0)
+ & CLK & fpga_register_07_i(6 downto 0);
+end rpc_trb_v2_fpga;
--- /dev/null
+#-- Synplicity, Inc.
+#-- Version Synplify Pro 8.2.1
+
+
+#add_file options
+add_file -vhdl -lib work "etrax_interface.vhd"
+add_file -vhdl -lib work "lvl1_fifo.vhd"
+add_file -vhdl -lib work "trigger_logic.vhd"
+add_file -vhdl -lib work "up_down_counter.vhd"
+add_file -vhdl -lib work "f_divider.vhd"
+add_file -vhdl -lib work "up_counter_17bit.vhd"
+add_file -vhdl -lib work "lvl1_and_lvl2_busy.vhd"
+add_file -vhdl -lib work "tdc_interface.vhd"
+#add_file -vhdl -lib work "up_down_counter_16_bit.vhd"
+add_file -vhdl -lib work "rpc_trb_v2_fpga.vhd"
+add_file -vhdl -lib work "tlk_interface.vhd"
+add_file -vhdl -lib work "link_converter.vhd"
+add_file -vhdl -lib work "optical_link_test.vhd"
+add_file -vhdl -lib work "from_64_bit_to_optical_link.vhd"
+add_file -vhdl -lib work "optical_link_to_64_bit.vhd"
+add_file -vhdl -lib work "up_down_counter_10bit.vhd"
+add_file -vhdl -lib work "simpleupcounter_10bit.vhd"
+add_file -vhdl -lib work "simpleupcounter_16bit.vhd"
+add_file -vhdl -lib work "dsp_interface.vhd"
+#add_file -vhdl -lib work ""
+#add_file -vhdl -lib work ""
+#add_file -vhdl -lib work ""
+#add_file -vhdl -lib work ""
+#add_file -vhdl -lib work ""
+#add_file -vhdl -lib work ""
+#add_file -vhdl -lib work ""
+#add_file -vhdl -lib work ""
+add_file -constraint "rpc_trb_v2_fpga_syn.sdc"
+
+
+#implementation: "workdir"
+impl -add workdir
+
+#device options
+set_option -technology VIRTEX4
+set_option -part xc4vlx40
+set_option -package ff1148
+set_option -speed_grade -10
+
+#compilation/mapping options
+set_option -default_enum_encoding default
+set_option -symbolic_fsm_compiler 0
+set_option -resource_sharing 1
+set_option -use_fsm_explorer 0
+set_option -top_module "rpc_trb_v2_fpga"
+
+#map options
+set_option -frequency 100.000
+set_option -run_prop_extract 0
+set_option -fanout_limit 100
+set_option -disable_io_insertion 0
+set_option -pipe 1
+set_option -update_models_cp 0
+set_option -verification_mode 0
+set_option -fixgatedclocks 0
+set_option -modular 0
+set_option -no_sequential_opt 0
+set_option -retiming 0
+
+#simulation options
+set_option -write_verilog 0
+set_option -write_vhdl 0
+
+#VIF options
+set_option -write_vif 1
+
+#automatic place and route (vendor) options
+set_option -write_apr_constraint 1
+
+#set result format/file last
+project -result_file "workdir/rpc_trb_v2_fpga.edf"
+
+#
+#implementation attributes
+
+set_option -synthesis_onoff_pragma 0
+impl -active "workdir"
--- /dev/null
+# Synplicity, Inc. constraint file
+# /home/tiago/RPC/rpctrbfpga/RPCBoardController_syn.sdc
+# Written on Thu Nov 17 14:24:22 2005
+# by Synplify Pro, Synplify Pro 8.2.1 Scope Editor
+
+#
+# Collections
+#
+
+#
+# Clocks
+#
+define_clock -name {CLK} -freq 100.000 -clockgroup default_clkgroup_0
+define_clock -name {tlk_rx_clk_r} -freq 100.000 -clockgroup default_clkgroup_2
+define_clock -name {tlk_clk_r} -freq 100.000 -clockgroup default_clkgroup_3
+
+
+#
+# Clock to Clock
+#
+
+#
+# Inputs/Outputs
+#
+#define_input_delay -disable -default
+#define_output_delay -disable -default
+#define_input_delay -disable {A_DATA_READY}
+#define_input_delay -disable {A_LVDS_IN}
+#define_input_delay -disable {A_TDC_SERIAL_BP_IN}
+#define_input_delay -disable {A_TDC_SERIAL_IN}
+#define_input_delay -disable {A_TDC_SERIAL_OUT}
+#define_input_delay -disable {A_TDC_TOKEN_BP}
+#define_input_delay -disable {ADDR[22:1]}
+#define_output_delay -disable {ADDR_2QUE[15:0]}
+#define_output_delay -disable {AL_ADS}
+#define_output_delay -disable {AL_CE[1:0]}
+#define_output_delay -disable {AL_CNTEN}
+#define_output_delay -disable {AL_CNTRST}
+#define_output_delay -disable {AL_FT}
+#define_output_delay -disable {AL_OE}
+#define_output_delay -disable {AL_RW}
+#define_output_delay -disable {ALVOUT[1:0]}
+#define_output_delay -disable {ALVOUTB[1:0]}
+#define_output_delay -disable {ALVTTTLOUT2}
+#define_output_delay -disable {AR_CE1}
+#define_output_delay -disable {AR_FT}
+#define_input_delay -disable {B_DATA_READY}
+#define_input_delay -disable {B_LVDS_IN}
+#define_input_delay -disable {B_TDC_SERIAL_BP_IN}
+#define_input_delay -disable {B_TDC_SERIAL_IN}
+#define_input_delay -disable {B_TDC_SERIAL_OUT}
+#define_input_delay -disable {B_TDC_TOKEN_BP}
+#define_output_delay -disable {BL_ADS}
+#define_output_delay -disable {BL_CE[1:0]}
+#define_output_delay -disable {BL_CNTEN}
+#define_output_delay -disable {BL_CNTRST}
+#define_output_delay -disable {BL_FT}
+#define_output_delay -disable {BL_OE}
+#define_output_delay -disable {BL_RW}
+#define_output_delay -disable {BLVOUT[1:0]}
+#define_output_delay -disable {BLVOUTB[1:0]}
+#define_output_delay -disable {BLVTTTLOUT2}
+#define_output_delay -disable {BR_CE1}
+#define_output_delay -disable {BR_FT}
+#define_input_delay -disable {C_DATA_READY}
+#define_input_delay -disable {C_LVDS_IN}
+#define_input_delay -disable {C_TDC_SERIAL_BP_IN}
+#define_input_delay -disable {C_TDC_SERIAL_IN}
+#define_input_delay -disable {C_TDC_SERIAL_OUT}
+#define_input_delay -disable {C_TDC_TOKEN_BP}
+#define_input_delay -disable {CCLK}
+#define_output_delay -disable {CLVOUT[1:0]}
+#define_output_delay -disable {CLVOUTB[1:0]}
+#define_output_delay -disable {CLVTTTLOUT2}
+#define_input_delay -disable {CSP0_CPLD}
+#define_input_delay -disable {CTS1}
+#define_input_delay -disable {D_DATA_READY}
+#define_input_delay -disable {D_LVDS_IN}
+#define_input_delay -disable {D_TDC_SERIAL_BP_IN}
+#define_input_delay -disable {D_TDC_SERIAL_IN}
+#define_input_delay -disable {D_TDC_SERIAL_OUT}
+#define_input_delay -disable {D_TDC_TOKEN_BP}
+#define_input_delay -disable {DACK[1:0]}
+#define_input_delay -disable {DATA[15:0]}
+#define_output_delay -disable {DATA[15:0]}
+#define_output_delay -disable {DLVOUT[1:0]}
+#define_output_delay -disable {DLVOUTB[1:0]}
+#define_output_delay -disable {DLVTTTLOUT2}
+#define_output_delay -disable {DREQ[1:0]}
+#define_output_delay -disable {END_EVENT_IN}
+#define_input_delay -disable {END_EVENT_OUT}
+#define_output_delay -disable {ETRAX_WAIT}
+#define_input_delay -disable {FIFO_EF}
+#define_input_delay -disable {FIFO_FF}
+#define_input_delay -disable {FIFO_HF}
+#define_output_delay -disable {FIFO_LD}
+#define_output_delay -disable {FIFO_OE}
+#define_input_delay -disable {FIFO_PAE}
+#define_input_delay -disable {FIFO_PAF}
+#define_output_delay -disable {FIFO_REN}
+#define_output_delay -disable {FIFO_RT}
+#define_output_delay -disable {FIFO_WEN}
+#define_output_delay -disable {FPGA_CPLD_10}
+#define_input_delay -disable {FPGA_CPLD_11}
+#define_output_delay -disable {FPGA_CPLD_12}
+#define_input_delay -disable {FPGA_CPLD_13}
+#define_output_delay -disable {FPGA_CPLD_14}
+#define_output_delay -disable {FPGA_CPLD_15}
+#define_output_delay -disable {FPGA_CPLD_16}
+#define_input_delay -disable {FPGA_CPLD_17}
+#define_input_delay -disable {FPGA_CPLD_18}
+#define_input_delay -disable {FPGA_CPLD_19}
+#define_output_delay -disable {FPGA_CPLD_20}
+#define_output_delay -disable {FPGA_CPLD_3}
+#define_input_delay -disable {FPGA_CPLD_4}
+#define_input_delay -disable {FPGA_CPLD_5}
+#define_output_delay -disable {FPGA_CPLD_6}
+#define_output_delay -disable {FPGA_CPLD_7}
+#define_output_delay -disable {FPGA_CPLD_8}
+#define_output_delay -disable {FPGA_CPLD_9}
+#define_input_delay -disable {FPGA_DONE}
+#define_input_delay -disable {FPGA_PROG}
+#define_input_delay -disable {FPGA_TCK}
+#define_input_delay -disable {FPGA_TDI}
+#define_input_delay -disable {FPGA_TDO}
+#define_input_delay -disable {FPGA_TMS}
+#define_output_delay -disable {GET_DATA}
+#define_input_delay -disable {INTA}
+#define_output_delay -disable {IRQ}
+#define_input_delay -disable {M[2:0]}
+#define_output_delay -disable {NMI}
+#define_input_delay -disable {PA[7:0]}
+#define_input_delay -disable {PB[7:0]}
+#define_input_delay -disable {PHY_RESET}
+#define_input_delay -disable {RD}
+#define_output_delay -disable {RERUN}
+#define_input_delay -disable {RESETB}
+#define_input_delay -disable {RTS1}
+#define_input_delay -disable {RXD1}
+#define_input_delay -disable {SPARE_IN}
+#define_output_delay -disable {SPARE_OUT}
+#define_input_delay -disable {TB_R}
+#define_output_delay -disable {TB_RB}
+#define_input_delay -disable {TB_RD[3:0]}
+#define_output_delay -disable {TB_RE}
+#define_input_delay -disable {TB_RS}
+#define_input_delay -disable {TB_T}
+#define_output_delay -disable {TB_TB}
+#define_input_delay -disable {TB_TD[3:0]}
+#define_output_delay -disable {TB_TE}
+#define_input_delay -disable {TB_TS}
+#define_output_delay -disable {TDC_CLOCK_ENABLE}
+#define_output_delay -disable {TDC_DATA[15:0]}
+#define_input_delay -disable {TDC_OUT[31:0]}
+#define_output_delay -disable {TDC_TOKEN_IN}
+#define_input_delay -disable {TDC_TOKEN_OUT}
+#define_output_delay -disable {TDV_BU_RESET}
+#define_output_delay -disable {TDV_BU_RESETB}
+#define_output_delay -disable {TDV_EV_RESET}
+#define_output_delay -disable {TDV_EV_RESETB}
+#define_input_delay -disable {TESTB}
+#define_input_delay -disable {TRIGG}
+#define_output_delay -disable {TRIGGER}
+#define_output_delay -disable {TRIGGERB}
+#define_input_delay -disable {TXD1}
+#define_input_delay -disable {WR0}
+
+#
+# Registers
+#
+
+#
+# Multicycle Path
+#
+
+#
+# False Path
+#
+
+#
+# Path Delay
+#
+
+#
+# Attributes
+#
+
+#
+# I/O standards
+#
+
+#
+# Compile Points
+#
+
+#
+# Other Constraints
+#
--- /dev/null
+
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 08:27:11 01/24/2007
+-- Design Name: rpc_trb_v2_fpga
+-- Module Name: rpc_trb_v2_fpga_tb.vhd
+-- Project Name: trbv2
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: rpc_trb_v2_fpga
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all;
+USE ieee.numeric_std.ALL;
+
+ENTITY rpc_trb_v2_fpga_tb_vhd IS
+END rpc_trb_v2_fpga_tb_vhd;
+
+ARCHITECTURE behavior OF rpc_trb_v2_fpga_tb_vhd IS
+
+ -- Component Declaration for the Unit Under Test (UUT)
+ COMPONENT rpc_trb_v2_fpga
+ PORT(
+ VIRT_CLK : IN std_logic;
+ VIRT_CLKB : IN std_logic;
+ RESET_VIRT : IN std_logic;
+ A_RESERVED : IN std_logic;
+ A_TEMP : IN std_logic;
+ B_RESERVED : IN std_logic;
+ B_TEMP : IN std_logic;
+ C_RESERVED : IN std_logic;
+ C_TEMP : IN std_logic;
+ D_RESERVED : IN std_logic;
+ D_TEMP : IN std_logic;
+ VIR_TRIG : IN std_logic;
+ VIR_TRIGB : IN std_logic;
+ DSP_HBG : IN std_logic;
+ TLK_CLK : IN std_logic;
+ TLK_RXD : IN std_logic_vector(15 downto 0);
+ TLK_RX_CLK : IN std_logic;
+ TLK_RX_DV : IN std_logic;
+ TLK_RX_ER : IN std_logic;
+ VIRT_TDO : IN std_logic;
+ FS_PC : INOUT std_logic_vector(17 downto 0);
+ DSPDAT : INOUT std_logic_vector(31 downto 0);
+ DBAD : OUT std_logic;
+ DGOOD : OUT std_logic;
+ DINT : OUT std_logic;
+ DWAIT : OUT std_logic;
+ TDC_RESET : OUT std_logic;
+ FS_PB : OUT std_logic_vector(17 downto 0);
+ ETRAX_IRQ : OUT std_logic;
+ DSPADDR : OUT std_logic_vector(31 downto 0);
+ DSP_HBR : OUT std_logic;
+ DSP_RD : INOUT std_logic;
+ TLK_ENABLE : OUT std_logic;
+ TLK_LCKREFN : OUT std_logic;
+ TLK_LOOPEN : OUT std_logic;
+ TLK_PRBSEN : OUT std_logic;
+ TLK_TXD : OUT std_logic_vector(15 downto 0);
+ TLK_TX_EN : OUT std_logic;
+ TLK_TX_ER : OUT std_logic;
+ SFP_TX_DIS : OUT std_logic;
+ VIRT_TCK : OUT std_logic;
+ VIRT_TDI : OUT std_logic;
+ VIRT_TMS : OUT std_logic;
+ VIRT_TRST : OUT std_logic;
+ DSP_WRH :inout std_logic;
+ DSP_WRL :inout std_logic;
+ DSP_RESET : out std_logic;
+ DSP_BRST : inout std_logic;
+ DSP_ACK : in std_logic;
+ DSP_BM : in std_logic;
+ ADO_TTL : out std_logic_vector(46 downto 0)
+ );
+ END COMPONENT;
+
+ --Inputs
+ SIGNAL VIRT_CLK : std_logic := '0';
+ SIGNAL VIRT_CLKB : std_logic := '0';
+ SIGNAL RESET_VIRT : std_logic := '0';
+ SIGNAL A_RESERVED : std_logic := '0';
+ SIGNAL A_TEMP : std_logic := '0';
+ SIGNAL B_RESERVED : std_logic := '0';
+ SIGNAL B_TEMP : std_logic := '0';
+ SIGNAL C_RESERVED : std_logic := '0';
+ SIGNAL C_TEMP : std_logic := '0';
+ SIGNAL D_RESERVED : std_logic := '0';
+ SIGNAL D_TEMP : std_logic := '0';
+ SIGNAL VIR_TRIG : std_logic := '0';
+ SIGNAL VIR_TRIGB : std_logic := '0';
+ SIGNAL DSP_HBG : std_logic := '0';
+ SIGNAL TLK_CLK : std_logic := '0';
+ SIGNAL TLK_RX_CLK : std_logic := '0';
+ SIGNAL TLK_RX_DV : std_logic := '0';
+ SIGNAL TLK_RX_ER : std_logic := '0';
+ SIGNAL VIRT_TDO : std_logic := '0';
+ SIGNAL TLK_RXD : std_logic_vector(15 downto 0) := (others=>'0');
+
+ --BiDirs
+ SIGNAL FS_PC : std_logic_vector(17 downto 0);
+ SIGNAL DSPDAT : std_logic_vector(31 downto 0);
+
+ --Outputs
+ SIGNAL DBAD : std_logic;
+ SIGNAL DGOOD : std_logic;
+ SIGNAL DINT : std_logic;
+ SIGNAL DWAIT : std_logic;
+ SIGNAL TDC_RESET : std_logic;
+ SIGNAL FS_PB : std_logic_vector(17 downto 0);
+ SIGNAL ETRAX_IRQ : std_logic;
+ SIGNAL DSPADDR : std_logic_vector(31 downto 0);
+ SIGNAL DSP_HBR : std_logic;
+ SIGNAL DSP_RD : std_logic;
+ SIGNAL TLK_ENABLE : std_logic;
+ SIGNAL TLK_LCKREFN : std_logic;
+ SIGNAL TLK_LOOPEN : std_logic;
+ SIGNAL TLK_PRBSEN : std_logic;
+ SIGNAL TLK_TXD : std_logic_vector(15 downto 0);
+ SIGNAL TLK_TX_EN : std_logic;
+ SIGNAL TLK_TX_ER : std_logic;
+ SIGNAL SFP_TX_DIS : std_logic;
+ SIGNAL VIRT_TCK : std_logic;
+ SIGNAL VIRT_TDI : std_logic;
+ SIGNAL VIRT_TMS : std_logic;
+ SIGNAL VIRT_TRST : std_logic;
+ signal test_synch_00 : std_logic;
+ SIGNAL DSP_WRH :std_logic;
+ SIGNAL DSP_WRL : std_logic;
+ SIGNAL DSP_RESET : std_logic;
+ SIGNAL DSP_BRST : std_logic;
+ SIGNAL DSP_ACK : std_logic;
+ SIGNAL DSP_BM : std_logic;
+BEGIN
+
+ -- Instantiate the Unit Under Test (UUT)
+ uut: rpc_trb_v2_fpga PORT MAP(
+ VIRT_CLK => VIRT_CLK,
+ VIRT_CLKB => VIRT_CLKB,
+ RESET_VIRT => RESET_VIRT,
+ DBAD => DBAD,
+ DGOOD => DGOOD,
+ DINT => DINT,
+ DWAIT => DWAIT,
+ A_RESERVED => A_RESERVED,
+ A_TEMP => A_TEMP,
+ B_RESERVED => B_RESERVED,
+ B_TEMP => B_TEMP,
+ C_RESERVED => C_RESERVED,
+ C_TEMP => C_TEMP,
+ D_RESERVED => D_RESERVED,
+ D_TEMP => D_TEMP,
+ VIR_TRIG => VIR_TRIG,
+ VIR_TRIGB => VIR_TRIGB,
+ TDC_RESET => TDC_RESET,
+ FS_PB => FS_PB,
+ FS_PC => FS_PC,
+ ETRAX_IRQ => ETRAX_IRQ,
+ DSPADDR => DSPADDR,
+ DSPDAT => DSPDAT,
+ DSP_HBG => DSP_HBG,
+ DSP_HBR => DSP_HBR,
+ DSP_RD => DSP_RD,
+ TLK_CLK => TLK_CLK,
+ TLK_ENABLE => TLK_ENABLE,
+ TLK_LCKREFN => TLK_LCKREFN,
+ TLK_LOOPEN => TLK_LOOPEN,
+ TLK_PRBSEN => TLK_PRBSEN,
+ TLK_RXD => TLK_RXD,
+ TLK_RX_CLK => TLK_RX_CLK,
+ TLK_RX_DV => TLK_RX_DV,
+ TLK_RX_ER => TLK_RX_ER,
+ TLK_TXD => TLK_TXD,
+ TLK_TX_EN => TLK_TX_EN,
+ TLK_TX_ER => TLK_TX_ER,
+ SFP_TX_DIS => SFP_TX_DIS,
+ VIRT_TCK => VIRT_TCK,
+ VIRT_TDI => VIRT_TDI,
+ VIRT_TDO => VIRT_TDO,
+ VIRT_TMS => VIRT_TMS,
+ VIRT_TRST => VIRT_TRST,
+ DSP_WRH => DSP_WRH,
+ DSP_WRL => DSP_WRL,
+ DSP_BRST => DSP_BRST,
+ DSP_ACK => DSP_ACK,
+ DSP_BM => DSP_BM
+ );
+
+ etrax_intf : PROCESS
+ BEGIN
+
+ --reading DSP(dev number 1)
+ wait for 10 ns;
+ RESET_VIRT <= '0';
+ wait for 10 ns;
+ RESET_VIRT <= '1';
+ wait for 10 ns;
+ FS_PC(15 downto 0) <= x"0000";
+ FS_PC(16) <= '0';
+ FS_PC(17) <= '0';
+ wait for 20 ns;
+ FS_PC(16) <= '1';
+ wait for 20 ns;
+ FS_PC(15) <= '1'; --read mode
+ FS_PC(14 downto 8) <= (others => '0');
+ FS_PC(7 downto 0) <= x"01"; --device
+ FS_PC(16) <= '0';
+ FS_PC(17) <= '0';
+ wait for 20 ns;
+ FS_PC(15 downto 0) <= x"0000"; --address upper part
+ FS_PC(16) <= '1';
+ FS_PC(17) <= '0';
+ wait for 20 ns;
+ FS_PC(16) <= '0';
+ wait for 20 ns;
+ FS_PC(16) <= '1';
+ FS_PC(15 downto 0) <= x"0005"; --adrees lower part
+ FS_PC(16) <= '1';
+ FS_PC(17) <= '0';
+ wait for 20 ns;
+ FS_PC(16) <= '0';
+ wait until FS_PB(16)= '1';
+ FS_PC(16) <= '1';
+ wait for 20 ns;
+ FS_PC(16) <= '0';
+ wait until FS_PB(16) = '0';
+ FS_PC(16) <= '1';
+ wait for 20 ns;
+ FS_PC(16) <= '0';
+ wait until FS_PB(16)= '1';
+ FS_PC(16) <= '1';
+ wait for 20 ns;
+ FS_PC(16) <= '0';
+ --writing DSP
+ wait for 20 ns;
+ FS_PC(16) <= '1';
+ test_synch_00 <= '1';
+ wait for 20 ns;
+ FS_PC(15) <= '0'; --write mode
+ FS_PC(14 downto 8) <= (others => '0');
+ FS_PC(7 downto 0) <= x"01"; --device
+ FS_PC(16) <= '0';
+ FS_PC(17) <= '0';
+ wait for 20 ns;
+ FS_PC(15 downto 0) <= x"6754"; --address upper part
+ FS_PC(16) <= '1';
+ FS_PC(17) <= '0';
+ wait for 20 ns;
+ FS_PC(16) <= '0';
+ wait for 20 ns;
+ FS_PC(16) <= '1';
+ FS_PC(15 downto 0) <= x"ad05"; --adrees lower part
+ FS_PC(16) <= '1';
+ FS_PC(17) <= '0';
+ wait for 20 ns;
+ FS_PC(16) <= '0';
+ wait for 20 ns;
+ FS_PC(15 downto 0) <= x"dada"; --data upper part
+ FS_PC(16) <= '1';
+ FS_PC(17) <= '0';
+ wait for 20 ns;
+ FS_PC(16) <= '0';
+ wait for 20 ns;
+ FS_PC(15 downto 0) <= x"baca"; --data upper part
+ FS_PC(16) <= '1';
+ FS_PC(17) <= '0';
+ wait for 20 ns;
+ FS_PC(16) <= '0';
+ wait for 20 ns;
+ test_synch_00 <= '0';
+ wait until FS_PB(16)= '1';
+ FS_PC(16) <= '1';
+ wait for 20 ns;
+ FS_PC(16) <= '0';
+
+-- process
+-- begin
+-- VIRT_CLK <= '0';
+-- VIRT_CLKB <= '1';
+-- wait for 10 ns;
+-- VIRT_CLKB <= '0';
+-- VIRT_CLK <= '1';
+-- wait for 10 ns;
+-- end process;
+ -- Place stimulus here
+
+ wait; -- will wait forever
+ end process;
+
+ clock_gclk : process
+ begin
+ VIRT_CLK <= '0';
+ VIRT_CLKB <= '1';
+ wait for 5 ns;
+ VIRT_CLKB <= '0';
+ VIRT_CLK <= '1';
+ wait for 5 ns;
+ end process;
+
+ dsp : process
+ begin
+ DSP_ACK <= '1';
+ DSP_HBG <= '1';
+ wait for 20 ns;
+ DSPDAT <= (others => 'Z');
+ wait until DSP_HBR = '0';
+ wait for 8 ns;
+ DSP_HBG <= '0';
+ DSPDAT <= x"babeface";
+ wait for 10 ns;
+ DSP_ACK <= '1';
+ wait until DSP_HBR = '1';
+ DSP_ACK <= '0';
+ DSP_HBG <= '1';
+ DSPDAT <= (others => 'Z');
+ wait until test_synch_00 = '1';
+ wait until DSP_HBR = '0';
+ wait for 8 ns;
+ DSP_HBG <= '0';
+ wait until DSP_HBR = '1';
+ DSP_HBG <= '1';
+ wait;
+ end process;
+ -----------------------------------------------------------------------
+ -- TLK
+ -----------------------------------------------------------------------
+ clock_tlk_clk : process
+ begin
+ TLK_CLK <= '0';
+ wait for 5 ns;
+ TLK_CLK <= '1';
+ wait for 5 ns;
+ end process;
+ clock_tlk_rx_clk : process
+ begin
+ TLK_RX_CLK <= '0';
+ wait for 5 ns;
+ TLK_RX_CLK <= '1';
+ wait for 5 ns;
+ end process;
+ RX_ER: process
+ begin
+ TLK_RX_ER <= '0';
+ wait for 2200 ns;
+ TLK_RX_ER <= '1';
+ wait for 120 ns;
+ end process;
+ TLK_RXD <= TLK_TXD;
+ --TLK_RX_ER <= '0';
+ TLK_RX_DV <= '1';
+
+END;
--- /dev/null
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use IEEE.NUMERIC_STD.all;
+
+--use work.support.all;
+ library UNISIM;
+ use UNISIM.VCOMPONENTS.all;
+
+-- -- Uncomment the following lines to use the declarations that are
+-- -- provided for instantiating Xilinx primitive components.
+-- library UNISIM;
+-- use UNISIM.VComponents.all;
+
+entity trigger_logic is
+
+ port (
+ CLK : in std_logic;
+ RESET : in std_logic;
+ LVL1_TRIGGER_CODE : in std_logic_vector(3 downto 0);
+ LVL1_TRIGGER_TAG : in std_logic_vector(7 downto 0);
+ TDC_CODE : out std_logic_vector(3 downto 0);
+ TDC_TAG : out std_logic_vector(7 downto 0);
+ LVL2_TRIGGER : in std_logic_vector(1 downto 0); --0 trigger, 1 value
+ LVL1_TRIGGER : in std_logic;
+ LVL1_TDC_TRIGG : out std_logic;
+ LVL2_TDC_TRIGG : out std_logic_vector(1 downto 0);
+ TRIGG_WITHOUT_HADES : in std_logic;
+ TDC_CONTROL_REGISTER : in std_logic_vector(7 downto 0);
+ DELAY_TRIGGER : in std_logic_vector(7 downto 0);
+ LVL1_BUSY : in std_logic;
+ LVL2_BUSY : in std_logic;
+ TRB_ACK_LVL1 : out std_logic;
+ TRB_ACK_LVL2 : out std_logic
+ );
+end trigger_logic;
+
+architecture trigger_logic of trigger_logic is
+ component edge_to_pulse
+ port (
+ clock : in std_logic;
+ en_clk : in std_logic;
+ signal_in : in std_logic;
+ pulse : out std_logic);
+ end component;
+ component up_counter_17bit
+ port (
+ QOUT : out std_logic_vector(16 downto 0);
+ UP : in std_logic;
+ CLK : in std_logic;
+ CLR : in std_logic);
+ end component;
+
+ type DELAY_FSM_TRIGG is
+ (IDLE ,DELAY_1,DELAY_2,DELAY_3,DELAY_4,DELAY_5);
+ signal delay_fsm_currentstate, delay_fsm_nextstate: DELAY_FSM_TRIGG;
+ type LVL1_START_FSM is
+ (IDLE, SEND_LVL1_TRIGG_1, SEND_LVL1_TRIGG_2, SEND_LVL1_TRIGG_3, SEND_LVL1_TRIGG_4, WAIT_FOR_ACK);
+ signal LVL1_START_fsm_currentstate, LVL1_START_fsm_nextstate : LVL1_START_FSM;
+ type ACK_LVL1_STATE_MACHINE is
+ (IDLE, ACK_LVL1_PULSE_1, ACK_LVL1_CHECK_COMPLETION);
+ signal ACK_LVL1_STATE : ACK_LVL1_STATE_MACHINE;
+ type LVL2_START_FSM is
+ (IDLE, SEND_LVL2_TRIGG_1, SEND_LVL2_TRIGG_2, WAIT_FOR_ACK);
+ signal LVL2_START_fsm_currentstate,LVL2_START_fsm_nextstate : LVL2_START_FSM;
+ type ACK_LVL2_STATE_MACHINE is
+ (IDLE, ACK_LVL2_PULSE_1, ACK_LVL2_CHECK_COMPLETION);
+ signal ACK_LVL2_STATE : ACK_LVL2_STATE_MACHINE;
+ signal lvl1_trigger_pulse : std_logic;
+ signal lvl2_trigger_pulse : std_logic;
+ signal lvl1_tag_reg : std_logic_vector(7 downto 0);
+ signal lvl1_code_reg : std_logic_vector(3 downto 0);
+ signal delay_up : std_logic;
+ signal delay_clr : std_logic;
+ signal delay_qout : std_logic_vector(16 downto 0);
+ signal lvl1_trigger_pulse_start : std_logic;
+ signal lvl1_trigger_pulse_delay : std_logic;
+
+
+begin
+ -----------------------------------------------------------------------------
+ -- LVL1 trigger logic
+ -----------------------------------------------------------------------------
+-- resetTDCBunchCounter <= '1'; --remember to reset after each LVL1
+-- busy or just in the begginning ?!
+-- resetTDCEventCounter <= '1'; --rememebr to reset at the beggining,
+-----------------------------------------------------------------------------
+ LVL1_START_PULSER : edge_to_pulse
+ port map (
+ clock => CLK,
+ en_clk => '1',
+ signal_in => LVL1_TRIGGER,
+ pulse => lvl1_trigger_pulse);
+ -----------------------------------------------------------------------------
+ -- delay for trigger deliverd to TDC
+ -----------------------------------------------------------------------------
+ DELAY_COUNTER : up_counter_17bit
+ port map (
+ CLK => CLK,
+ UP => delay_up,
+ CLR => delay_clr,
+ QOUT => delay_qout
+ );
+ DELAY_FSM_CLOCK : process (CLK, RESET)
+ begin -- process DELAY_FSM_CLOCK
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ delay_fsm_currentstate <= IDLE;
+ else
+ delay_fsm_currentstate <= delay_fsm_nextstate;
+ end if;
+ end if;
+ end process DELAY_FSM_CLOCK;
+ -- purpose: delay trigger whitch is sending to TDC
+ TO_DELAY_TRIGG : process (CLK)
+ begin -- process TO_DELAY_TRIGG
+ case (delay_fsm_currentstate) is
+ when IDLE =>
+ lvl1_trigger_pulse_delay <= '0';
+ delay_clr <= '1';
+ delay_up <= '0';
+ if lvl1_trigger_pulse = '1' then
+ delay_fsm_nextstate <= DELAY_1;
+ else
+ delay_fsm_nextstate <= IDLE;
+ end if;
+ when DELAY_1 =>
+ lvl1_trigger_pulse_delay <= '0';
+ delay_clr <= '0';
+ delay_up <= '1';
+ if delay_qout = DELAY_TRIGGER(7 downto 0) then
+ delay_fsm_nextstate <= DELAY_2;
+ else
+ delay_fsm_nextstate <= DELAY_1;
+ end if;
+ when DELAY_2 =>
+ lvl1_trigger_pulse_delay <= '1';
+ delay_clr <= '1';
+ delay_up <= '0';
+ delay_fsm_nextstate <= IDLE;
+ when others =>
+ lvl1_trigger_pulse_delay <= '0';
+ delay_clr <= '1';
+ delay_up <= '0';
+ delay_fsm_nextstate <= IDLE;
+ end case;
+ end process TO_DELAY_TRIGG;
+ lvl1_trigger_pulse_start <= lvl1_trigger_pulse when DELAY_TRIGGER = x"00" else lvl1_trigger_pulse_delay;
+ SAVE_LVL1_TRIGG_VALUES : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ lvl1_tag_reg <= (others => '0');
+ lvl1_code_reg <= (others => '0');
+ elsif lvl1_trigger_pulse = '1' then
+ lvl1_tag_reg <= LVL1_TRIGGER_TAG;
+ lvl1_code_reg <= LVL1_TRIGGER_CODE;
+ else
+ lvl1_tag_reg <= lvl1_tag_reg;
+ lvl1_code_reg <= lvl1_code_reg;
+ end if;
+ end if;
+ end process SAVE_LVL1_TRIGG_VALUES;
+ TDC_TAG <= lvl1_tag_reg;
+ TDC_CODE <= lvl1_code_reg;
+ LVL1_START : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ LVL1_START_fsm_currentstate <= IDLE;
+ else
+ LVL1_START_fsm_currentstate <= LVL1_START_fsm_nextstate;
+ end if;
+ end if;
+ end process LVL1_START;
+ LVL1_START_FSM_PROC : process (LVL1_START_fsm_currentstate, CLK,lvl1_trigger_pulse_start)
+ begin
+ case (LVL1_START_fsm_currentstate) is
+ when IDLE =>
+ LVL1_TDC_TRIGG <= '0';
+ if (lvl1_trigger_pulse_start = '1' and LVL1_TRIGGER_CODE /= x"d") or
+ (TRIGG_WITHOUT_HADES ='1' and TDC_CONTROL_REGISTER(0) = '1') then
+ LVL1_START_fsm_nextstate <= SEND_LVL1_TRIGG_1;
+ else
+ LVL1_START_fsm_nextstate <= IDLE;
+ end if;
+ when SEND_LVL1_TRIGG_1 => --4 clock of 100MHz - to generate token
+ LVL1_TDC_TRIGG <= '1';
+ LVL1_START_fsm_nextstate <= SEND_LVL1_TRIGG_2;
+ when SEND_LVL1_TRIGG_2 =>
+ LVL1_TDC_TRIGG <= '1';
+ LVL1_START_fsm_nextstate <= SEND_LVL1_TRIGG_3;
+ when SEND_LVL1_TRIGG_3 =>
+ LVL1_TDC_TRIGG <= '1';
+ LVL1_START_fsm_nextstate <= SEND_LVL1_TRIGG_4;
+ when SEND_LVL1_TRIGG_4 =>
+ LVL1_TDC_TRIGG <= '1';
+ LVL1_START_fsm_nextstate <= WAIT_FOR_ACK;
+ when WAIT_FOR_ACK =>
+ LVL1_TDC_TRIGG <= '0';
+ if ACK_LVL1_STATE = ACK_LVL1_pulse_1 then
+ LVL1_START_fsm_nextstate <= IDLE;
+ else
+ LVL1_START_fsm_nextstate <= WAIT_FOR_ACK;
+ end if;
+ when others =>
+ LVL1_START_fsm_nextstate <= IDLE;
+ LVL1_TDC_TRIGG <= '0';
+ end case;
+ end process LVL1_START_FSM_PROC;
+ ACK_LVL1_NEXT_STATE_DECODE : process (CLK, RESET, ACK_LVL1_STATE)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ ACK_LVL1_STATE <= IDLE;
+ else
+ case (ACK_LVL1_STATE) is
+ when IDLE =>
+ TRB_ACK_LVL1 <= '0';
+ if LVL1_BUSY = '1' then
+ ACK_LVL1_STATE <= ACK_LVL1_CHECK_COMPLETION;
+ elsif lvl1_trigger_pulse_start = '1' and LVL1_TRIGGER_CODE = x"d" then
+ ACK_LVL1_STATE <= ACK_LVL1_PULSE_1;
+ else
+ ACK_LVL1_STATE <= IDLE;
+ end if;
+ when ACK_LVL1_CHECK_COMPLETION =>
+ TRB_ACK_LVL1 <= '0';
+ if LVL1_BUSY = '1'then
+ ACK_LVL1_STATE <= ACK_LVL1_CHECK_COMPLETION;
+ else
+ ACK_LVL1_STATE <= ACK_LVL1_PULSE_1;
+ end if;
+ when ACK_LVL1_PULSE_1 =>
+ TRB_ACK_LVL1 <= '1';
+ ACK_LVL1_STATE <= IDLE;
+ when others =>
+ ACK_LVL1_STATE <= IDLE;
+ end case;
+ end if;
+ end if;
+ end process;
+ -----------------------------------------------------------------------------
+ -- LVL2 trigger logic
+ -----------------------------------------------------------------------------
+ LVL2_START_PULSER : edge_to_pulse
+ port map (
+ clock => CLK,
+ en_clk => '1',
+ signal_in => LVL2_TRIGGER(0),
+ pulse => lvl2_trigger_pulse);
+
+ LVL2_START : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ LVL2_START_fsm_currentstate <= IDLE;
+ else
+ LVL2_START_fsm_currentstate <= LVL2_START_fsm_nextstate;
+ end if;
+ end if;
+ end process LVL2_START;
+ LVL2_START_FSM_PROC : process (LVL2_START_fsm_currentstate,CLK)
+ begin
+ case (LVL2_START_fsm_currentstate) is
+ when IDLE =>
+ LVL2_TDC_TRIGG <= "00";
+ if (lvl2_trigger_pulse='1') or (ACK_LVL1_STATE = ACK_LVL1_PULSE_1 and TDC_CONTROL_REGISTER(0) = '1') then
+ LVL2_START_fsm_nextstate <= SEND_LVL2_TRIGG_1;
+ else
+ LVL2_START_fsm_nextstate <= IDLE;
+ end if;
+ when SEND_LVL2_TRIGG_1 =>
+ LVL2_TDC_TRIGG <= (not(LVL2_TRIGGER(1)) or (TDC_CONTROL_REGISTER(0))) & '1';
+ LVL2_START_fsm_nextstate <= SEND_LVL2_TRIGG_2;
+ when SEND_LVL2_TRIGG_2 =>
+ LVL2_TDC_TRIGG <= "00";
+ LVL2_START_fsm_nextstate <= WAIT_FOR_ACK;
+ when WAIT_FOR_ACK =>
+ LVL2_TDC_TRIGG <= "00";
+ if ACK_LVL2_STATE = ACK_LVL2_PULSE_1 then
+ LVL2_START_fsm_nextstate <= IDLE;
+ else
+ LVL2_START_fsm_nextstate <= WAIT_FOR_ACK;
+ end if;
+ when others =>
+ LVL2_START_fsm_nextstate <= IDLE;
+ LVL2_TDC_TRIGG <= "00";
+ end case;
+ end process LVL2_START_FSM_PROC;
+ ACK_LVL2_NEXT_STATE_DECODE : process (CLK, RESET, ACK_LVL2_STATE)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ ACK_LVL2_STATE <= IDLE;
+ else
+ case (ACK_LVL2_STATE) is
+ when IDLE =>
+ if LVL2_BUSY = '1' then
+ ACK_LVL2_STATE <= ACK_LVL2_CHECK_COMPLETION;
+ else
+ ACK_LVL2_STATE <= IDLE;
+ end if;
+ when ACK_LVL2_CHECK_COMPLETION =>
+ if LVL2_BUSY = '1' then
+ ACK_LVL2_STATE <= ACK_LVL2_CHECK_COMPLETION;
+ else
+ ACK_LVL2_STATE <= ACK_LVL2_PULSE_1;
+ end if;
+ when ACK_LVL2_PULSE_1 =>
+ ACK_LVL2_STATE <= IDLE;
+ when others =>
+ ACK_LVL2_STATE <= IDLE;
+ end case;
+ end if;
+ end if;
+ end process;
+ TRB_ACK_LVL2 <= '1' when ACK_LVL2_STATE = ACK_LVL2_PULSE_1 else '0';
+end trigger_logic;
--- /dev/null
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+-- Uncomment the following lines to use the declarations that are
+-- provided for instantiating Xilinx primitive components.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity up_counter_17bit is
+ Port ( QOUT : out std_logic_vector(16 downto 0);
+ UP : in std_logic;
+ CLK : in std_logic;
+ CLR : in std_logic);
+end up_counter_17bit;
+
+architecture Behavioral of up_counter_17bit is
+
+signal counter: std_logic_vector (16 downto 0);
+
+begin
+
+ process (CLR, UP, CLK)
+
+ begin
+ if CLR = '1' then
+ counter <= "00000000000000000";
+ elsif clk'event and clk = '1' then
+ if UP = '1' then
+ counter <= counter + 1;
+ else
+ counter <= counter;
+ end if;
+end if;
+end process;
+
+QOUT <= counter;
+
+end Behavioral;
--- /dev/null
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+-- Uncomment the following lines to use the declarations that are
+-- provided for instantiating Xilinx primitive components.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity up_down_counter_16_bit is
+ Port ( QOUT : out std_logic_vector(15 downto 0);
+ UP : in std_logic;
+ DOWN : in std_logic;
+ CLK : in std_logic;
+ CLR : in std_logic);
+end up_down_counter_16_bit;
+
+architecture up_down_counter_16_bit of up_down_counter_16_bit is
+
+signal counter: std_logic_vector (15 downto 0);
+signal upDown: std_logic_vector (1 downto 0);
+
+begin
+
+upDown <= up & down;
+
+process (CLR, UPDOWN, CLK)
+begin
+ if CLR = '1' then
+ counter <="0000000000000000";
+ elsif clk'event and clk = '1' then
+ case upDown is
+ when "01" => counter <= counter - 1;
+ when "10" => counter <= counter + 1;
+ when others => counter <= counter;
+ end case;
+ end if;
+end process;
+
+QOUT <= counter;
+
+end up_down_counter_16_bit;
--- /dev/null
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+-- Uncomment the following lines to use the declarations that are
+-- provided for instantiating Xilinx primitive components.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity up_down_counter_10bit is
+ Port ( QOUT : out std_logic_vector(9 downto 0);
+ UP : in std_logic;
+ DOWN : in std_logic;
+ CLK : in std_logic;
+ CLR : in std_logic);
+end up_down_counter_10bit;
+
+architecture Behavioral of up_down_counter_10bit is
+
+signal counter: std_logic_vector (9 downto 0);
+signal upDown: std_logic_vector (1 downto 0);
+
+begin
+
+upDown <= up & down;
+
+process (CLR, UPDOWN, CLK)
+begin
+ if CLR = '1' then
+ counter <="0000000000";
+ elsif clk'event and clk = '1' then
+ case upDown is
+ when "01" => counter <= counter - 1;
+ when "10" => counter <= counter + 1;
+ when others => counter <= counter;
+ end case;
+ end if;
+end process;
+
+QOUT <= counter;
+
+end Behavioral;
--- /dev/null
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+-- Uncomment the following lines to use the declarations that are
+-- provided for instantiating Xilinx primitive components.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity up_down_counter_16_bit is
+ Port ( QOUT : out std_logic_vector(15 downto 0);
+ UP : in std_logic;
+ DOWN : in std_logic;
+ CLK : in std_logic;
+ CLR : in std_logic);
+end up_down_counter_16_bit;
+
+architecture up_down_counter_16_bit of up_down_counter_16_bit is
+
+signal counter: std_logic_vector (15 downto 0);
+signal upDown: std_logic_vector (1 downto 0);
+
+begin
+
+upDown <= up & down;
+
+process (CLR, UPDOWN, CLK)
+begin
+ if CLR = '1' then
+ counter <="0000000000000000";
+ elsif clk'event and clk = '1' then
+ case upDown is
+ when "01" => counter <= counter - 1;
+ when "10" => counter <= counter + 1;
+ when others => counter <= counter;
+ end case;
+ end if;
+end process;
+
+QOUT <= counter;
+
+end up_down_counter_16_bit;
jspc29 / trbv2.git / commitdiff