made project compatible with tdc_v2.2

diff --git a/tdc_release b/tdc_release
index e8932f5de582f92b84622120c7913d0c8d192432..8d7edcef0e0c758c299febe268b9dd5b7b91212a 120000 (symlink)
--- a/tdc_release
+++ b/tdc_release
@@ -1 +1 @@
-../tdc/releases/tdc_v2.1.6
\ No newline at end of file
+../tdc/releases/tdc_v2.2
\ No newline at end of file

diff --git a/tdctemplate/config.vhd b/tdctemplate/config.vhd
index 6679bdf4e8fe6ac80aaf2496993060984650e4ec..bfddb39d7609e8b83c14af6e3930219f45e45ec9 100644 (file)
--- a/tdctemplate/config.vhd
+++ b/tdctemplate/config.vhd
@@ -12,7 +12,7 @@ package config is
 
 --TDC settings
   constant NUM_TDC_MODULES         : integer range 1 to 4  := 1;  -- number of tdc modules to implement
-  constant NUM_TDC_CHANNELS        : integer range 1 to 65 := 3;  -- number of tdc channels per module
+  constant NUM_TDC_CHANNELS        : integer range 1 to 65 := 41;  -- number of tdc channels per module
   constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6  := 5;  --the nearest power of two, for convenience reasons 
   constant DOUBLE_EDGE_TYPE        : integer range 0 to 3  := 3;  --double edge type:  0, 1, 2,  3
   -- 0: single edge only,

diff --git a/tdctemplate/config_compile_gsi.pl b/tdctemplate/config_compile_gsi.pl
index 052a7c11f167ce0ac664ca0db60e8849e10a3836..416f4ee7836c5d523fc2984d2dbc54283e7c44c9 100644 (file)
--- a/tdctemplate/config_compile_gsi.pl
+++ b/tdctemplate/config_compile_gsi.pl
@@ -1,12 +1,12 @@
 TOPNAME                      => "trb3sc_tdctemplate",
 lm_license_file_for_synplify => "27000\@lxcad01.gsi.de",
 lm_license_file_for_par      => "1702\@hadeb05.gsi.de",
-lattice_path                 => '/opt/lattice/diamond/3.4_x64/',
+lattice_path                 => '/opt/lattice/diamond/3.5_x64/',
 synplify_path                => '/opt/synplicity/J-2014.09-SP2',
 #synplify_command             => "/opt/lattice/diamond/3.5_x64/bin/lin64/synpwrap -fg -options",
 synplify_command             => "/opt/synplicity/J-2014.09-SP2/bin/synplify_premier_dp",
 
-nodelist_file                => 'nodelist_gsi_template.txt',
+nodelist_file                => 'nodes_gsi_template.txt',
 
 include_TDC                  => 1,
 

diff --git a/tdctemplate/trb3sc_tdctemplate.lpf b/tdctemplate/trb3sc_tdctemplate.lpf
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..b5995bbdda5b2810baf1be776ab5576f9310ee4e 100644 (file)
--- a/tdctemplate/trb3sc_tdctemplate.lpf
+++ b/tdctemplate/trb3sc_tdctemplate.lpf
@@ -0,0 +1,8 @@
+MULTICYCLE FROM CLKNET "clk_sys" TO CLKNET "clk_full" 1 X ;
+MULTICYCLE FROM CLKNET "clk_full" TO CLKNET "clk_sys" 2 X ;
+
+MULTICYCLE FROM CELL "THE_TDC/GEN_Channels*Channels/Channel200/RingBuffer*FIFO/*" CLKNET clk_full TO CELL "THE_TDC/GEN_Channels*Channels/Channel200/RingBuffer*FIFO/*" CLKNET clk_sys 2x;
+MULTICYCLE FROM CELL "THE_TDC/ReferenceChannel/Channel200/RingBuffer*FIFO/*" CLKNET clk_full TO CELL "THE_TDC/ReferenceChannel/Channel200/RingBuffer*FIFO/*" CLKNET clk_sys 2x;
+
+MULTICYCLE FROM CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" CLKNET clk_sys TO CLKNET clk_sys 5x;
+MULTICYCLE FROM CELL "THE_TDC/reset_tdc*" TO CLKNET clk_full 2x;

diff --git a/tdctemplate/trb3sc_tdctemplate.prj b/tdctemplate/trb3sc_tdctemplate.prj
index ef3b94b40c2bb064ed8f1d20ab63b9df421f6864..49d6a048c57cdb071fd3e8cb5bf6155e97c0664b 100644 (file)
--- a/tdctemplate/trb3sc_tdctemplate.prj
+++ b/tdctemplate/trb3sc_tdctemplate.prj
@@ -179,22 +179,21 @@ add_file -vhdl -lib work "../../trbnet/special/bus_register_handler.vhd"
 add_file -vhdl -lib work "../../trb3sc/tdc_release/tdc_version.vhd"
 add_file -vhdl -lib work "../../trb3sc/tdc_release/tdc_components.vhd"
 add_file -vhdl -lib work "../../trb3sc/tdc_release/bit_sync.vhd"
-add_file -vhdl -lib work "../../trb3sc/tdc_release/BusHandler.vhd"
 add_file -vhdl -lib work "../../trb3sc/tdc_release/BusHandler_record.vhd"
 add_file -vhdl -lib work "../../trb3sc/tdc_release/Channel_200.vhd"
 add_file -vhdl -lib work "../../trb3sc/tdc_release/Channel.vhd"
-add_file -vhdl -lib work "../../trb3sc/tdc_release/Encoder_304_Bit.vhd"
+add_file -vhdl -lib work "../../trb3sc/tdc_release/Encoder_288_Bit.vhd"
+#add_file -vhdl -lib work "../../trb3sc/tdc_release/Encoder_304_Bit.vhd"
 add_file -vhdl -lib work "../../trb3sc/tdc_release/fallingEdgeDetect.vhd"
 add_file -vhdl -lib work "../../trb3sc/tdc_release/hit_mux.vhd"
 add_file -vhdl -lib work "../../trb3sc/tdc_release/LogicAnalyser.vhd"
-add_file -vhdl -lib work "../../trb3sc/tdc_release/Readout.vhd"
+add_file -vhdl -lib work "../../trb3sc/tdc_release/Readout_record.vhd"
 add_file -vhdl -lib work "../../trb3sc/tdc_release/risingEdgeDetect.vhd"
 add_file -vhdl -lib work "../../trb3sc/tdc_release/ROM_encoder_ecp3.vhd"
 add_file -vhdl -lib work "../../trb3sc/tdc_release/ShiftRegisterSISO.vhd"
 add_file -vhdl -lib work "../../trb3sc/tdc_release/Stretcher_A.vhd"
 add_file -vhdl -lib work "../../trb3sc/tdc_release/Stretcher_B.vhd"
 add_file -vhdl -lib work "../../trb3sc/tdc_release/Stretcher.vhd"
-add_file -vhdl -lib work "../../trb3sc/tdc_release/TDC.vhd"
 add_file -vhdl -lib work "../../trb3sc/tdc_release/TDC_record.vhd"
 add_file -vhdl -lib work "../../trb3sc/tdc_release/TriggerHandler.vhd"
 add_file -vhdl -lib work "../../trb3sc/tdc_release/up_counter.vhd"

diff --git a/tdctemplate/trb3sc_tdctemplate.vhd b/tdctemplate/trb3sc_tdctemplate.vhd
index d683dfe77d736aefe986269954f45f3e686673d6..3e8a66d098fcd38b3adc19e22c678927e5e8e798 100644 (file)
--- a/tdctemplate/trb3sc_tdctemplate.vhd
+++ b/tdctemplate/trb3sc_tdctemplate.vhd
@@ -418,19 +418,20 @@ begin
       DEBUG          => c_YES,
       SIMULATION     => c_NO)
     port map (
-      RESET          => reset_i,
-      CLK_TDC        => clk_full_osc,   
-      CLK_READOUT    => clk_sys,        -- Clock for the readout
-      REFERENCE_TIME => TRIG_LEFT,      -- Reference time input
-      HIT_IN         => hit_in_i(NUM_TDC_CHANNELS-1 downto 1),  -- Channel start signals
-      HIT_CAL_IN     => clk_cal,        -- Hits for calibrating the TDC
+      RESET              => reset_i,
+      CLK_TDC            => clk_full_osc,
+      CLK_READOUT        => clk_sys,    -- Clock for the readout
+      REFERENCE_TIME     => TRIG_LEFT,  -- Reference time input
+      HIT_IN             => hit_in_i(NUM_TDC_CHANNELS-1 downto 1),  -- Channel start signals
+      HIT_CAL_IN         => clk_cal,    -- Hits for calibrating the TDC
       -- Trigger signals from handler
-      READOUT_RX     => readout_rx,
-      READOUT_TX     => readout_tx(0),
-      --
-      LOGIC_ANALYSER_OUT => logic_analyser_i,
+      BUSRDO_RX          => readout_rx,
+      BUSRDO_TX          => readout_tx(0),
+      -- Slow control bus
       BUS_RX             => bustdc_rx,
-      BUS_TX             => bustdc_tx
+      BUS_TX             => bustdc_tx,
+      -- Dubug signals
+      LOGIC_ANALYSER_OUT => logic_analyser_i
       );
 
   -- For single edge measurements

diff --git a/template/config_compile_gsi.pl b/template/config_compile_gsi.pl
index 2fa920e37861b1653b5cde28bac6e29666505c06..8fb3469a85b603feab24efe2d178eb68621c449b 100644 (file)
--- a/template/config_compile_gsi.pl
+++ b/template/config_compile_gsi.pl
@@ -6,7 +6,7 @@ synplify_path                => '/opt/synplicity/J-2014.09-SP2',
 #synplify_command             => "/opt/lattice/diamond/3.5_x64/bin/lin64/synpwrap -fg -options",
 synplify_command             => "/opt/synplicity/J-2014.09-SP2/bin/synplify_premier_dp",
 
-nodelist_file                => 'nodelist_gsi_template.txt',
+nodelist_file                => 'nodes_gsi_template.txt',
 
 include_TDC                  => 1,