update project files with automatic ADC reader

diff --git a/adcaddon/trb3sc_adc.prj b/adcaddon/trb3sc_adc.prj
index 7da9261c12aa010fc9865c6b115807efd32c083c..84e0f5dcf1aaecd8b1818dc68b31672eeb06cd9a 100644 (file)
--- a/adcaddon/trb3sc_adc.prj
+++ b/adcaddon/trb3sc_adc.prj
@@ -116,6 +116,8 @@ add_file -vhdl -lib work "../../trb3sc/code/load_settings.vhd"
 add_file -vhdl -lib work "../../trb3sc/code/spi_master_generic.vhd"
 add_file -vhdl -lib work "../../trb3/base/code/input_to_trigger_logic_record.vhd"
 add_file -vhdl -lib work "../../trb3/base/code/input_statistics.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_dp_19x8_preset.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/adc_controller.vhd"
 
 #SlowControl files
 add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd"

diff --git a/backplanemaster/config_compile_frankfurt.pl b/backplanemaster/config_compile_frankfurt.pl
index 0cf8f69174458265df01f173d39e3f41927cde04..b40a05a3546a1c8d40e6fe89243e83a734c76280 100644 (file)
--- a/backplanemaster/config_compile_frankfurt.pl
+++ b/backplanemaster/config_compile_frankfurt.pl
@@ -1,8 +1,8 @@
 TOPNAME                      => "trb3sc_master",
 lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de";
 lm_license_file_for_par      => "1702\@hadeb05.gsi.de",
-lattice_path                 => '/d/jspc29/lattice/diamond/3.10_x64/',
-synplify_path                => '/d/jspc29/lattice/synplify/O-2018.09-SP1',
+lattice_path                 => '/d/jspc29/lattice/diamond/3.12/',
+synplify_path                => '/d/jspc29/lattice/synplify/S-2021.09-SP2',
 #lattice_path                 => '/d/jspc29/lattice/diamond/3.10_x64/',
 #synplify_path                => '/d/jspc29/lattice/synplify/N-2017.09-1/',
 # synplify_command             => "/d/jspc29/lattice/diamond/3.6_x64/bin/lin64/synpwrap -fg -options",

diff --git a/backplanemaster/trb3sc_master.prj b/backplanemaster/trb3sc_master.prj
index 81e1854ac11796f3c2231833a83285d5156fe998..ad3212f58e075669f07fafb5a489a7b55e76fb9b 100644 (file)
--- a/backplanemaster/trb3sc_master.prj
+++ b/backplanemaster/trb3sc_master.prj
@@ -120,6 +120,8 @@ add_file -vhdl -lib work "../../trb3sc/code/load_settings.vhd"
 add_file -vhdl -lib work "../../trb3sc/code/spi_master_generic.vhd"
 add_file -vhdl -lib work "../../trb3/base/code/input_to_trigger_logic_record.vhd"
 add_file -vhdl -lib work "../../trb3/base/code/input_statistics.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_dp_19x8_preset.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/adc_controller.vhd"
 
 #SlowControl files
 add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd"

diff --git a/cts/trb3sc_cts.prj b/cts/trb3sc_cts.prj
index 646d4a6f71638a95d2aed8d446561d7e36608f42..c440017f7efaa8480945a91dc0f2f47944f99f17 100644 (file)
--- a/cts/trb3sc_cts.prj
+++ b/cts/trb3sc_cts.prj
@@ -122,6 +122,8 @@ add_file -vhdl -lib work "../../trbnet/special/uart.vhd"
 add_file -vhdl -lib work "../../trbnet/special/uart_rec.vhd"
 add_file -vhdl -lib work "../../trbnet/special/uart_trans.vhd"
 add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_dp_19x8_preset.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/adc_controller.vhd"
 
 #SlowControl files
 add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd"

diff --git a/halfmasterhub/trb3sc_master.prj b/halfmasterhub/trb3sc_master.prj
index 81e1854ac11796f3c2231833a83285d5156fe998..ad3212f58e075669f07fafb5a489a7b55e76fb9b 100644 (file)
--- a/halfmasterhub/trb3sc_master.prj
+++ b/halfmasterhub/trb3sc_master.prj
@@ -120,6 +120,8 @@ add_file -vhdl -lib work "../../trb3sc/code/load_settings.vhd"
 add_file -vhdl -lib work "../../trb3sc/code/spi_master_generic.vhd"
 add_file -vhdl -lib work "../../trb3/base/code/input_to_trigger_logic_record.vhd"
 add_file -vhdl -lib work "../../trb3/base/code/input_statistics.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_dp_19x8_preset.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/adc_controller.vhd"
 
 #SlowControl files
 add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd"

diff --git a/hub/config_compile_frankfurt.pl b/hub/config_compile_frankfurt.pl
index 6aa6e41e29d875266b45d990ad0887ad63519713..6ed05321fa84dabd797d1d84f34a9332f9235593 100644 (file)
--- a/hub/config_compile_frankfurt.pl
+++ b/hub/config_compile_frankfurt.pl
@@ -1,8 +1,8 @@
 TOPNAME                      => "trb3sc_hub",
 lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de";
-lm_license_file_for_par      => "1702\@hadeb05.gsi.de",
-lattice_path                 => '/d/jspc29/lattice/diamond/3.10_x64',
-synplify_path                => '/d/jspc29/lattice/synplify/O-2018.09-SP1',
+lm_license_file_for_par      => "1710\@jspc29",
+lattice_path                 => '/d/jspc29/lattice/diamond/3.11_x64',
+synplify_path                => '/d/jspc29/lattice/synplify/R-2020.09-SP1',
 #synplify_path                => '/d/jspc29/lattice/synplify/L-2016.09-1/',
 #synplify_command             => "/d/jspc29/lattice/diamond/3.5_x64/bin/lin64/synpwrap -fg -options",
 #synplify_command             => "/d/jspc29/lattice/synplify/J-2014.09-SP2/bin/synplify_premier_dp",

diff --git a/hub/trb3sc_hub.prj b/hub/trb3sc_hub.prj
index 9aa1b1338652f2122c87b15d86e6c708ab2b779d..5862200ee67827d804200ca706f708c74ddc8354 100644 (file)
--- a/hub/trb3sc_hub.prj
+++ b/hub/trb3sc_hub.prj
@@ -120,6 +120,8 @@ add_file -vhdl -lib work "../../trb3sc/code/load_settings.vhd"
 add_file -vhdl -lib work "../../trb3sc/code/spi_master_generic.vhd"
 add_file -vhdl -lib work "../../trb3/base/code/input_to_trigger_logic_record.vhd"
 add_file -vhdl -lib work "../../trb3/base/code/input_statistics.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_dp_19x8_preset.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/adc_controller.vhd"
 
 #SlowControl files
 add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd"

diff --git a/padiwa/trb3sc_padiwa.prj b/padiwa/trb3sc_padiwa.prj
index 297e689dd75599fde00fb2945c43f8b7c6af21b7..6497e53606581c72747352d338981ff4548bcb81 100644 (file)
--- a/padiwa/trb3sc_padiwa.prj
+++ b/padiwa/trb3sc_padiwa.prj
@@ -117,6 +117,8 @@ add_file -vhdl -lib work "../../trb3sc/code/load_settings.vhd"
 add_file -vhdl -lib work "../../trb3sc/code/spi_master_generic.vhd"
 add_file -vhdl -lib work "../../trb3/base/code/input_to_trigger_logic.vhd"
 add_file -vhdl -lib work "../../trb3/base/code/input_statistics.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_dp_19x8_preset.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/adc_controller.vhd"
 
 #SlowControl files
 add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd"

diff --git a/tdctemplate/trb3sc_tdctemplate.prj b/tdctemplate/trb3sc_tdctemplate.prj
index 5b88f31f577d9a9d7134e30062e1101f48963ac3..a397525f44dd39f47934f1662adea274cbc535e6 100644 (file)
--- a/tdctemplate/trb3sc_tdctemplate.prj
+++ b/tdctemplate/trb3sc_tdctemplate.prj
@@ -172,6 +172,8 @@ add_file -vhdl -lib work "../../trb3sc/code/spi_master_generic.vhd"
 add_file -vhdl -lib work "../../trb3/base/code/input_to_trigger_logic_record.vhd"
 add_file -vhdl -lib work "../../trb3/base/code/input_statistics.vhd"
 add_file -vhdl -lib work "../../trb3sc/code/fee_signals.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_dp_19x8_preset.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/adc_controller.vhd"
 
 #SlowControl files
 add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd"

diff --git a/template/trb3sc_basic.prj b/template/trb3sc_basic.prj
index 75bfd566b6929c9d8bf783003c8d2cc6b9ef540b..ca2c3fa6841529669d1d8f2dbc13c037f3783e7a 100644 (file)
--- a/template/trb3sc_basic.prj
+++ b/template/trb3sc_basic.prj
@@ -120,6 +120,8 @@ add_file -vhdl -lib work "../../trb3sc/code/load_settings.vhd"
 add_file -vhdl -lib work "../../trb3sc/code/spi_master_generic.vhd"
 add_file -vhdl -lib work "../../trb3/base/code/input_to_trigger_logic_record.vhd"
 add_file -vhdl -lib work "../../trb3/base/code/input_statistics.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_dp_19x8_preset.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/adc_controller.vhd"
 
 #SlowControl files
 add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd"

diff --git a/triggerbox/trb3sc_triggerbox.prj b/triggerbox/trb3sc_triggerbox.prj
index 5b07f803949e375fee96c2452030dca525ffcbe2..9c5599ebc8559b9d16f0373662cde85e62e6f0b3 100644 (file)
--- a/triggerbox/trb3sc_triggerbox.prj
+++ b/triggerbox/trb3sc_triggerbox.prj
@@ -121,6 +121,8 @@ add_file -vhdl -lib work "../../trb3sc/code/load_settings.vhd"
 add_file -vhdl -lib work "../../trb3sc/code/spi_master_generic.vhd"
 add_file -vhdl -lib work "../../trb3/base/code/input_to_trigger_logic_record.vhd"
 add_file -vhdl -lib work "../../trb3/base/code/input_statistics.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_dp_19x8_preset.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/adc_controller.vhd"
 
 #SlowControl files
 add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd"