Corrected register addresses for Generator

diff --git a/mupix/Mupix8/sources/FrameGenMux2.vhd b/mupix/Mupix8/sources/FrameGenMux2.vhd
index 37fcf8fe14e05c72193bfda1278ad79540e4fcd4..d636176b9e46aa108a6516d60b69a2c763a648b4 100644 (file)
--- a/mupix/Mupix8/sources/FrameGenMux2.vhd
+++ b/mupix/Mupix8/sources/FrameGenMux2.vhd
@@ -203,11 +203,11 @@ begin -- Behavioral
     
 ----------------------------------------------------------------------------------
 -- TRB Slave Bus
--- 0x0100:  start pseudo data generator (writes data to fifo)
--- 0x0101:  number of datawords per block
--- 0x0102:  pause between words
--- 0x0103:  downtime between blocks
--- 0x0105:  select data source (0 for MuPix data, 1 for pseudo data)
+-- 0x0140:  start pseudo data generator (writes data to fifo)
+-- 0x0141:  number of datawords per block
+-- 0x0142:  pause between words
+-- 0x0143:  downtime between blocks
+-- 0x0144:  select data source (0 for MuPix data, 1 for pseudo data)
 ----------------------------------------------------------------------------------
 
 SLV_BUS_HANDLER: process (clk)
@@ -221,16 +221,16 @@ SLV_BUS_HANDLER: process (clk)
             
             if SLV_READ_IN = '1' then
                 case SLV_ADDR_IN is
-                    when x"0101" =>
+                    when x"0141" =>
                         SLV_DATA_OUT <= gen_num;
                         SLV_ACK_OUT  <= '1';
-                    when x"0102" =>
+                    when x"0142" =>
                         SLV_DATA_OUT <= gen_pause;
                         SLV_ACK_OUT  <= '1';
-                    when x"0103" =>
+                    when x"0143" =>
                         SLV_DATA_OUT <= gen_down;
                         SLV_ACK_OUT  <= '1';
-                    when x"0105" =>
+                    when x"0144" =>
                         SLV_DATA_OUT(0) <= mux_sel;
                         SLV_ACK_OUT     <= '1';
                     when others =>
@@ -239,19 +239,19 @@ SLV_BUS_HANDLER: process (clk)
                 
             elsif SLV_WRITE_IN = '1' then
                 case SLV_ADDR_IN is
-                    when x"0100" =>
+                    when x"0140" =>
                         gen_start   <= SLV_DATA_IN(0);
                         SLV_ACK_OUT <= '1';
-                    when x"0101" =>
+                    when x"0141" =>
                         gen_num     <= SLV_DATA_IN;
                         SLV_ACK_OUT <= '1';
-                    when x"0102" =>
+                    when x"0142" =>
                         gen_pause   <= SLV_DATA_IN;
                         SLV_ACK_OUT <= '1';
-                    when x"0103" =>
+                    when x"0143" =>
                         gen_down    <= SLV_DATA_IN;
                         SLV_ACK_OUT <= '1';
-                    when x"0105" =>
+                    when x"0144" =>
                         mux_sel     <= SLV_DATA_IN(0);
                         SLV_ACK_OUT <= '1';
                     when others =>

diff --git a/mupix/Mupix8/sources/MupixBoard.vhd b/mupix/Mupix8/sources/MupixBoard.vhd
index 6bce0c7679a339f9002e52a4936d1bc12c0f5ae4..bc27cd4e024a7df74372386acd7e7eaca4409cf4 100644 (file)
--- a/mupix/Mupix8/sources/MupixBoard.vhd
+++ b/mupix/Mupix8/sources/MupixBoard.vhd
@@ -43,11 +43,6 @@ entity MupixBoard8 is
     fifo_empty         : in std_logic_vector(3 downto 0); -- mupix data FIFO empty flags
     fifo_full          : in std_logic_vector(3 downto 0); -- mupix data FIFO full flags
     fifo_data          : in std_logic_vector(127 downto 0); -- mupix readout data from FIFOs
-
-    --hit generator / source selector outputs
-    -- mux_data_out    : out std_logic_vector(127 downto 0);
-    -- mux_fifo_full   : out std_logic_vector(3 downto 0);
-    -- mux_fifo_empty  : out std_logic_vector(3 downto 0);
     
     --resets
     timestampreset_in    : in std_logic;  --time stamp reset