implement trigger delay

diff --git a/ADC/source/adc_processor_cfd.vhd b/ADC/source/adc_processor_cfd.vhd
index 520a1dd7122f249e8d9a79098822b4199e505868..e7b3db65c305d90facab190fd6c649efd9731cd4 100644 (file)
--- a/ADC/source/adc_processor_cfd.vhd
+++ b/ADC/source/adc_processor_cfd.vhd
@@ -55,7 +55,7 @@ architecture arch of adc_processor_cfd is
   signal ram_counter : ram_counter_t := (others => (others => '0')); 
   --signal ram_we_adc : std_logic_vector(CHANNELS - 1 downto 0) := (others => '0');
 
-  type state_t is (IDLE, DO_RELEASE, RELEASE_DIRECT, WAIT_FOR_END, CHECK_STATUS_TRIGGER, SEND_STATUS, READOUT, WAIT_BSY, WAIT_RAM);
+  type state_t is (IDLE, DO_RELEASE, RELEASE_DIRECT, WAIT_FOR_END, CHECK_STATUS_TRIGGER, SEND_STATUS, READOUT, WAIT_BSY, WAIT_RAM, TRIG_DLY);
   signal state     : state_t;
   signal statebits : std_logic_vector(7 downto 0);
 
@@ -68,10 +68,11 @@ architecture arch of adc_processor_cfd is
   type epoch_counter_t is array(CHANNELS - 1 downto 0) of unsigned(23 downto 0);
   signal epoch_counter : epoch_counter_t;
   
-  --signal trigger_delay : unsigned();
+  signal trigger_delay : unsigned(11 downto 0);
 begin
   CONF_adc <= CONFIG when rising_edge(CLK_ADC);
-
+  trigger_delay <= CONFIG.TriggerDelay when rising_edge(CLK_SYS);
+  
   trigger_mask <= CONF_adc.TriggerEnable((DEVICE + 1) * CHANNELS - 1 downto DEVICE * CHANNELS);
   TRIGGER_OUT  <= or_all(trigger_gen and trigger_mask) when rising_edge(CLK_ADC);
 
@@ -116,6 +117,7 @@ begin
 
   proc_readout : process
     variable channelselect : integer range 0 to 3;
+    variable counter : integer range 0 to 2**trigger_delay'length - 1; 
   begin
     wait until rising_edge(CLK_SYS);
     READOUT_TX.busy_release  <= '0';
@@ -134,8 +136,8 @@ begin
           READOUT_TX.statusbits <= (23 => '1', others => '0'); --event not found
           state                 <= RELEASE_DIRECT;
         elsif READOUT_RX.valid_timing_trg = '1' then
-          state <= WAIT_BSY;
-          busy_in_sys(channelselect) <= '1';
+          state <= TRIG_DLY;
+          counter := to_integer(trigger_delay);
         end if;
 
       when RELEASE_DIRECT =>
@@ -162,8 +164,13 @@ begin
           end if;
         end if;
 
-      --when TRIG_DLY =>
-                
+      when TRIG_DLY =>
+        if counter = 0 then
+          busy_in_sys(channelselect) <= '1';
+          state <= WAIT_BSY;
+        else
+          counter := counter - 1;
+        end if;             
 
       when WAIT_BSY =>
         busy_in_sys(channelselect) <= '1';