###################################################################################
#Settings for this project
my $TOPNAME = "panda_dirc_wasa"; #Name of top-level entity
-my $lattice_path = '/d/jspc29/lattice/diamond/2.0';
+my $lattice_path = '/d/jspc29/lattice/diamond/2.01';
my $synplify_path = '/d/jspc29/lattice/synplify/F-2012.03-SP1/';
my $lm_license_file_for_synplify = "27000\@lxcad01.gsi.de";
my $lm_license_file_for_par = "1702\@hadeb05.gsi.de";
wire [7:0] cmd_read;
wire [7:0] cmd_erase;
wire [7:0] cmd_program;
+ wire [7:0] cmd_select_sector;
wire [12:0] real_address;
assign ufm_repeated_read = (cmd == 3'b001) ? 1'b1 : 1'b0 ;
assign ufm_repeated_write = (cmd == 3'b011) ? 1'b1 : 1'b0 ;
-`define CMD_CHECK_BUSY_FLAG 8'hF0
-`define CMD_BYPASS 8'hFF
-`define CMD_ENABLE_INTERFACE 8'h74
-`define CMD_DISABLE_INTERFACE 8'h26
-`define CMD_SET_ADDRESS 8'hB4
-`define CMD_UFM_READ 8'hCA
-`define CMD_UFM_ERASE 8'hCB
-`define CMD_UFM_PROGRAM 8'hC9
-`define CMD_CFG_READ 8'h73
-`define CMD_CFG_ERASE 8'h0E
-`define CMD_CFG_PROGRAM 8'h70
-
- assign cmd_read = ((ufm_page >= 13'b1110000000000)? CMD_UFM_READ : CMD_CFG_READ ;
- assign cmd_erase = ((ufm_page >= 13'b1110000000000)? CMD_UFM_ERASE : CMD_CFG_ERASE ;
- assign cmd_program = ((ufm_page >= 13'b1110000000000)? CMD_UFM_PROGRAM : CMD_CFG_PROGRAM ;
- assign real_address= ((ufm_page >= 13'b1110000000000)? (ufm_page xor 13'b1110000000000) : ufm_page ;
+ assign cmd_read = (ufm_page[12:10] == 3'b111)? `CMD_UFM_READ : `CMD_CFG_READ ;
+ assign cmd_erase = (ufm_page[12:10] == 3'b111)? `CMD_UFM_ERASE : `CMD_CFG_ERASE ;
+ assign cmd_program = (ufm_page[12:10] == 3'b111)? `CMD_UFM_PROGRAM : `CMD_CFG_PROGRAM ;
+ assign real_address= (ufm_page[12:10] == 3'b111)? {3'b000,ufm_page[9:0]} : ufm_page ;
+ assign cmd_select_sector = (ufm_page[12:10] == 3'b111)? 8'h40 : 8'h00 ;
always @ (posedge clk_i or negedge rst_n) // generate clk enable and write enable signals for port A of the DPRAM
n_wb_we_i = `WRITE;
n_efb_flag = 1'b1 ;
n_wb_adr_i = `CFGTXDR;
- n_wb_dat_i = CMD_ENABLE_INTERFACE;
+ n_wb_dat_i = `CMD_ENABLE_INTERFACE;
n_wb_stb_i = `HIGH ;
end
end
n_wb_we_i = `WRITE;
n_efb_flag = 1'b1 ;
n_wb_adr_i = `CFGTXDR;
- n_wb_dat_i = 8'h00;
+ n_wb_dat_i = 8'h04; //JM added for 0xE to erase CFG Flash
n_wb_stb_i = `HIGH ;
end
end
n_wb_we_i = `WRITE;
n_efb_flag = 1'b1 ;
n_wb_adr_i = `CFGTXDR;
- n_wb_dat_i = CMD_DISABLE_INTERFACE;
+ n_wb_dat_i = `CMD_DISABLE_INTERFACE;
n_wb_stb_i = `HIGH ;
end
end
n_wb_we_i = `WRITE;
n_efb_flag = 1'b1 ;
n_wb_adr_i = `CFGTXDR;
- n_wb_dat_i = CMD_BYPASS;
+ n_wb_dat_i = `CMD_BYPASS;
n_wb_stb_i = `HIGH ;
end
end
n_wb_we_i = `WRITE;
n_efb_flag = 1'b1 ;
n_wb_adr_i = `CFGTXDR;
- n_wb_dat_i = CMD_BYPASS;
+ n_wb_dat_i = `CMD_BYPASS;
n_wb_stb_i = `HIGH ;
end
end
else begin
n_wb_we_i = `WRITE;
n_wb_adr_i = `CFGTXDR;
- n_wb_dat_i = CMD_BYPASS;
+ n_wb_dat_i = `CMD_BYPASS;
n_efb_flag = 1'b1 ;
n_wb_stb_i = `HIGH ;
end
n_wb_we_i = `WRITE;
n_efb_flag = 1'b1 ;
n_wb_adr_i = `CFGTXDR;
- n_wb_dat_i = CMD_BYPASS;
+ n_wb_dat_i = `CMD_BYPASS;
n_wb_stb_i = `HIGH ;
end
end
n_efb_flag = `HIGH ;
n_wb_we_i = `WRITE;
n_wb_adr_i = `CFGTXDR;
- n_wb_dat_i = CMD_SET_ADDRESS;
+ n_wb_dat_i = `CMD_SET_ADDRESS;
n_wb_stb_i = `HIGH ;
end
end
n_efb_flag = `HIGH ;
n_wb_we_i = `WRITE;
n_wb_adr_i = `CFGTXDR;
- n_wb_dat_i = 8'h40;
+ n_wb_dat_i = cmd_select_sector;
n_wb_stb_i = `HIGH ;
end
end
n_efb_flag = `HIGH ;
n_wb_we_i = `WRITE;
n_wb_adr_i = `CFGTXDR;
- n_wb_dat_i = {5'b000,real_address[12:8]};
+ n_wb_dat_i = {3'b000,real_address[12:8]};
n_wb_stb_i = `HIGH ;
end
end
* *\r
***********************************************************************/ \r
\r
+`define CMD_CHECK_BUSY_FLAG 8'hF0\r
+`define CMD_BYPASS 8'hFF\r
+`define CMD_ENABLE_INTERFACE 8'h74\r
+`define CMD_DISABLE_INTERFACE 8'h26\r
+`define CMD_SET_ADDRESS 8'hB4\r
\r
+`define CMD_UFM_READ 8'hCA\r
+`define CMD_UFM_ERASE 8'hCB\r
+`define CMD_UFM_PROGRAM 8'hC9\r
+\r
+`define CMD_CFG_READ 8'h73\r
+`define CMD_CFG_ERASE 8'h0E\r
+`define CMD_CFG_PROGRAM 8'h70\r
+ \r
+ \r
+ \r
`define state0 7'd00 \r
`define state1 7'd01 \r
`define state2 7'd02 \r
#project files
add_file -vhdl -lib work "/d/jspc29/lattice/diamond/1.4.2.105/cae_library/synthesis/vhdl/machxo2.vhd"
-add_file -vhdl -lib work "/d/jspc22/trb/cvs/trbnet/trb_net_std.vhd"
-add_file -vhdl -lib work "/d/jspc22/trb/cvs/trb3/base/trb3_components.vhd"
-add_file -vhdl -lib work "/d/jspc22/trb/cvs/trbnet/trb_net_components.vhd"
-add_file -vhdl -lib work "/d/jspc22/trb/cvs/trb3/wasa/source/spi_slave.vhd"
-add_file -vhdl -lib work "/d/jspc22/trb/cvs/trbnet/trb_net_onewire.vhd"
-add_file -vhdl -lib work "/d/jspc22/trb/cvs/trb3/wasa/version.vhd"
-add_file -vhdl -lib work "/d/jspc22/trb/cvs/trb3/wasa/source/pwm.vhd"
+add_file -vhdl -lib work "../..//trbnet/trb_net_std.vhd"
+add_file -vhdl -lib work "../base/trb3_components.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd"
+add_file -vhdl -lib work "source/spi_slave.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_onewire.vhd"
+add_file -vhdl -lib work "version.vhd"
+add_file -vhdl -lib work "source/pwm.vhd"
-add_file -vhdl -lib work "/d/jspc22/trb/cvs/trb3/wasa/cores/oddr16.vhd"
-add_file -vhdl -lib work "/d/jspc22/trb/cvs/trb3/wasa/cores/flash.vhd"
-add_file -vhdl -lib work "/d/jspc22/trb/cvs/trb3/wasa/cores/flashram.vhd"
-add_file -vhdl -lib work "/d/jspc22/trb/cvs/trb3/wasa/cores/pll.vhd"
-add_file -verilog -lib work "/d/jspc22/trb/cvs/trb3/wasa/cores/UFM_WB.v"
-add_file -verilog -lib work "/d/jspc22/trb/cvs/trb3/wasa/cores/efb_define_def.v"
+add_file -vhdl -lib work "cores/oddr16.vhd"
+add_file -vhdl -lib work "cores/flash.vhd"
+add_file -vhdl -lib work "cores/flashram.vhd"
+add_file -vhdl -lib work "cores/pll.vhd"
+add_file -verilog -lib work "cores/efb_define_def.v"
+add_file -verilog -lib work "cores/UFM_WB.v"
-add_file -vhdl -lib work "/d/jspc22/trb/cvs/trb3/wasa/panda_dirc_wasa.vhd"
+add_file -vhdl -lib work "panda_dirc_wasa.vhd"
#implementation: "panda_dirc_wasa"
signal ram_fsm_addr_i : std_logic_vector(3 downto 0);
signal ram_fsm_write_i: std_logic;
+signal enable_cfg_flash : std_logic;
+
begin
wait until rising_edge(clk_i);
if(spi_write_i(5) = '1' and spi_channel_i(7 downto 4) = x"0") then
flash_command <= spi_data_i(15 downto 13);
- flash_page <= spi_data_i(12 downto 0);
+ if(enable_cfg_flash = '1') then
+ flash_page <= spi_data_i(12 downto 0);
+ else
+ flash_page <= "111" & spi_data_i(9 downto 0);
+ end if;
flash_go_tmp(0)<= '1';
else
flash_go_tmp(5 downto 0) <= flash_go_tmp(4 downto 0) & '0';
end if;
end process;
- flash_go <= or_all(flash_go_tmp);
+PROC_CTRL_FLASH_ENABLE : process begin
+ wait until rising_edge(clk_i);
+ if(spi_write_i(5) = '1' and spi_channel_i(7 downto 4) = x"C") then
+ enable_cfg_flash <= spi_data_i(0);
+ end if;
+end process;
+
+flash_go <= or_all(flash_go_tmp);
+
THE_FLASH_RAM : flashram
port map(
jspc29 / trb3.git / commitdiff