--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+
+entity parser is
+ port(
+ CLK : in std_logic;
+ RESET : in std_logic;
+ --
+ PHY_D_IN : in std_logic_vector(7 downto 0);
+ PHY_K_IN : in std_logic;
+ --\r
+ UNKNOWN_OUT : out std_logic;
+ IDLE_OUT : out std_logic;
+ CFG_OUT : out std_logic
+ );
+end entity parser;
+
+architecture parser_arch of parser is
+
+-- state machine signals
+ type state_t is (ST0, ST1, IDLE0, IDLE1, CFG0, CFG1, CFG2, CFG3, UK0, UK1);
+ signal STATE, NEXT_STATE : state_t;
+
+-- Signals\r
+ signal phy_d_q : std_logic_vector(7 downto 0);
+ signal phy_d_qq : std_logic_vector(7 downto 0);
+ signal phy_k_q : std_logic;
+ signal phy_k_qq : std_logic;
+\r
+ signal idle_x : std_logic;\r
+ signal cfg_x : std_logic;\r
+ signal unknown_x : std_logic;\r
+
+begin
+\r
+ THE_SYNC_PROC: process( CLK )\r
+ begin\r
+ if( rising_edge(CLK) ) then\r
+ phy_d_qq <= phy_d_q;\r
+ phy_d_q <= PHY_D_IN;\r
+ phy_k_qq <= phy_k_q;
+ phy_k_q <= PHY_K_IN;
+ end if;\r
+ end process THE_SYNC_PROC;\r
+
+ -----------------------------------------------------------
+ -- statemachine: clocked process
+ -----------------------------------------------------------
+ THE_FSM: process( CLK )
+ begin
+ if( rising_edge(CLK) ) then
+ if( RESET = '1' ) then
+ STATE <= ST0;
+ else
+ STATE <= NEXT_STATE;
+ end if;
+ end if;
+ end process THE_FSM;
+\r
+ THE_STATE_TRANSITIONS: process( STATE, phy_d_qq, phy_d_q, phy_k_qq, phy_k_q )
+ begin
+ idle_x <= '0';\r
+ cfg_x <= '0';\r
+ unknown_x <= '0';\r
+
+ case STATE is
+\r
+ when ST0 =>\r
+ if ( (phy_d_qq = x"bc") and (phy_k_qq = '1') and (phy_d_q = x"50") and (phy_k_q = '0') ) then\r
+ NEXT_STATE <= IDLE0;\r
+ elsif( (phy_d_qq = x"bc") and (phy_k_qq = '1') and (phy_d_q = x"b5") and (phy_k_q = '0') ) then\r
+ NEXT_STATE <= CFG0;
+ elsif( (phy_d_qq = x"bc") and (phy_k_qq = '1') and (phy_d_q = x"42") and (phy_k_q = '0') ) then\r
+ NEXT_STATE <= CFG0;
+ else\r
+ NEXT_STATE <= ST1;\r
+ end if;\r
+\r
+ when ST1 =>
+ if ( (phy_d_qq = x"bc") and (phy_k_qq = '1') and (phy_d_q = x"50") and (phy_k_q = '0') ) then
+ NEXT_STATE <= IDLE0;
+ elsif( (phy_d_qq = x"bc") and (phy_k_qq = '1') and (phy_d_q = x"b5") and (phy_k_q = '0') ) then
+ NEXT_STATE <= CFG0;
+ elsif( (phy_d_qq = x"bc") and (phy_k_qq = '1') and (phy_d_q = x"42") and (phy_k_q = '0') ) then
+ NEXT_STATE <= CFG0;
+ else
+ NEXT_STATE <= ST0;
+ end if;
+\r
+ when IDLE0 =>\r
+ idle_x <= '1';\r
+ NEXT_STATE <= IDLE1;\r
+\r
+ when IDLE1 =>\r
+ idle_x <= '1';
+ if ( (phy_d_qq = x"bc") and (phy_k_qq = '1') and (phy_d_q = x"50") and (phy_k_q = '0') ) then
+ NEXT_STATE <= IDLE0;
+ elsif( (phy_d_qq = x"bc") and (phy_k_qq = '1') and (phy_d_q = x"b5") and (phy_k_q = '0') ) then
+ NEXT_STATE <= CFG0;
+ elsif( (phy_d_qq = x"bc") and (phy_k_qq = '1') and (phy_d_q = x"42") and (phy_k_q = '0') ) then
+ NEXT_STATE <= CFG0;
+ else
+ NEXT_STATE <= UK0;
+ end if;
+\r
+ when CFG0 =>\r
+ cfg_x <= '1';\r
+ NEXT_STATE <= CFG1;\r
+\r
+ when CFG1 =>\r
+ cfg_x <= '1';
+ NEXT_STATE <= CFG2;
+\r
+ when CFG2 =>\r
+ cfg_x <= '1';
+ NEXT_STATE <= CFG3;
+\r
+ when CFG3 =>\r
+ cfg_x <= '1';
+ if ( (phy_d_qq = x"bc") and (phy_k_qq = '1') and (phy_d_q = x"50") and (phy_k_q = '0') ) then
+ NEXT_STATE <= IDLE0;
+ elsif( (phy_d_qq = x"bc") and (phy_k_qq = '1') and (phy_d_q = x"b5") and (phy_k_q = '0') ) then
+ NEXT_STATE <= CFG0;
+ elsif( (phy_d_qq = x"bc") and (phy_k_qq = '1') and (phy_d_q = x"42") and (phy_k_q = '0') ) then
+ NEXT_STATE <= CFG0;
+ else
+ NEXT_STATE <= UK0;
+ end if;
+\r
+ when UK0 =>\r
+ unknown_x <= '1';\r
+ NEXT_STATE <= UK1;\r
+\r
+ when UK1 =>
+ unknown_x <= '1';
+ if ( (phy_d_qq = x"bc") and (phy_k_qq = '1') and (phy_d_q = x"50") and (phy_k_q = '0') ) then
+ NEXT_STATE <= IDLE0;
+ elsif( (phy_d_qq = x"bc") and (phy_k_qq = '1') and (phy_d_q = x"b5") and (phy_k_q = '0') ) then
+ NEXT_STATE <= CFG0;
+ elsif( (phy_d_qq = x"bc") and (phy_k_qq = '1') and (phy_d_q = x"42") and (phy_k_q = '0') ) then
+ NEXT_STATE <= CFG0;
+ else
+ NEXT_STATE <= UK0;
+ end if;
+\r
+ when others =>
+ NEXT_STATE <= ST0;
+\r
+ end case;\r
+\r
+ end process THE_STATE_TRANSITIONS;\r
+\r
+ IDLE_OUT <= idle_x when rising_edge(CLK);\r
+ CFG_OUT <= cfg_x when rising_edge(CLK);\r
+ UNKNOWN_OUT <= unknown_x when rising_edge(CLK);\r
+
+end architecture;
DLM_CLK_OUT : out std_logic_vector(3 downto 0);
-- Debug
STATUS_OUT : out std_logic_vector(4 * 8 - 1 downto 0);
- DEBUG_OUT : out std_logic_vector(63 downto 0)
+ DEBUG_OUT : out std_logic_vector(127 downto 0)
);
end entity gbe_med_fifo;
signal led_activity_x : std_logic_vector(3 downto 0);
signal led_activity : std_logic_vector(4 * 2 - 1 downto 0);
+ signal unknown_tx_int : std_logic_vector(3 downto 0);
+ signal idle_tx_int : std_logic_vector(3 downto 0);
+ signal cfg_tx_int : std_logic_vector(3 downto 0);
+
+ signal unknown_rx_int : std_logic_vector(3 downto 0);
+ signal idle_rx_int : std_logic_vector(3 downto 0);
+ signal cfg_rx_int : std_logic_vector(3 downto 0);
+
-- attribute HGROUP : string;
-- attribute BBOX : string;
-- attribute HGROUP of gbe_med_fifo_arch : architecture is "gbe_med_fifo_group";
CHANNEL_GEN : for i in 0 to 3 generate
CHANNEL_ACTIVE_GEN : if LINKS_ACTIVE(i) = '1' generate
+
+ THE_TX_PARSER: entity parser
+ port map(
+ CLK => CLK_125,
+ RESET => CLEAR,
+ --
+ PHY_D_IN => sd_tx_data_dst((i + 1) * 8 - 1 downto i * 8),
+ PHY_K_IN => sd_tx_kcntl_dst(i),
+ --
+ UNKNOWN_OUT => unknown_tx_int(i),
+ IDLE_OUT => idle_tx_int(i),
+ CFG_OUT => cfg_tx_int(i)
+ );
+
+ THE_RX_PARSER: entity parser
+ port map(
+ CLK => sd_rx_clk(i),
+ RESET => CLEAR,
+ --
+ PHY_D_IN => sd_rx_data_src((i + 1) * 8 - 1 downto i * 8),
+ PHY_K_IN => sd_rx_kcntl_src(i),
+ --
+ UNKNOWN_OUT => unknown_rx_int(i),
+ IDLE_OUT => idle_rx_int(i),
+ CFG_OUT => cfg_rx_int(i)
+ );
+
+ -- Debug signals, MSB to LSB
+ DEBUG_OUT((i + 1) * 32 - 1) <= '0';
+ DEBUG_OUT((i + 1) * 32 - 2) <= '0';
+ DEBUG_OUT((i + 1) * 32 - 3) <= '0';
+ DEBUG_OUT((i + 1) * 32 - 4) <= '0';
+ DEBUG_OUT((i + 1) * 32 - 5) <= '0';
+ DEBUG_OUT((i + 1) * 32 - 6) <= '0';
+ DEBUG_OUT((i + 1) * 32 - 7) <= '0';
+ DEBUG_OUT((i + 1) * 32 - 8) <= '0';
+ DEBUG_OUT((i + 1) * 32 - 9) <= '0';
+ DEBUG_OUT((i + 1) * 32 - 10) <= '0';
+ DEBUG_OUT((i + 1) * 32 - 11) <= '0';
+ DEBUG_OUT((i + 1) * 32 - 12) <= '0';
+ DEBUG_OUT((i + 1) * 32 - 13) <= mr_restart_an(i);
+ DEBUG_OUT((i + 1) * 32 - 14) <= cfg_rx_int(i);
+ DEBUG_OUT((i + 1) * 32 - 15) <= idle_rx_int(i);
+ DEBUG_OUT((i + 1) * 32 - 16) <= unknown_rx_int(i);
+ DEBUG_OUT((i + 1) * 32 - 17) <= cfg_tx_int(i);
+ DEBUG_OUT((i + 1) * 32 - 18) <= idle_tx_int(i);
+ DEBUG_OUT((i + 1) * 32 - 19) <= unknown_tx_int(i);
+ DEBUG_OUT((i + 1) * 32 - 20) <= TX_LINK_READY_IN;
+ DEBUG_OUT((i + 1) * 32 - 21) <= link_rx_ready(i);
+ DEBUG_OUT((i + 1) * 32 - 22) <= rx_serdes_rst(i);
+ DEBUG_OUT((i + 1) * 32 - 23) <= rx_pcs_rst(i);
+ DEBUG_OUT((i + 1) * 32 - 24) <= sd_rx_disp_error(i);
+ DEBUG_OUT((i + 1) * 32 - 25) <= sd_rx_cv_error(i);
+ DEBUG_OUT((i + 1) * 32 - 26) <= lsm_status(i);
+ DEBUG_OUT((i + 1) * 32 - 27) <= rx_los_low(i);
+ DEBUG_OUT((i + 1) * 32 - 28) <= rx_cdr_lol(i);
+ DEBUG_OUT((i + 1) * 32 - 29) <= TX_PCS_RST_IN;
+ DEBUG_OUT((i + 1) * 32 - 30) <= tx_plol_lol;
+ DEBUG_OUT((i + 1) * 32 - 31) <= RESET;
+ DEBUG_OUT((i + 1) * 32 - 32) <= CLEAR;
powerup_ch(i) <= '1';
SD_TXDIS_OUT(i) <= '0';
DLM_DATA_IN => DLM_DATA_IN((i + 1) * 8 - 1 downto i * 8),
DLM_INJECT_IN => DLM_INJECT_IN(i),
--
- DEBUG_OUT => open --inserter_dbg
+ DEBUG_OUT => open
);
THE_EVE: entity remover
DLM_DATA_OUT => DLM_DATA_OUT((i + 1) * 8 - 1 downto i * 8),
DLM_FOUND_OUT => DLM_FOUND_OUT(i),
--
- DEBUG_OUT => open --remover_dbg
+ DEBUG_OUT => open
);
end generate TRUDY_AND_EVE;
-- SGMII core
SGMII_GBE_PCS : sgmii_gbe_pcs42
port map(
- rst_n => RESET_N,
+ rst_n => CLEAR_N, --RESET_N,
signal_detect => link_rx_ready(i),
gbe_mode => '1',
sgmii_mode => '0',
CHANNEL_INACTIVE_GEN : if LINKS_ACTIVE(i) = '0' generate
+ DEBUG_OUT((i + 1) * 32 - 1 downto i * 32) <= (others => '0');
+
powerup_ch(i) <= '0';
SD_TXDIS_OUT(i) <= '1';
rx_pcs_rst_q(i) <= '1';
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