RST distribution to be included. Reset of Master Ports fixed.

diff --git a/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd b/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd
index b1be58c958171ea4c138dcb55c2d0aa4a2350adf..595da832922de18dd72cf21baa69776d106d021a 100644 (file)
--- a/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd
+++ b/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd
@@ -190,10 +190,10 @@ begin
                     clk_rx_full(1) when ((quad_mode >= 8) and (IS_MODE(1) = c_IS_SLAVE))  else
                     clk_rx_full(2) when ((quad_mode >= 8) and (IS_MODE(2) = c_IS_SLAVE))  else
                     clk_rx_full(3) when ((quad_mode >= 8) and (IS_MODE(3) = c_IS_SLAVE))  else
-                    clk_tx_full(0) when ((quad_mode = 1)  and (IS_MODE(0) = c_IS_MASTER)) else
-                    clk_tx_full(1) when ((quad_mode = 1)  and (IS_MODE(1) = c_IS_MASTER)) else
-                    clk_tx_full(2) when ((quad_mode = 1)  and (IS_MODE(2) = c_IS_MASTER)) else
-                    clk_tx_full(3) when ((quad_mode = 1)  and (IS_MODE(3) = c_IS_MASTER)) else
+--                    clk_tx_full(0) when ((quad_mode = 1)  and (IS_MODE(0) = c_IS_MASTER)) else
+--                    clk_tx_full(1) when ((quad_mode = 1)  and (IS_MODE(1) = c_IS_MASTER)) else
+--                    clk_tx_full(2) when ((quad_mode = 1)  and (IS_MODE(2) = c_IS_MASTER)) else
+--                    clk_tx_full(3) when ((quad_mode = 1)  and (IS_MODE(3) = c_IS_MASTER)) else
                     '0';
 
 -------------------------------------------------      

diff --git a/media_interfaces/sync/med_sync_control_RS.vhd b/media_interfaces/sync/med_sync_control_RS.vhd
index 9dae191e5340a6524e837fef086915e59fb36cd0..e77929a829f4e6183329d85c572e0b0a057fb062 100644 (file)
--- a/media_interfaces/sync/med_sync_control_RS.vhd
+++ b/media_interfaces/sync/med_sync_control_RS.vhd
@@ -105,14 +105,6 @@ architecture med_sync_control_arch of med_sync_control_RS is
 --  attribute syn_preserve : boolean;  
 --  attribute syn_keep of rx_lsm_state         : signal is true;
 --  attribute syn_preserve of rx_lsm_state     : signal is true;
---  attribute syn_keep of link_half_done_i     : signal is true;
---  attribute syn_preserve of link_half_done_i : signal is true;
---  attribute syn_keep of link_full_done_i     : signal is true;
---  attribute syn_preserve of link_full_done_i : signal is true;
---  attribute syn_keep of word_sync_rx_i       : signal is true;
---  attribute syn_preserve of word_sync_rx_i   : signal is true;
---  attribute syn_keep of word_sync_tx_i       : signal is true;
---  attribute syn_preserve of word_sync_tx_i   : signal is true;
 
 begin
 
@@ -147,7 +139,7 @@ begin
       -- outputs
       RX_SERDES_RST_OUT => rx_serdes_rst_i, -- CLK_REF based
       RX_PCS_RST_OUT    => rx_pcs_rst_i, -- CLK_REF based
-      LINK_RX_READY_OUT => link_rx_ready_i, -- CLK_REF based
+      LINK_RX_READY_OUT => link_rx_ready_i, --LINK_RX_READY_OUT, -- CLK_REF based
       STATE_OUT         => rx_fsm_state
     );
 

diff --git a/media_interfaces/sync/rx_control_RS.vhd b/media_interfaces/sync/rx_control_RS.vhd
index de556f83907c339acfd20e4cbd669566b42fcff7..3e192f5c86e127c550321576d2549171a5660531 100644 (file)
--- a/media_interfaces/sync/rx_control_RS.vhd
+++ b/media_interfaces/sync/rx_control_RS.vhd
@@ -210,7 +210,7 @@ begin
 \r
       when FIRST =>\r
         rx_state_bits         <= x"2";\r
-        rx_data(7 downto 0) <= reg_rx_data_in;\r
+        rx_data(7 downto 0)   <= reg_rx_data_in;\r
         sync_k_i              <= '1';\r
         if( reg_rx_k_in = '1' ) then\r
           case reg_rx_data_in is\r
@@ -276,8 +276,8 @@ begin
     end case;\r
   \r
   -- BUG: master ports don't reset correctly\r
---    if( (RESET = '1') or (link_rx_ready_qrx = '0') ) then\r
-    if( (RESET = '1') ) then\r
+    if( (RESET = '1') or (link_rx_ready_qrx = '0') ) then\r
+--    if( (RESET = '1') ) then\r
       rx_state      <= SLEEP;\r
       rx_dlm_word_i <= x"00";\r
       rx_rst_word_i <= x"00";\r

diff --git a/media_interfaces/sync/tx_control_RS.vhd b/media_interfaces/sync/tx_control_RS.vhd
index feaa457fe316675419882db9f7aeb1d4aac0c225..632600b4cf8cb6d5c85a7a73cca0e131d73a7f1b 100644 (file)
--- a/media_interfaces/sync/tx_control_RS.vhd
+++ b/media_interfaces/sync/tx_control_RS.vhd
@@ -131,7 +131,7 @@ begin
 \r
   link_active_qtx <= link_active_int when rising_edge(CLK_TXI);\r
 \r
-  -- if not set, send toggling idles\r
+  -- if set send IDLE1, else IDLE0\r
   send_steady_idle_int <= link_tx_ready_qtx and link_rx_ready_qtx and \r
                             link_half_done_qtx when (IS_MODE = c_IS_MASTER) else\r
                           link_tx_ready_qtx and link_rx_ready_qtx and\r