SCI reader works now

diff --git a/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd b/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd
index 1ca036699d19c8215c2baa436d9bc93ec3687d53..7d97efe773cba8c05920231bae0cc08abc842ae0 100644 (file)
--- a/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd
+++ b/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd
@@ -130,6 +130,7 @@ architecture med_ecp3_sfp_sync_all_RS_arch of med_ecp3_sfp_sync_all_RS is
   signal lb_sel_i           : std_logic_vector(3 downto 0);
   signal lb_start_i         : std_logic;
   signal lb_start_qsys      : std_logic;
+  signal lb_onoff_i         : std_logic;
   
   signal quad_mode          : integer range 0 to 100;
 
@@ -266,7 +267,9 @@ begin
     RESET_B_IN      => '0',
     PULSE_B_OUT     => lb_start_qsys
   );
-         
+    
+  lb_onoff_i <= TX_RST_WORD_IN(0);
+
 -------------------------------------------------
 -- Serdes
 -------------------------------------------------
@@ -674,8 +677,9 @@ end generate;
       WA_POS_OUT  => wa_position_i,
       WA_REQ_IN   => wap_req_all_q(2),
       -- Loopback hack
-      LB_START_IN => '0', --lb_start_qsys,
-      LB_SEL_IN   => (others => '0'), --lb_sel_i,
+      LB_START_IN => lb_start_qsys,
+      LB_SEL_IN   => lb_sel_i,
+      LB_ONOFF_IN => lb_onoff_i,
       --Slowcontrol
       BUS_RX      => BUS_RX,
       BUS_TX      => BUS_TX,

diff --git a/media_interfaces/sync/sci_reader_RS.vhd b/media_interfaces/sync/sci_reader_RS.vhd
index 980da1781f76afb6b0438d342e428b182f2b9046..53dc0f064eb580f8a7d5b206c5fa33c5bb362cf0 100644 (file)
--- a/media_interfaces/sync/sci_reader_RS.vhd
+++ b/media_interfaces/sync/sci_reader_RS.vhd
@@ -26,6 +26,7 @@ entity sci_reader_RS is
     -- Loopback hack
     LB_START_IN      : in  std_logic;
     LB_SEL_IN        : in  std_logic_vector(3 downto 0);
+    LB_ONOFF_IN      : in  std_logic;
     --Slowcontrol
     BUS_RX           : in  CTRLBUS_RX;
     BUS_TX           : out CTRLBUS_TX;    
@@ -37,9 +38,9 @@ end entity;
 
 architecture sci_reader_arch of sci_reader_RS is
 
---type sci_ctrl is (IDLE, SCTRL, SCTRL_WAIT, SCTRL_WAIT2, SCTRL_FINISH, GET_WA, GET_WA_WAIT, GET_WA_WAIT2, GET_WA_FINISH,
---                  W_RL, W_RL_WAIT, W_RL_WAIT2, W_RL_FINISH, W_RLS, W_RLS_WAIT, W_RLS_WAIT2, W_RLS_FINISH);
-type sci_ctrl is (IDLE, SCTRL, SCTRL_WAIT, SCTRL_WAIT2, SCTRL_FINISH, GET_WA, GET_WA_WAIT, GET_WA_WAIT2, GET_WA_FINISH);
+type sci_ctrl is (IDLE, SCTRL, SCTRL_WAIT, SCTRL_WAIT2, SCTRL_FINISH, GET_WA, GET_WA_WAIT, GET_WA_WAIT2, GET_WA_FINISH,
+                  W_RL, W_RL_WAIT, W_RL_WAIT2, W_RL_FINISH, W_RLS, W_RLS_WAIT, W_RLS_WAIT2, W_RLS_FINISH);
+--type sci_ctrl is (IDLE, SCTRL, SCTRL_WAIT, SCTRL_WAIT2, SCTRL_FINISH, GET_WA, GET_WA_WAIT, GET_WA_WAIT2, GET_WA_FINISH);
 
 signal sci_state         : sci_ctrl;
 signal sci_timer         : unsigned(16 downto 0) := (others => '0');
@@ -89,9 +90,17 @@ begin
         elsif( (sci_timer(sci_timer'left) = '1') and (WA_REQ_IN = '1') ) then
           sci_timer     <= (others => '0');
           sci_state     <= GET_WA;
---        elsif( LB_START_IN = '1' ) then
---          sci_state     <= W_RL;
---          next_sci_wr   <= '1';
+      ----------------------------------------
+      ----------------------------------------
+        elsif( LB_START_IN = '1' ) then
+          next_sci_wr   <= '1';
+          if( LB_ONOFF_IN = '1' ) then
+            sci_state     <= W_RL;
+          else
+            sci_state     <= W_RLS;
+          end if;
+      ----------------------------------------
+      ----------------------------------------
         end if;      
       when SCTRL =>
         if( sci_reg_i = '1' ) then
@@ -113,41 +122,59 @@ begin
         BUS_TX.ack      <= '1';
         SCI_RD          <= '0';
         sci_state       <= IDLE;
-
       ----------------------------------------
       ----------------------------------------
---      when W_RL =>
---        SCI_SEL         <= '0' & LB_SEL_IN; 
---        SCI_ADDR        <= b"010001"; -- x"11" for ECP3
---        SCI_WRDATA      <= x"21"; -- set source of TX data
---        SCI_RD          <= '0';
---        sci_state       <= W_RL_WAIT;
---      when W_RL_WAIT =>
---        next_sci_wr     <= '0';
---        sci_state       <= W_RL_WAIT2;
---      when W_RL_WAIT2 =>
---        sci_state       <= W_RL_FINISH;
---      when W_RL_FINISH =>
---        next_sci_wr     <= '1';
---        sci_state       <= W_RLS;
---      when W_RLS =>
---        SCI_ADDR        <= b"010100"; -- x"14" for ECP3
---        SCI_WRDATA      <= x"69"; -- enable feedback
---        SCI_RD          <= '0';
---        sci_state       <= W_RLS_WAIT;
---      when W_RLS_WAIT =>
---        next_sci_wr     <= '0';
---        sci_state       <= W_RLS_WAIT2;
---      when W_RLS_WAIT2 =>
---        sci_state       <= W_RLS_FINISH;
---      when W_RLS_FINISH =>
---        SCI_SEL         <= (others => '0');
---        SCI_ADDR        <= (others => '0');
---        SCI_WRDATA      <= (others => '0');
---        sci_state       <= IDLE;
-      ----------------------------------------
+      when W_RL =>
+        SCI_SEL         <= '0' & LB_SEL_IN; 
+        SCI_ADDR        <= b"010001"; -- x"11" for ECP3
+        if( LB_ONOFF_IN = '1' ) then
+          SCI_WRDATA      <= x"21"; -- source of TX data is feedback
+        else
+          SCI_WRDATA      <= x"11"; -- source of TX data is normal
+        end if;
+        SCI_RD          <= '0';
+        sci_state       <= W_RL_WAIT;
+      when W_RL_WAIT =>
+        next_sci_wr     <= '0';
+        sci_state       <= W_RL_WAIT2;
+      when W_RL_WAIT2 =>
+        sci_state       <= W_RL_FINISH;
+      when W_RL_FINISH =>
+        if( LB_ONOFF_IN = '1' ) then
+          next_sci_wr     <= '1';
+          sci_state       <= W_RLS;
+        else
+          SCI_SEL         <= (others => '0');
+          SCI_ADDR        <= (others => '0');
+          SCI_WRDATA      <= (others => '0');
+          sci_state       <= IDLE;
+        end if;
+      when W_RLS =>
+        SCI_ADDR        <= b"010100"; -- x"14" for ECP3
+        if( LB_ONOFF_IN = '1' ) then
+          SCI_WRDATA      <= x"69"; -- enable feedback
+        else
+          SCI_WRDATA      <= x"09"; -- disable feedback
+        end if;
+        SCI_RD          <= '0';
+        sci_state       <= W_RLS_WAIT;
+      when W_RLS_WAIT =>
+        next_sci_wr     <= '0';
+        sci_state       <= W_RLS_WAIT2;
+      when W_RLS_WAIT2 =>
+        sci_state       <= W_RLS_FINISH;
+      when W_RLS_FINISH =>
+        if( LB_ONOFF_IN = '1' ) then
+          SCI_SEL         <= (others => '0');
+          SCI_ADDR        <= (others => '0');
+          SCI_WRDATA      <= (others => '0');
+          sci_state       <= IDLE;
+        else
+          next_sci_wr     <= '1';
+          sci_state       <= W_RL;
+        end if;
       ----------------------------------------
-      
+      ----------------------------------------      
       when GET_WA =>
         if( ((cnt = 4) and (FPGA_TYPE = 3)) or ((cnt = 2) and (FPGA_TYPE = 5)) ) then
           cnt           := 0;