adjusted padiwa project for the tdc_v2.2

diff --git a/scripts/compile.pl b/scripts/compile.pl
index f0b5452ef7983099eeff196d93b59f5ee7486f70..6ef246676ec771428ea77aaab17a74c7cb4295ae 100755 (executable)
--- a/scripts/compile.pl
+++ b/scripts/compile.pl
@@ -253,7 +253,7 @@ if($par==1 || $all==1){
     system("rm $TOPNAME.ncd");
     if ($isMultiPar)
     {
-       $c=qq|LC_ALL=en_US.UTF-8; par -m ../nodes_lxhadeb07.txt -n $nrNodes -w -i 15 -l 5 -y -s 8 -t 33 -c 1 -e 2 -exp parCDP=1:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=1:parHoldLimit=10000:paruseNBR=1 $tpmap.ncd $TOPNAME.dir $TOPNAME.prf;|;
+       $c=qq|LC_ALL=en_US.UTF-8; par -m ../nodes_lxhadeb07.txt -n $nrNodes -w -i 15 -l 5 -y -s 8 -t 1 -c 1 -e 2 -exp parCDP=1:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=1:parHoldLimit=10000:paruseNBR=1 $tpmap.ncd $TOPNAME.dir $TOPNAME.prf;|;
        execute($c);
 
         # find and copy the .ncd file which has met the timing constraints

diff --git a/wasa/config.vhd b/wasa/config.vhd
index 171c07d2e52a19814dedfa32e799d11e6602caf4..6ee4c214455c90c6cd97c6c7fd35d7399647bb6e 100644 (file)
--- a/wasa/config.vhd
+++ b/wasa/config.vhd
@@ -12,18 +12,24 @@ package config is
 
 --TDC settings
   constant NUM_TDC_MODULES         : integer range 1 to 4  := 1;  -- number of tdc modules to implement
-  constant NUM_TDC_CHANNELS        : integer range 1 to 65 := 65; -- number of tdc channels per module
+  constant NUM_TDC_CHANNELS        : integer range 1 to 65 := 5; -- number of tdc channels per module
   constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6  := 6;  --the nearest power of two, for convenience reasons 
   constant DOUBLE_EDGE_TYPE        : integer range 0 to 3  := 3;  --double edge type:  0, 1, 2,  3
   -- 0: single edge only,
   -- 1: same channel,
   -- 2: alternating channels,
   -- 3: same channel with stretcher
-  constant RING_BUFFER_SIZE        : integer range 0 to 7  := 7;  --ring buffer size:  0, 1, 2,  3,  7   --> change names in constraints file
-                                                                  --ring buffer size: 32,64,96,128,dyn
-
-  constant EVENT_BUFFER_SIZE       : integer range 9 to 13 := 13; -- size of the event buffer, 2**N
-  constant EVENT_MAX_SIZE          : integer := 4096;             --maximum event size. Should not exceed EVENT_BUFFER_SIZE/2
+  constant RING_BUFFER_SIZE        : integer range 0 to 7  := 7;  --change names in constraints file
+                                                                  --ring buffer size:
+                                                                  -- 0->32
+                                                                  -- 1->64
+                                                                  -- 2->96
+                                                                  -- 3->128
+                                                                  -- 5->64dyn
+                                                                  -- 7->128dyn 
+
+  constant EVENT_BUFFER_SIZE       : integer range 9 to 13 := 11; -- size of the event buffer, 2**N
+  constant EVENT_MAX_SIZE          : integer := 1024;             --maximum event size. Should not exceed EVENT_BUFFER_SIZE/2
 
 --Use only every second input channel (mask slow channels from padiwa amps)
   constant USE_PADIWA_FAST_ONLY : integer := c_NO;
@@ -34,7 +40,7 @@ package config is
 --Add logic to generate configurable trigger signal from input signals.
   constant INCLUDE_TRIGGER_LOGIC : integer := c_YES;
   constant INCLUDE_STATISTICS    : integer := c_YES;  --Do histos of all inputs
-  constant PHYSICAL_INPUTS       : integer := 32;  --number of inputs connected
+  constant PHYSICAL_INPUTS       : integer := 16;  --number of inputs connected
   constant USE_SINGLE_FIFO       : integer := c_YES;  -- single fifo for statistics
 
 --Run wih 125 MHz instead of 100 MHz, use received clock from serdes or external clock input

diff --git a/wasa/tdc_release b/wasa/tdc_release
index 776b99812740678d34f6a2da42a025f182dceb85..df11eae721febf0bfb54aa9ee69e9c6e2bad511e 120000 (symlink)
--- a/wasa/tdc_release
+++ b/wasa/tdc_release
@@ -1 +1 @@
-../../tdc/releases/tdc_v2.1.3
\ No newline at end of file
+../../tdc/releases/tdc_v2.2
\ No newline at end of file

diff --git a/wasa/trb3_periph_padiwa.prj b/wasa/trb3_periph_padiwa.prj
index 0f0d6578cf70f5b9a06cff4002b81f0a2a13bb0f..f1216d669fc10d77d1265d41ec62462ec76af14e 100644 (file)
--- a/wasa/trb3_periph_padiwa.prj
+++ b/wasa/trb3_periph_padiwa.prj
@@ -70,6 +70,7 @@ add_file -vhdl -lib work "../../trbnet/trb_net_sbuf6.vhd"
 add_file -vhdl -lib work "../../trbnet/trb_net16_sbuf.vhd"
 add_file -vhdl -lib work "../../trbnet/trb_net16_regIO.vhd"
 add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler_record.vhd"
 add_file -vhdl -lib work "../../trbnet/trb_net_priority_encoder.vhd"
 add_file -vhdl -lib work "../../trbnet/trb_net_dummy_fifo.vhd"
 add_file -vhdl -lib work "../../trbnet/trb_net16_dummy_fifo.vhd"
@@ -148,29 +149,36 @@ add_file -vhdl -lib work "../base/code/sedcheck.vhd"
 #add_file -vhdl -lib work "tdc_release/Adder_304.vhd"
 add_file -vhdl -lib work "tdc_release/tdc_components.vhd"
 add_file -vhdl -lib work "tdc_release/bit_sync.vhd"
-add_file -vhdl -lib work "tdc_release/BusHandler.vhd"
+#add_file -vhdl -lib work "tdc_release/BusHandler.vhd"
+add_file -vhdl -lib work "tdc_release/BusHandler_record.vhd"
 add_file -vhdl -lib work "tdc_release/Channel_200.vhd"
+#add_file -vhdl -lib work "tdc_release/Channel_fast.vhd"
 add_file -vhdl -lib work "tdc_release/Channel.vhd"
-add_file -vhdl -lib work "tdc_release/Encoder_304_Bit.vhd"
+add_file -vhdl -lib work "tdc_release/Encoder_288_Bit.vhd"
+#add_file -vhdl -lib work "tdc_release/Encoder_304_Bit.vhd"
 add_file -vhdl -lib work "tdc_release/fallingEdgeDetect.vhd"
 add_file -vhdl -lib work "tdc_release/hit_mux.vhd"
 add_file -vhdl -lib work "tdc_release/LogicAnalyser.vhd"
-add_file -vhdl -lib work "tdc_release/Readout.vhd"
+#add_file -vhdl -lib work "tdc_release/Readout.vhd"
+add_file -vhdl -lib work "tdc_release/Readout_record.vhd"
 add_file -vhdl -lib work "tdc_release/risingEdgeDetect.vhd"
 add_file -vhdl -lib work "tdc_release/ROM_encoder_ecp3.vhd"
 add_file -vhdl -lib work "tdc_release/ShiftRegisterSISO.vhd"
 add_file -vhdl -lib work "tdc_release/Stretcher_A.vhd"
 add_file -vhdl -lib work "tdc_release/Stretcher_B.vhd"
 add_file -vhdl -lib work "tdc_release/Stretcher.vhd"
-add_file -vhdl -lib work "tdc_release/TDC.vhd"
+#add_file -vhdl -lib work "tdc_release/TDC.vhd"
+add_file -vhdl -lib work "tdc_release/TDC_record.vhd"
 add_file -vhdl -lib work "tdc_release/TriggerHandler.vhd"
 add_file -vhdl -lib work "tdc_release/up_counter.vhd"
 
 add_file -vhdl -lib work "../../tdc/base/cores/ecp3/PLL/pll_in125_out33.vhd"
 add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_DC_36x128_DynThr_OutReg.vhd"
 add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_DC_36x128_OutReg.vhd"
+add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_DC_36x64_DynThr_OutReg.vhd"
 add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_DC_36x64_OutReg.vhd"
 add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_DC_36x32_OutReg.vhd"
+add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_36x128_DynThr_OutReg.vhd"
 add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_36x128_OutReg.vhd"
 add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_36x64_OutReg.vhd"
 add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_36x32_OutReg.vhd"