Update ADC AddOn design

diff --git a/adcaddon/trb3sc_adc.prj b/adcaddon/trb3sc_adc.prj
index 6138d950bf72c0ce1d683abcb093a83942c145fe..c89cf144d08a2dbd9a9a4bc051e1a930e899f4e2 100644 (file)
--- a/adcaddon/trb3sc_adc.prj
+++ b/adcaddon/trb3sc_adc.prj
@@ -191,4 +191,4 @@ add_file -vhdl -lib "work" "../../trb3/ADC/source/adc_handler.vhd"
 add_file -vhdl -lib "work" "../../trb3/ADC/source/adc_slowcontrol_data_buffer.vhd"
 
 add_file -vhdl -lib "work" "trb3sc_adc.vhd"
-add_file -constraint "trb3sc_adc.sdc"
+#add_file -constraint "trb3sc_adc.sdc"

diff --git a/adcaddon/trb3sc_adc.vhd b/adcaddon/trb3sc_adc.vhd
index a17289f7f30c9b26c9cfde7e8ec6ad1cd86e7d4c..a5e3c1cf8ea0279e4e99fe2c8890e07004dc5507 100644 (file)
--- a/adcaddon/trb3sc_adc.vhd
+++ b/adcaddon/trb3sc_adc.vhd
@@ -338,6 +338,9 @@ THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record
 ---------------------------------------------------------------------------
 gen_reallogic : if USE_DUMMY_READOUT = 0 generate
   THE_ADC : entity work.adc_handler
+    generic map(
+      IS_TRB3 = 0
+      )
     port map(
       CLK        => clk_sys,
       CLK_ADCRAW => CLK_CORE_PCLK, --clk_full_osc,