\section{Breakdown of the data acquisition system}
-\subsection{Overview}
+% \subsection{Overview}
\begin{figure}[H]
\centering
\item[Computer]
Common PC running Linux and custom control, monitoring, and data acquisition software.
\end{description}
-
\subsection{The sensors}
The MIMOSA26 sensors are Monolithic Active Pixel Sensors (MAPS). In contrast to CCD sensors
MAPS can be produced in a standard CMOS process and have an amplifying transistor in each
MIMOSA26 has two synchronous serial data output ports, which operate at a frequency of
\SI{80}{\mega\hertz}.
-The data output possesses an additional signal, MKD, which signals the beginning of a readout frame.
+The data output possesses an additional signal, MKD, which marks the beginning of a readout frame.
The sensor's settings are being programmed via a JTAG interface (LVTTL) which provides the
possibility to queue multiple sensors to a JTAG chain.
\label{fig:m26lines}
\end{figure}
-\subsection{The front-end electronics (draft!)}
-\label{sec:front-end_electronics}
-\subsubsection{The front-end board(draft!)}
+\subsection{Front-end electronics(1): The front-end board}
\label{sec:front-end_board}
-The front-end board serves mainly as an adaptor between the sensor FPC, to which the MIMOSA26 chip is
-bonded, and the converter board. The front-end board possesses decoupling capacitors to filter off
+The front-end board is the PCB deployed closest to the sensors.
+It serves mainly as an adaptor between the sensor FPC (to which the MIMOSA26 chips are
+bonded) and the \hyperref[sec:converter_board]{converter board}. The front-end board possesses decoupling capacitors to filter off
fluctuations in the supply voltages. It also provides some circuitry to generate the clamping voltage
-for the sensor or buffer a clamping voltage generated on the
-\hyperref[sec:converter_board]{converter board}.
-\subsubsection{The converter board(draft!)}
+for the sensor or buffer a clamping voltage generated on the converter board.
+\subsection{Front-end electronics(2): The converter board}
\label{sec:converter_board}
The converter board is the main front-end electronics component.
It is intended to electrically accommodate up to two sensors and it provides a means to monitor the
sensor's electrical behaviour.
The converter board consists of the following circuits:
-\begin{description}
-\item[Power supplies]
+% \begin{description}
+\subsubsection{Power supplies}
\label{sec:Power_supplies}
% \paragraph{Power supplies}
For each of the two sensors, the converter board provides a power supply for the analog supply voltage
\item[DisD1]
Short/discharge output of digital power supply for sensor 1
\end{description}
-\item[ADC]
+\subsubsection{ADC}
\label{sec:ADC}
-% \paragraph{ADC}
+
+
+
+
The converter board possesses two 16 bit ADCs and adjacent amplifier and multiplexer circuits
to monitor the following observables for each of the two sensors:
\begin{description}
The voltage drop on a forward biased diode on the silicon bulk of the MIMOSA26 chip. The voltage shows
a negative temperature dependence (the lower the voltage drop, the warmer the chip).
\item[VDiscRef2A-VDiscRef2D]
+\begin{figure}[H]
+\centering
+\includegraphics[width=1\textwidth]{dacmatrix.pdf}
+\caption{Simplified schema of the discriminator threshold DACs and their respective
+test outputs inside MIMOSA26}
+\label{fig:dacmatrix}
+\end{figure}
The voltages on the VDISCREF2 outputs of the sensor. These are test outputs to review the baseline
voltages of the discriminator circuit, which are set via a JTAG controllable
DAC\footnote{JTAG register "DAC\_BIAS", field "IVDREF2"}.
There are four individual test outputs, since the
baseline voltage is actively buffered for each quarter of the sensor and each buffer introduces
-a different voltage offset.
-The DAC range is \SIrange{0}{2.7}{\volt} according to the datasheet.
+a different voltage offset (see figure \ref{fig:dacmatrix}).
+The DAC range is \SIrange{1}{1.5}{\volt} according to the datasheet\cite{m26_manual}
+but was actually measured to be \SIrange{0}{2.7}{\volt} in the lab.
\item[VDiscRefA-VDiscRefD]
The voltages on the discriminator reference voltage outputs, measured relative to their respective
baseline. The readings of these channels directly show the discriminator threshold voltages
that are generated by four individual
DACs\footnote{JTAG register "DAC\_BIAS", fields "IVDREF1A-IVDREF1D"}
inside the chip. The DAC range is \SIrange{-32}{32}{\milli\volt} according to the datasheet.
-For these input channels the converter board has a measuring range from \SIrange{-39.9}{39.9}{\volt}.
+For these input channels the converter board has a measuring input range from
+\SIrange{-39.9}{39.9}{\volt}.
\item[ZeroSingle]
Calibration offset that has to be subtracted from VDiscRef2A-VDiscRef2D to reduce systematic
uncertainty introduced by the multiplexer and amplifier circuitry.
Calibration offset that has to be subtracted from VDiscRefA-VDiscRefD to reduce systematic
uncertainty introduced by the multiplexer and amplifier circuitry.
\end{description}
-\item[Latch-up detection circuit]
+\subsubsection{Latch-up detection circuit}
\label{sec:Latch-up_detection_circuit}
+
+
+\begin{figure}[H]
+\centering
+\includegraphics[width=.6\textwidth]{latchup_prot.pdf}
+\caption{Simplified schema of the latch-up detection circuit}
+\label{fig:latch-up_detection}
+\end{figure}
+
+
+
% \paragraph{Latch-up detection circuit}
Each power supply unit has a shunt plus a high side current mirror in order to measure the
voltage drop on the shunt that is proportional to the output current.
This voltage drop is not only measured by the ADC section, but also monitored by an analog comparator.
The comparator also receives a reference voltage from a programmable on-board DAC.
If the output current exceeds a certain threshold, depending on the DAC setting, a fast digital signal
-is generated by the comparator indicating an overcurrent situation.
-\item[Programmable DAC]
+is generated by the comparator indicating an overcurrent situation
+(see figure \ref{fig:latch-up_detection}).
+These signals are forwarded to the FPGA with the
+\hyperref[sec:CbController]{converter board controller} entity.
+The FPGA can then decide whether to disable the power supply or not.
+?? A reaction mechanism is not yet implemented ??
+
+\subsubsection{Programmable DAC}
\label{sec:Programmable_DAC}
% \paragraph{Programmable DAC}
On the converter board there is one programmable eight channel digital to analog converter (DAC).
The clamping voltage outputs of the DAC is only connected to the sensors if the proper jumpers/solder
bridges are closed.
% \paragraph{Signal switches}
-\item[Signal switches]
+\subsubsection{Signal switches}
\label{sec:Signal_switches}
The converter board provides semiconductor switches to enable/disable the sensor control signals
and to enable/bypass JTAG for each sensor.
signal is 0.
\end{description}
% \paragraph{Microcontroller}
-\item[Microcontroller]
+\subsubsection{Microcontroller}
\label{sec:Microcontroller}
The converter board is equipped with an STM32F103RC microcontroller.
Its processor core is an ARM 32-bit Cortex™-M3 CPU which is operated at a clock rate of
the SPI transmission of the gathered data, while the main processor can devote itself to the
acquisition of the next ADC values.
+The microcontroller is a general purpose device and has to be programmed with a custom firmware
+in order to perform the above tasks.
+The firmware is written in C and compiled via a cross compiler. The resulting executable binary
+file is written to the microcontroller's flash memory by using an
+SWD\footnote{Serial wire debug, a serial debug and programming interface developed by ST
+Microeletronics}
+programmer.
-% - general purpose device, custom firmware, written in C
+% - ?? why the microcontroller - to save lines - should I write that?
-\item[Signal buffers and signal converters]
+\subsubsection{Signal buffers and signal converters}
All signals between the converter board and the TRB3 are exchanged via LVDS lines to use the most
stable transmission technique. After all this connection is the longest distance in the set-up
that needs to be bridged by copper cables.
% \item[Flat cable connector]
-\end{description}
+% \end{description}
jspc29 / mvd_docu.git / commitdiff