re-add TRB3 central hub without GbE

diff --git a/trb3_gbe/trb3_central_gbe.vhd b/trb3_gbe/trb3_central_gbe.vhd
index af23a9747a269c635403b1034793fef28da349ea..3e4d3d1707eafa7d3b760100582ef9187c2347be 100644 (file)
--- a/trb3_gbe/trb3_central_gbe.vhd
+++ b/trb3_gbe/trb3_central_gbe.vhd
@@ -264,7 +264,8 @@ THE_RESET_HANDLER : trb_net_reset_handler
     DEBUG_OUT       => open
   );
 
-trb_reset_in <= med_stat_op(4*16+13) or reset_via_gbe_delayed(2);
+trb_reset_in <=    med_stat_op(4*16+13) or reset_via_gbe_delayed(2) when USE_ETHERNET = c_YES 
+              else med_stat_op(4*16+13);
 reset_i <= reset_i_temp;
 
 process begin
@@ -620,6 +621,67 @@ gen_ethernet_hub : if USE_ETHERNET = c_YES generate
 
 end generate;
 
+gen_noethernet_hub : if USE_ETHERNET = c_NO generate
+THE_HUB : trb_net16_hub_base
+  generic map (
+    HUB_USED_CHANNELS => (c_YES,c_YES,c_NO,c_YES),
+    IBUF_SECURE_MODE  => c_YES,
+    MII_NUMBER        => 5,
+    MII_IS_UPLINK       => IS_UPLINK,
+    MII_IS_DOWNLINK     => IS_DOWNLINK,
+    MII_IS_UPLINK_ONLY  => IS_UPLINK_ONLY,
+    INT_NUMBER        => 0,
+    INT_CHANNELS      => (others => 0),
+    USE_ONEWIRE       => c_YES,
+    COMPILE_TIME      => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,32)),
+    HARDWARE_VERSION  => x"90000000",
+    INIT_ENDPOINT_ID  => x"0005",
+    INIT_ADDRESS      => x"F305",
+    BROADCAST_SPECIAL_ADDR => x"40"
+    )
+  port map (
+    CLK    => clk_sys_i,
+    RESET  => reset_i,
+    CLK_EN => '1',
+
+    --Media interfacces
+    MED_DATAREADY_OUT(5*1-1 downto 0)   => med_dataready_out,
+    MED_DATA_OUT(5*16-1 downto 0)       => med_data_out,
+    MED_PACKET_NUM_OUT(5*3-1 downto 0)  => med_packet_num_out,
+    MED_READ_IN(5*1-1 downto 0)         => med_read_in,
+    MED_DATAREADY_IN(5*1-1 downto 0)    => med_dataready_in,
+    MED_DATA_IN(5*16-1 downto 0)        => med_data_in,
+    MED_PACKET_NUM_IN(5*3-1 downto 0)   => med_packet_num_in,
+    MED_READ_OUT(5*1-1 downto 0)        => med_read_out,
+    MED_STAT_OP(5*16-1 downto 0)        => med_stat_op,
+    MED_CTRL_OP(5*16-1 downto 0)        => med_ctrl_op,
+
+    COMMON_STAT_REGS                => common_stat_reg,
+    COMMON_CTRL_REGS                => common_ctrl_reg,
+    MY_ADDRESS_OUT                  => my_address,
+    --REGIO INTERFACE
+    REGIO_ADDR_OUT                  => ctrlbus_rx.addr,
+    REGIO_READ_ENABLE_OUT           => ctrlbus_rx.read,
+    REGIO_WRITE_ENABLE_OUT          => ctrlbus_rx.write,
+    REGIO_DATA_OUT                  => ctrlbus_rx.data,
+    REGIO_DATA_IN                   => ctrlbus_tx.data,
+    REGIO_DATAREADY_IN              => ctrlbus_tx.ack,
+    REGIO_NO_MORE_DATA_IN           => ctrlbus_tx.nack,
+    REGIO_WRITE_ACK_IN              => ctrlbus_tx.ack,
+    REGIO_UNKNOWN_ADDR_IN           => ctrlbus_tx.unknown,
+    REGIO_TIMEOUT_OUT               => ctrlbus_rx.timeout,
+
+    ONEWIRE                         => TEMPSENS,
+    ONEWIRE_MONITOR_OUT             => open,
+    --Status ports (for debugging)
+    MPLEX_CTRL            => (others => '0'),
+    CTRL_DEBUG            => (others => '0'),
+    STAT_DEBUG            => open
+    );
+
+
+
+end generate;
 
 ---------------------------------------------------------------------------
 -- Bus Handler