------------------------------------------------------------------------------
--TDC settings
+ constant FPGA_TYPE : integer := 3; --3: ECP3, 5: ECP5
constant NUM_TDC_MODULES : integer range 1 to 4 := 1; -- number of tdc modules to implement
constant NUM_TDC_CHANNELS : integer range 1 to 65 := 33; -- number of tdc channels per module
- constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 5; --the nearest power of two, for convenience reasons
+ constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 4; --the nearest power of two, for convenience reasons
constant DOUBLE_EDGE_TYPE : integer range 0 to 3 := 1; --double edge type: 0, 1, 2, 3
-- 0: single edge only,
-- 1: same channel,
-- 13: Debug - single fine time and the chain for the 0x3ff hits
-- 14: Debug - single fine time and the ROM addresses for the two transitions
-- 15: Debug - complete carry chain dump
-
+ constant USE_PINOUT : integer := 1; --1: normal, 3: every 4th channel (HPTDC)
+
+
constant EVENT_BUFFER_SIZE : integer range 9 to 13 := 13; -- size of the event buffer, 2**N
constant EVENT_MAX_SIZE : integer := 4096; --maximum event size. Should not exceed EVENT_BUFFER_SIZE/2
--Add logic to generate configurable trigger signal from input signals.
constant INCLUDE_TRIGGER_LOGIC : integer := c_YES;
- constant INCLUDE_STATISTICS : integer := c_NO; --Do histos of all inputs
+ constant INCLUDE_STATISTICS : integer := c_YES; --Do histos of all inputs
constant PHYSICAL_INPUTS : integer := 32; --number of inputs connected
constant TRIG_GEN_OUTPUT_NUM : integer := 4;
constant MONITOR_INPUT_NUM : integer := PHYSICAL_INPUTS+TRIG_GEN_OUTPUT_NUM;
begin
t := (others => '0');
t(63 downto 56) := std_logic_vector(to_unsigned(2,8)); --table version 2
- t(7 downto 0) := std_logic_vector(to_unsigned(1,8));
+ t(7 downto 0) := std_logic_vector(to_unsigned(USE_PINOUT,8));
t(11 downto 8) := std_logic_vector(to_unsigned(DOUBLE_EDGE_TYPE,4));
t(14 downto 12) := std_logic_vector(to_unsigned(RING_BUFFER_SIZE,3));
t(15) := '1'; --TDC
project_path => "ADA_Addon",
lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de";
lm_license_file_for_par => "1702\@hadeb05.gsi.de",
-lattice_path => '/d/jspc29/lattice/diamond/3.6_x64',
-synplify_path => '/d/jspc29/lattice/synplify/K-2015.09/',
+lattice_path => '/d/jspc29/lattice/diamond/3.9_x64',
+synplify_path => '/d/jspc29/lattice/synplify/L-2016.09-1/',
# synplify_command => "/d/jspc29/lattice/diamond/3.5_x64/bin/lin64/synpwrap -fg -options",
#synplify_command => "/d/jspc29/lattice/synplify/J-2014.09-SP2/bin/synplify_premier_dp",
#Include only necessary lpf files
#pinout_file => '', #name of pin-out file, if not equal TOPNAME
-include_TDC => 0,
+include_TDC => 1,
include_GBE => 0,
#Report settings
add_file -vhdl -lib work "tdc_release/BusHandler_record.vhd"
add_file -vhdl -lib work "tdc_release/Channel.vhd"
add_file -vhdl -lib work "tdc_release/Channel_200.vhd"
-add_file -vhdl -lib work "tdc_release/Encoder_288_Bit.vhd"
+add_file -vhdl -lib work "tdc_release/Encoder_304_Bit.vhd"
add_file -vhdl -lib work "tdc_release/fallingEdgeDetect.vhd"
add_file -vhdl -lib work "tdc_release/hit_mux.vhd"
add_file -vhdl -lib work "tdc_release/LogicAnalyser.vhd"