scaler update

diff --git a/scaler/trb3_periph_scaler_constraints.lpf b/scaler/trb3_periph_scaler_constraints.lpf
index e0888c6dd592e91efc090dd464be87deeb451a96..e924dbc5eb521c1ff3c2314b8cb292eb631a3d27 100644 (file)
--- a/scaler/trb3_periph_scaler_constraints.lpf
+++ b/scaler/trb3_periph_scaler_constraints.lpf
@@ -1,6 +1,5 @@
 #######################################################################
 
-
 BLOCK RESETPATHS ;
 BLOCK ASYNCPATHS ;
 BLOCK RD_DURING_WR_PATHS ;
@@ -55,75 +54,25 @@ LOCATE UGROUP "THE_SPI_MEMORY/SPI_group" REGION "REGION_SPI" ;
 #
 #################################################
 
+BLOCK PATH FROM CLKNET "clk_100_i" TO CLKNET "clk_scaler";
+BLOCK PATH FROM CLKNET "clk_scaler" TO CLKNET "clk_100_i";
 
 PROHIBIT PRIMARY   NET "quad_channel_0*";
 PROHIBIT SECONDARY NET "quad_channel_0*";
 
-MULTICYCLE FROM CELL   "THE_RESET_HANDLER/final_reset*"                                                  100 ns;
+#MULTICYCLE FROM CELL   "THE_RESET_HANDLER/final_reset*"                                                  100 ns;
 
-MULTICYCLE TO   CELL   "scaler_0/reset_d1_ff*[1]*"                                                       100 ns;
+#MULTICYCLE TO   CELL   "scaler_0/reset_d1_ff*[1]*"                                                       100 ns;
 
-MULTICYCLE TO   CELL   "scaler_0/scaler_channel_0/pulse_ff*[2]*"                                           30 ns;
+#MULTICYCLE TO   CELL   "scaler_0/scaler_channel_0/pulse_ff*[2]*"                                           30 ns;
 
-MULTICYCLE TO   CELL   "scaler_0/latch_handler_1/reset_ctr_ff*[2]*"                                        30 ns;
-MULTICYCLE TO   CELL   "scaler_0/latch_handler_1/latch_ff*[2]*"                                            30 ns;
+#MULTICYCLE TO   CELL   "scaler_0/latch_handler_1/reset_ctr_ff*[2]*"                                        30 ns;
+#MULTICYCLE TO   CELL   "scaler_0/latch_handler_1/latch_ff*[2]*"                                            30 ns;
 
 MULTICYCLE TO   GROUP  "TEST_LINE_group"          500.000000 ns ;
 MAXDELAY   TO   GROUP  "TEST_LINE_group"          500.000000 ns ;
 
 
-# MULTICYCLE TO   CELL "nXyter_FEE_board_*/nx_trigger_handler_*/trigger_busy_ff*"                            30 ns;
-# MULTICYCLE to   CELL "nXyter_FEE_board_*/nx_trigger_handler_*/fast_clear_ff*"                              30 ns;
-# MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_handler_*/reg_testpulse_delay*"                       100 ns;
-# MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_handler_*/reg_testpulse_length*"                      100 ns;
-# MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_handler_*/reg_testpulse_enable*"                      100 ns;
-# MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_handler_*/calibration_trigger_o*"                      50 ns;
-# MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_handler_*/timestamp_calib_trigger_c*"                  20 ns;
-# 
-# MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_generator_*/internal_trigger_o*"                      100 ns;
-# 
-# MULTICYCLE TO   CELL "nXyter_FEE_board_*/nx_fpga_timestamp_*/reset_nx_main_clk_in_ff*"                     30 ns;
-# MULTICYCLE TO   CELL "nXyter_FEE_board_*/nx_fpga_timestamp_*/timestamp_reset_ff*"                          10 ns;
-# MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_fpga_timestamp_*/timestamp_hold_o_*"                           30 ns;
-# 
-# MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/reset_nx_timestamp_clk_in_ff*"                 30 ns;
-# MULTICYCLE TO   CELL "nXyter_FEE_board_*/nx_data_receiver_*/merge_handler_reset_i*"                        30 ns;
-# MULTICYCLE TO   CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_reset_handler_cnx_ff*"                     30 ns;
-# MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/reset_handler_start_r*"                       100 ns;
-# MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/johnson_counter_sync_r*"                      100 ns;
-# MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/nx_timestamp_delay_s*"                        100 ns;
-# MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/pll_adc_sample_clk_finedelb_r*"               100 ns;
-# MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/pll_adc_sample_clk_dphase_r*"                 100 ns;
-# MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/pll_adc_sampling_clk_reset*"                  100 ns;
-# MULTICYCLE TO   CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_dt_error_ctr_r*"                          100 ns;
-# MULTICYCLE TO   CELL "nXyter_FEE_board_*/nx_data_receiver_*/timestamp_dt_error_ctr_*"                     100 ns;
-# MULTICYCLE TO   CELL "nXyter_FEE_board_*/nx_data_receiver_*/merge_error_ctr_r*"                           100 ns;
-# MULTICYCLE TO   CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_sclk_ok_f*"                               100 ns; 
-# MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_debug_type_r*"                            100 ns;
-# MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/nx_timestamp_reset_o*"                        100 ns;
-# MULTICYCLE TO   CELL "nXyter_FEE_board_*/nx_data_receiver_*/nx_frame_synced_rr*"                          100 ns;
-# MULTICYCLE TO   CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_debug_type_f*"                            100 ns;
-# 
-# MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_validate_*/readout_mode_r_*"                          100 ns;
-# MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_validate_*/cts_trigger_delay_*"                       100 ns;
-# MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_validate_*/ts_window_offset_*"                        100 ns;
-# MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_validate_*/ts_window_width_*"                         100 ns;
-# MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_validate_*/readout_time_max_*"                        100 ns;
-# MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_validate_*/fpga_timestamp_offset_*"                   100 ns;
-# 
-# MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_event_buffer_*/fifo_almost_full_thr_*"                        100 ns;
-# 
-# 
-# MULTICYCLE FROM CELL "nXyter_FEE_board_*/debug_multiplexer_*/port_select_*"                               500 ns;
-# 
-# 
-# MULTICYCLE TO   CELL "nXyter_FEE_board_*/nx_data_receiver_*/new_adc_dt_error_ctr_*"                       100 ns;
-# MULTICYCLE TO   CELL "nXyter_FEE_board_*/nx_data_receiver_*/new_timestamp_dt_error_ctr_*"                 100 ns;
-# MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_error_status_i_*"                         100 ns;
-# MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_ad9228_*/adc_ad9228_data_handler*/adc_locked_o*" 100 ns;
-# 
-
-
 #################################################################
 # Constraints for nxyter inputs
 #################################################################