entity Cal_Limits_v2 is
generic (
- cal_Limit_gen : unsigned(19 downto 0) := "00000000000000001000";--"00000000000100000000";
+ cal_Limit_gen : unsigned(19 downto 0) := "00000000000100000000";--"00000000000100000000";
locBufDepth : integer := 7
);
port (
chnl_next : in std_logic_vector( 6 downto 0);
Do_Cal_in : in std_logic;
chnl_cnt_in : in unsigned(19 downto 0);
- new_data : in std_logic;
write_curr : out std_logic;
write_next : out std_logic;
min_next : out std_logic_vector( 9 downto 0);
FPGA_out_write_cnt : out std_logic_vector( 3 downto 0);
cal_Limit_set : out unsigned (19 downto 0);
BUS_Flash_value : in std_logic_vector(27 downto 0);
- Flash_flag : in std_logic
+ Flash_flag : in std_logic;
+ Debug_Data_min : out std_logic_vector(31 downto 0);
+ Debug_Data_max : out std_logic_vector(31 downto 0)
);
end Cal_Limits_v2;
signal cnt_ii : unsigned(19 downto 0):="00000000000000000000";
signal chnl_i : std_logic_vector( 6 downto 0);
signal use_old : std_logic:='0';
- signal cal_Limit : unsigned(19 downto 0):="00000000000000001000";--"00011000011010100000";
+ signal cal_Limit : unsigned(19 downto 0):="00011000011010100000";--"00011000011010100000";
type array2D is array (1 downto 0, 0 to 64) of std_logic_vector(19 downto 0); --(FPGA)(channel)
signal def_value : array2D := (others => ("10000000010000000010","10000000100000000010","10000000110000000010","10000001000000000010",
begin
if rising_edge(CLK) then
- -- if (cal_Limit_reg <= cal_Limit_gen) then
- -- cal_Limit <= cal_Limit_gen;
- -- cal_Limit_set <= cal_Limit_gen;
- -- else
- -- cal_Limit <= cal_Limit_reg;
- -- cal_Limit_set <= cal_Limit_reg;
- -- end if;
+ if (cal_Limit_reg <= cal_Limit_gen) then
+ cal_Limit <= cal_Limit_gen;
+ cal_Limit_set <= cal_Limit_gen;
+ else
+ cal_Limit <= cal_Limit_reg;
+ cal_Limit_set <= cal_Limit_reg;
+ end if;
end if;
end process;
else -- no calibr
write_curr <= '0';
write_next <= '0';
- min_out <= "1111111111";
- max_out <= "0000000000";
- min_curr <= "1111111111";
- max_curr <= "0000000000";
+ --min_out <= "1111111111";
+ --max_out <= "0000000000";
+ --min_curr <= "1111111111";
+ --max_curr <= "0000000000";
EBRbufNext(locBufDepth-1) <= x"00000000";
EBRbufCurr(locBufDepth-1) <= x"00000000";
end if;
EBRbufCurr(locBufDepth-1) <= "10" & FPGA_r & chnl_r(5 downto 0) & def_value(0,to_integer(unsigned(chnl_r)))(19 downto 10) & def_value(0,to_integer(unsigned(chnl_r)))( 9 downto 0);
else
write_curr <= '0';
- min_out <= b"0000000000";
- max_out <= b"0000000000";
+ --min_out <= b"0000000000";
+ --max_out <= b"0000000000";
min_curr <= b"0000000000";
max_curr <= b"0000000000";
min_curr_i <= b"0000000000";
if cnt_i /= to_unsigned(0,20) then --next memory
if unsigned(DIN_r(21 downto 12)) >= unsigned(EBRNext_Max_v) then
EBRNext_Max_v := DIN_r(21 downto 12);
+ Debug_Data_max <= DIN_r;
if unsigned(DIN_r(21 downto 12)) < unsigned(EBRNext_Min_v) then
EBRNext_Min_v := DIN_r(21 downto 12);
+ Debug_Data_min <= DIN_r;
end if;
else
if unsigned(DIN_r(21 downto 12)) < unsigned(EBRNext_Min_v) then
EBRNext_Min_v := DIN_r(21 downto 12);
+ Debug_Data_min <= DIN_r;
end if;
end if;
else
entity TDC_Calibration is
Port (
CLK : in std_logic;
- CLK_inv : in std_logic;
RESET : in std_logic;
DIN : in std_logic_vector(31 downto 0);
DIN_TYPE : in std_logic_vector( 3 downto 0);
signal chnl_out_write_cnt : std_logic_vector(6 downto 0);
signal FPGA_out_write_cnt : std_logic_vector(3 downto 0);
- signal docal_debug_out, docal_debug_in : unsigned(31 downto 0);
+ signal docal_debug_out, docal_debug_in: unsigned(31 downto 0);
+ signal Debug_Data_min, Debug_Data_max : std_logic_vector(31 downto 0);
begin
BUS_TX.ack <= '1';
case BUS_RX.addr(11 downto 0) is
when x"000" => BUS_TX.data(31 downto 1) <= (others => '0');
- BUS_TX.data(0) <= BUS_do_Cal;
+ BUS_TX.data( 0) <= BUS_do_Cal;
when x"001" => BUS_TX.data(31 downto 20) <= (others => '0');
BUS_TX.data(19 downto 0) <= std_logic_vector(cal_Limit_set);
+ when x"002" => BUS_TX.data( 3 downto 0) <= Bus_FPGA;
+ BUS_TX.data(31 downto 4) <= (others => '0');
+ when x"003" => BUS_TX.data( 6 downto 0) <= Bus_Chnl;
+ BUS_TX.data(31 downto 7) <= (others => '0');
when x"004" => BUS_TX.data(31 downto 10) <= (others => '0');
BUS_TX.data( 9 downto 0) <= Bus_min;
when x"005" => BUS_TX.data(31 downto 10) <= (others => '0');
BUS_TX.data( 9 downto 0) <= Bus_max;
when x"006" => BUS_TX.data <= std_logic_vector(docal_debug_in);
when x"007" => BUS_TX.data <= std_logic_vector(docal_debug_out);
- when others => BUS_TX.ack <= '0';
+
+ when x"008" => BUS_TX.data(11 downto 8) <= FPGA_Lim;
+ BUS_TX.data(7) <= '0';
+ BUS_TX.data( 6 downto 0) <= chnl_Lim;
+ BUS_TX.data(31 downto 12) <= (others => '0');
+ when x"009" => BUS_TX.data(31 downto 20) <= (others => '0');
+ BUS_TX.data(19 downto 0) <= std_logic_vector(cal_cnt_in);
+ when x"00A" => BUS_TX.data <= Debug_Data_min;
+ when x"00B" => BUS_TX.data <= Debug_Data_max;
+ when others => BUS_TX.ack <= '0';
BUS_TX.unknown <= '1';
end case;
end if;
ent_cnt_val : entity work.cnt_val
port map(
CLK => CLK,
- CLK_inv => CLK_inv,
RESET => RESET,
read => read_compare_old,
write => write_chnl_cnt,
Mem_next : entity work.Memory
port map(
CLK => CLK,
- CLK_inv => CLK_inv,
RESET => RESET,
read => read_compare_old,
write => write_next,
Mem_curr : entity work.Memory_curr
port map(
CLK => CLK,
- CLK_inv => CLK_inv,
RESET => RESET,
read => read_compare_old,
write => write_curr,
Cal_Limits : entity work.Cal_Limits_v2
generic map(
- cal_Limit_gen => "00000000000000001000" -- 16
- )
+ cal_Limit_gen => "00000010011100010000" -- 10k
+ )
port map(
CLK => CLK,
cal_Limit_reg => Cal_Limit_reg,
chnl_next => CHNL_out_compare_old,
Do_Cal_in => Do_Cal_Memory,
chnl_cnt_in => cal_cnt_out,
- new_data => new_data_Memory,
write_curr => write_curr,
write_next => write_next,
min_next => min_next_Lim,
chnl_out_write => chnl_out_write,
FPGA_out_write => FPGA_out_write,
chnl_out_write_cnt => chnl_out_write_cnt,
- FPGA_out_write_cnt => FPGA_out_write_cnt,
+ FPGA_out_write_cnt => FPGA_out_write_cnt,
FPGA_out_curr => FPGA_out_curr,
chnl_out_curr => chnl_out_curr,
cal_Limit_set => cal_Limit_set,
BUS_Flash_value => BUS_Flash_value,
- Flash_flag => Flash_flag
+ Flash_flag => Flash_flag,
+ Debug_Data_min => Debug_Data_min,
+ Debug_Data_max => Debug_Data_max
);
LUTs : entity work.LUT
FPGA_out => FPGA_CalcOut
);
-
- DIN_i_Mem <= DIN;
+ THE_Enable : process
+ begin
+ wait until rising_edge(CLK);
+ if DIN_READY = '1' then
+ DIN_i_Mem <= DIN;
+ DIN_i_Mem_type <= DIN_TYPE;
+ end if;
DIN_i_Mem_ready <= DIN_READY;
- DIN_i_Mem_type <= DIN_TYPE;
-
+ end process;
+
- fine_out : process (CLK, Do_cal_CalcOut, slope_LUT, factor)
+ fine_out : process (CLK)
begin
if rising_edge(CLK) then
entity Memory is
Port (
CLK : in std_logic;
- CLK_inv : in std_logic;
RESET : in std_logic;
read : in std_logic;
write : in std_logic;
entity Memory_curr is
port (
CLK : in std_logic;
- CLK_inv : in std_logic;
RESET : in std_logic;
read : in std_logic;
write : in std_logic;
);
- mem : process (CLK,read,write)
+ mem : process (CLK)
begin
if rising_edge(CLK) then
-- handle read/write on same Address;
DIN_type_2r <= DIN_type_r;
DOUT_type <= DIN_type_2r;
- new_data <= read;
fpga_r <= FPGA_read;
fpga_2r <= fpga_r;
FPGA_out <= fpga_2r;
entity cnt_val is
Port (
CLK : in std_logic;
- CLK_inv : in std_logic;
RESET : in std_logic;
read : in std_logic;
write : in std_logic;
);
- mem : process (CLK,read,write)
+ mem : process (CLK)
begin
if rising_edge(CLK) then
-- handle read/write on same Address;
begin
if rising_edge(CLK) then
- if (DIN(31) = '1') and (DIN_type = x"4")then
+ if (DIN(31) = '1') and (DIN_type = x"4") and (DIN_ready = '1') then
chnl <= DIN(28 downto 22);
FPGA_out <= std_logic_vector(to_unsigned(FPGA_i,4));
- if DIN(21 downto 12) = "1111111111" then --3FF
- Do_Cal <= '0';
- else
+ if DIN(21 downto 12) /= "1111111111" and FPGA_in(15 downto 12) = x"1" then --3FF
Do_Cal <= '1';
+ else
+ Do_Cal <= '0';
end if;
else
--FPGA_i <= 0;
if RESET = '1' then
cnt <= 0;
else
- C1 : case FPGA_in is
- when x"156d" => FPGA_i <= 0;
- when x"1691" => FPGA_i <= 1;
- when x"13f9" => FPGA_i <= 2;
- when x"12ee" => FPGA_i <= 3;
- when x"12f8" => FPGA_i <= 4;
- when x"1403" => FPGA_i <= 5;
- when x"1663" => FPGA_i <= 6;
- when others => FPGA_i <= 7;
- end case C1;
-
+ if DIN_ready = '1' then
+ C1 : case FPGA_in is
+ when x"156d" => FPGA_i <= 0;
+ when x"1691" => FPGA_i <= 1;
+ when x"13f9" => FPGA_i <= 2;
+ when x"12ee" => FPGA_i <= 3;
+ when x"12f8" => FPGA_i <= 4;
+ when x"1403" => FPGA_i <= 5;
+ when x"1663" => FPGA_i <= 6;
+ when others => FPGA_i <= 7;
+ end case C1;
+ end if;
-- for i in 0 to 11 loop
-- if FPGA_in = FPGA_num(i) then
-- save(i) <= '1';
when SSE_DATA_L => --Analysing Data
if (fee_dataready and fee_read) = '1' then
pckr_Data(15 downto 0) <= fee_data;
- pckr_Data_type <= x"4"; --SSE_DATA
+ if fpga_flag = '1' then
+ pckr_Data_type <= x"5"; --SSE_DATA
+ else
+ pckr_Data_type <= x"4"; --SSE_DATA
+ end if;
pckr_Data_ready <= '1';
if fpga_flag = '1' then
FPGA <= fee_data;
when DATA =>
- if pckr_TX_data_type = x"3" or pckr_TX_data_type = x"4" then
+ if pckr_TX_data_type = x"3" or pckr_TX_data_type = x"4" or pckr_TX_data_type = x"5" then
if dataready = '1' then
cts_data <= pckr_TX_data;
cts_dataready <= '1';
jspc29 / dirich.git / commitdiff