SCI poll time changed, cleanup

diff --git a/media_interfaces/sync/main_rx_reset_RS.vhd b/media_interfaces/sync/main_rx_reset_RS.vhd
index 96bc90b48ca03d0584b6d98a450a1ce37982a5f1..aec67017e6beb42fcc2053f4b850ae8dc99da3b7 100644 (file)
--- a/media_interfaces/sync/main_rx_reset_RS.vhd
+++ b/media_interfaces/sync/main_rx_reset_RS.vhd
@@ -30,13 +30,9 @@ architecture main_rx_reset_RS_arch of main_rx_reset_RS is
 -- Without this piece of code, many things would have been a real pain.\r
 \r
   constant Tshort_bit : integer := 4; -- count up to 2^4 = 16\r
---  constant Tshort     : unsigned(31 downto 0) := x"0000000a";\r
   constant Tplol_bit  : integer := 22;\r
---  constant Tplol      : unsigned(31 downto 0) := x"003fffff"; --x"01312d00";\r
   constant Tcdr_bit   : integer := 22;\r
---  constant Tcdr       : unsigned(31 downto 0) := x"003fffff"; --x"01312d00";\r
   constant Tviol_bit  : integer := 22;\r
---  constant Tviol      : unsigned(31 downto 0) := x"003fffff"; --x"01312d00";\r
 \r
   signal pll_lol_s    : std_logic;\r
   signal cdr_lol_s    : std_logic;\r
@@ -100,7 +96,6 @@ begin
           if( (pll_lol_s = '1') or (sd_los_s = '1') ) then\r
             cnt <= (others => '0');\r
           else\r
---            if( cnt = Tplol ) then\r
             if( cnt(Tplol_bit) = '1' ) then\r
               cnt <= (others => '0');\r
               rx_sm <= APPLY_CDR_RST;\r
@@ -114,7 +109,6 @@ begin
           RX_SERDES_RST_OUT <= '1';\r
           RX_PCS_RST_OUT    <= '1';\r
           LINK_RX_READY_OUT <= '0';\r
---          if( cnt = Tshort ) then\r
           if( cnt(Tshort_bit) = '1' ) then\r
             cnt <= (others => '0');\r
             rx_sm <= WAIT_CDR_LOCK;\r
@@ -127,7 +121,6 @@ begin
           RX_SERDES_RST_OUT <= '0';\r
           RX_PCS_RST_OUT    <= '1';\r
           LINK_RX_READY_OUT <= '0';\r
---          if( cnt = Tcdr ) then\r
           if( cnt(Tcdr_bit) = '1' ) then\r
             cnt <= (others => '0');\r
             rx_sm <= TEST_CDR;\r
@@ -144,7 +137,6 @@ begin
             cnt <= (others => '0');\r
             rx_sm <= APPLY_CDR_RST;\r
           else\r
---            if( cnt = Tcdr ) then\r
             if( cnt(Tcdr_bit) = '1' ) then\r
               cnt <= (others => '0');\r
               rx_sm <= APPLY_RXPCS_RST;\r
@@ -158,7 +150,6 @@ begin
           RX_SERDES_RST_OUT <= '0';\r
           RX_PCS_RST_OUT    <= '1';\r
           LINK_RX_READY_OUT <= '0';\r
---          if( cnt = Tshort ) then\r
           if( cnt(Tshort_bit) ) then\r
             cnt <= (others => '0');\r
             rx_sm <= WAIT_RXPCS_LOCK;\r
@@ -171,7 +162,6 @@ begin
           RX_SERDES_RST_OUT <= '0';\r
           RX_PCS_RST_OUT    <= '0';\r
           LINK_RX_READY_OUT <= '0';\r
---          if( cnt = Tviol ) then\r
           if( cnt(Tviol_bit) = '1' ) then\r
             cnt <= (others => '0');\r
             rx_sm <= TEST_RXPCS;\r
@@ -188,7 +178,6 @@ begin
             cnt <= (others => '0');\r
             rx_sm <= APPLY_RXPCS_RST;\r
           else\r
---            if( cnt = Tviol ) then\r
             if( cnt(Tviol_bit) = '1' ) then\r
               cnt <= (others => '0');\r
               rx_sm <= CHECK_WAP;\r
@@ -203,7 +192,6 @@ begin
           RX_PCS_RST_OUT    <= '0';\r
           LINK_RX_READY_OUT <= '0';\r
           cnt <= (others => '0');\r
---          if( cnt = Tshort ) then\r
           if( cnt(Tshort_bit) = '1' ) then\r
             cnt <= (others => '0');\r
             if( wap_zero_s = '1' ) then\r
@@ -238,8 +226,6 @@ begin
       end case;\r
   \r
 ------------------------------------------------\r
---    if (pll_lol_s = '1') or (los_s = '1') then\r
---    if( pll_lol_s = '1' ) then\r
       if( (pll_lol_s = '1') or (sd_los_s = '1') ) then\r
         rx_sm <= POWERUP;      \r
         cnt <= (others => '0');\r
@@ -248,6 +234,7 @@ begin
     end if;\r
   end process rx_reset_proc;\r
 \r
-  WAP_REQ_OUT <= '1' when ((rx_sm = WAIT_RXPCS_LOCK) or (rx_sm = TEST_RXPCS)) else '0';\r
+--  WAP_REQ_OUT <= '1' when ((rx_sm = WAIT_RXPCS_LOCK) or (rx_sm = TEST_RXPCS)) else '0';\r
+  WAP_REQ_OUT <= '1' when ((rx_sm = TEST_RXPCS)) else '0';\r
   \r
 end architecture;\r

diff --git a/media_interfaces/sync/sci_reader_RS.vhd b/media_interfaces/sync/sci_reader_RS.vhd
index 3178438408c3dc20230e768dba7c3a6519afef6f..0898aaf2653c46268011e32fc9c7edd63f4f056d 100644 (file)
--- a/media_interfaces/sync/sci_reader_RS.vhd
+++ b/media_interfaces/sync/sci_reader_RS.vhd
@@ -39,7 +39,7 @@ architecture sci_reader_arch of sci_reader_RS is
 type sci_ctrl is (IDLE, SCTRL, SCTRL_WAIT, SCTRL_WAIT2, SCTRL_FINISH, GET_WA, GET_WA_WAIT, GET_WA_WAIT2, GET_WA_FINISH);
 
 signal sci_state         : sci_ctrl;
-signal sci_timer         : unsigned(14 downto 0) := (others => '0');
+signal sci_timer         : unsigned(16 downto 0) := (others => '0');
 
 signal sci_reg_i         : std_logic;
 signal wa_position       : std_logic_vector(15 downto 0);