update TriggerGenerator xml file

diff --git a/xml-db/database/InputMonitorTrb3sc.xml b/xml-db/database/InputMonitorTrb3sc.xml
index 128bea7c3de5f9db6fd21a591261a10b5dc4642b..1fb041cf0b297400164d9cbf92057f146b417307 100644 (file)
--- a/xml-db/database/InputMonitorTrb3sc.xml
+++ b/xml-db/database/InputMonitorTrb3sc.xml
@@ -90,19 +90,22 @@
 
   <group name="Trigger" purpose="config" address="0000" size="256" mode="rw" continuous="false">
     <description>Registers of the trigger generation logic</description>  
-    <group name="TriggerGeneration" purpose="config" address="0000" size="3" continuous="true">
-      <register name="TriggerEnable1" address="0000"  mode="rw" >
-        <description>Enables individual inputs 0 - 31 for trigger generation. If enabled, the input adds to the common or</description>
-        <field  name="TriggerEnable" start="0" bits="32" format="bitmask" noflag="true" />
+    <group name="TriggerGeneration" purpose="config" address="0000" size="4" repeat="8" continuous="false">
+      <register name="TriggerEnable1" address="0000"  mode="rw">
+        <description>Enables individual inputs 0 - 31 for trigger generation. If enabled, the input adds to the common or of 
+output #slice</description>
+        <field  name="TriggerEnable1" start="0" bits="32" format="bitmask" noflag="true" />
       </register>
-      <register name="TriggerEnable2" address="0001"  mode="rw" >
-        <description>Enables individual inputs 63 - 32 for trigger generation. If enabled, the input adds to the common or</description>
+      <register name="TriggerEnable2" address="0001"  mode="rw">
+        <description>Enables individual inputs 32-63 for trigger generation. If enabled, the input adds to the common or of 
+output #slice</description>
         <field  name="TriggerEnable2" start="0" bits="32" format="bitmask" noflag="true" />
       </register>
-      <register name="TriggerEnable3" address="0002"  mode="rw" >
-        <description>Enables individual inputs 95 - 64 for trigger generation. If enabled, the input adds to the common or</description>
+      <register name="TriggerEnable3" address="0002"  mode="rw">
+        <description>Enables individual inputs 64-95 for trigger generation. If enabled, the input adds to the common or of 
+output #slice</description>
         <field  name="TriggerEnable3" start="0" bits="32" format="bitmask" noflag="true" />
-      </register>      
+      </register>
     </group>