--- /dev/null
+library IEEE;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.all;
+library ieee;
+library work;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.all;
+
+entity system is
+
+end system;
+architecture system of system is
+ component hub
+ port (
+ LVDS_CLK_200P : in std_logic;
+ ADO_TTL : inout std_logic_vector(46 downto 0);
+ DBAD : out std_logic;
+ DGOOD : out std_logic;
+ DINT : out std_logic;
+ DWAIT : out std_logic;
+ LOK : out std_logic_vector(16 downto 1);
+ RT : out std_logic_vector(16 downto 1);
+ TX_DIS : out std_logic_vector(16 downto 1);
+ IPLL : out std_logic;
+ OPLL : out std_logic;
+ SFP_INP_N : in std_logic_vector(15 downto 0);
+ SFP_INP_P : in std_logic_vector(15 downto 0);
+ SFP_OUT_N : out std_logic_vector(15 downto 0);
+ SFP_OUT_P : out std_logic_vector(15 downto 0);
+ OPT_DATA_IN : in std_logic_vector(31 downto 0);
+ OPT_DATA_OUT : out std_logic_vector(31 downto 0);
+ OPT_DATA_VALID_IN : in std_logic_vector(1 downto 0);
+ OPT_DATA_VALID_OUT : out std_logic_vector(1 downto 0));
+ end component;
+ component trb_v2b_fpga
+ port (
+ VIRT_CLK : in std_logic;
+ VIRT_CLKB : in std_logic;
+ RESET_VIRT : in std_logic;
+ DBAD : out std_logic;
+ DGOOD : out std_logic;
+ DINT : out std_logic;
+ DWAIT : out std_logic;
+ A_RESERVED : in std_logic;
+ A_TEMP : in std_logic;
+ B_RESERVED : in std_logic;
+ B_TEMP : in std_logic;
+ C_RESERVED : in std_logic;
+ C_TEMP : in std_logic;
+ D_RESERVED : in std_logic;
+ D_TEMP : in std_logic;
+ VIR_TRIG : in std_logic;
+ VIR_TRIGB : in std_logic;
+ A_TDC_ERROR : in std_logic;
+ B_TDC_ERROR : in std_logic;
+ C_TDC_ERROR : in std_logic;
+ D_TDC_ERROR : in std_logic;
+ A_TDC_POWERUP : out std_logic;
+ B_TDC_POWERUP : out std_logic;
+ C_TDC_POWERUP : out std_logic;
+ D_TDC_POWERUP : out std_logic;
+ TOKEN_IN : in std_logic;
+ TOKEN_OUT : out std_logic;
+ C_TOKEN_OUT_TTL : in std_logic;
+ GET_DATA : out std_logic;
+ A_DATA_READY : in std_logic;
+ B_DATA_READY : in std_logic;
+ C_DATA_READY : in std_logic;
+ D_DATA_READY : in std_logic;
+ REF_TDC_CLK : in std_logic;
+ REF_TDC_CLKB : in std_logic;
+ A_TDC_BU_RESET : out std_logic;
+ A_TDC_BU_RESETB : out std_logic;
+ A_TDC_EV_RESET : out std_logic;
+ A_TDC_EV_RESETB : out std_logic;
+ B_TDC_BU_RESET : out std_logic;
+ B_TDC_BU_RESETB : out std_logic;
+ B_TDC_EV_RESET : out std_logic;
+ B_TDC_EV_RESETB : out std_logic;
+ C_TDC_BU_RESET : out std_logic;
+ C_TDC_BU_RESETB : out std_logic;
+ C_TDC_EV_RESET : out std_logic;
+ C_TDC_EV_RESETB : out std_logic;
+ D_TDC_BU_RESET : out std_logic;
+ D_TDC_BU_RESETB : out std_logic;
+ D_TDC_EV_RESET : out std_logic;
+ D_TDC_EV_RESETB : out std_logic;
+ TDC_OUT : in std_logic_vector (31 downto 0);
+ TDC_RESET : out std_logic;
+ A_TRIGGER : out std_logic;
+ A_TRIGGERB : out std_logic;
+ B_TRIGGER : out std_logic;
+ B_TRIGGERB : out std_logic;
+ C_TRIGGER : out std_logic;
+ C_TRIGGERB : out std_logic;
+ D_TRIGGER : out std_logic;
+ D_TRIGGERB : out std_logic;
+ FS_PB : out std_logic_vector (17 downto 0);
+ FS_PC : inout std_logic_vector (17 downto 0);
+ ETRAX_IRQ : out std_logic;
+ A_SCK : out std_logic;
+ A_SCKB : out std_logic;
+ A_SDI : in std_logic;
+ A_SDIB : in std_logic;
+ A_SDO : out std_logic;
+ A_SDOB : out std_logic;
+ A_CSB : out std_logic;
+ A_CS : out std_logic;
+ B_SCK : out std_logic;
+ B_SCKB : out std_logic;
+ B_SDI : in std_logic;
+ B_SDIB : in std_logic;
+ B_SDO : out std_logic;
+ B_SDOB : out std_logic;
+ B_CSB : out std_logic;
+ B_CS : out std_logic;
+ C_SCK : out std_logic;
+ C_SCKB : out std_logic;
+ C_SDI : in std_logic;
+ C_SDIB : in std_logic;
+ C_SDO : out std_logic;
+ C_SDOB : out std_logic;
+ C_CSB : out std_logic;
+ C_CS : out std_logic;
+ D_SCK : out std_logic;
+ D_SCKB : out std_logic;
+ D_SDI : in std_logic;
+ D_SDIB : in std_logic;
+ D_SDO : out std_logic;
+ D_SDOB : out std_logic;
+ D_CSB : out std_logic;
+ D_CS : out std_logic;
+ A_TEST1 : out std_logic;
+ A_TEST1B : out std_logic;
+ A_TEST2 : out std_logic;
+ A_TEST2B : out std_logic;
+ B_TEST1 : out std_logic;
+ B_TEST1B : out std_logic;
+ B_TEST2 : out std_logic;
+ B_TEST2B : out std_logic;
+ C_TEST1 : out std_logic;
+ C_TEST1B : out std_logic;
+ C_TEST2 : out std_logic;
+ C_TEST2B : out std_logic;
+ D_TEST1 : out std_logic;
+ D_TEST1B : out std_logic;
+ D_TEST2 : out std_logic;
+ D_TEST2B : out std_logic;
+ DSPADDR : out std_logic_vector (31 downto 0);
+ DSPDAT : inout std_logic_vector (31 downto 0);
+ DSP_ACK : in std_logic;
+ DSP_BM : inout std_logic;
+ DSP_BMS : out std_logic;
+ DSP_BOFF : out std_logic;
+ DSP_BRST : inout std_logic;
+ DSP_HBG : in std_logic;
+ DSP_HBR : out std_logic;
+ DSP_IRQ : out std_logic_vector (3 downto 0);
+ DSP_RD : out std_logic;
+ DSP_RESET : out std_logic;
+ DSP_RESET_OUT : in std_logic;
+ DSP_WRH : out std_logic;
+ DSP_WRL : out std_logic;
+ VSD_A : out std_logic_vector (12 downto 0);
+ VSD_BA : out std_logic_vector (1 downto 0);
+ VSD_CAS : out std_logic;
+ VSD_CKE : out std_logic;
+ VSD_CLOCK : out std_logic;
+ VSD_CSEH : out std_logic;
+ VSD_CSEL : out std_logic;
+ VSD_D : inout std_logic_vector (31 downto 0);
+ VSD_DQML : out std_logic_vector (3 downto 0);
+ VSD_RAS : out std_logic;
+ VSD_WE : out std_logic;
+ TLK_CLK : in std_logic;
+ TLK_ENABLE : out std_logic;
+ TLK_LCKREFN : out std_logic;
+ TLK_LOOPEN : out std_logic;
+ TLK_PRBSEN : out std_logic;
+ TLK_RXD : in std_logic_vector (15 downto 0);
+ TLK_RX_CLK : in std_logic;
+ TLK_RX_DV : in std_logic;
+ TLK_RX_ER : in std_logic;
+ TLK_TXD : out std_logic_vector (15 downto 0);
+ TLK_TX_EN : out std_logic;
+ TLK_TX_ER : out std_logic;
+ SFP_LOS : in std_logic;
+ SFP_TX_DIS : out std_logic;
+ SFP_TX_FAULT : in std_logic;
+ ADO_LV : in std_logic_vector(51 downto 0);
+ ADO_TTL : inout std_logic_vector(46 downto 0);
+ VIRT_TCK : out std_logic;
+ VIRT_TDI : out std_logic;
+ VIRT_TDO : in std_logic;
+ VIRT_TMS : out std_logic;
+ VIRT_TRST : out std_logic);
+ end component;
+component cts
+ port (
+ VIRT_CLK : in std_logic;
+ VIRT_CLKB : in std_logic;
+ RESET_VIRT : in std_logic;
+ DBAD : out std_logic;
+ DGOOD : out std_logic;
+ DINT : out std_logic;
+ DWAIT : out std_logic;
+ FS_PB : out std_logic_vector (17 downto 0);
+ FS_PC : inout std_logic_vector (17 downto 0);
+ ETRAX_IRQ : out std_logic;
+ DSPADDR : out std_logic_vector (31 downto 0);
+ DSPDAT : inout std_logic_vector (31 downto 0);
+ DSP_ACK : in std_logic;
+ DSP_BM : inout std_logic;
+ DSP_BMS : out std_logic;
+ DSP_BOFF : out std_logic;
+ DSP_BRST : inout std_logic;
+ DSP_HBG : in std_logic;
+ DSP_HBR : out std_logic;
+ DSP_IRQ : out std_logic_vector (3 downto 0);
+ DSP_RD : out std_logic;
+ DSP_RESET : out std_logic;
+ DSP_RESET_OUT : in std_logic;
+ DSP_WRH : out std_logic;
+ DSP_WRL : out std_logic;
+ VSD_A : out std_logic_vector (12 downto 0);
+ VSD_BA : out std_logic_vector (1 downto 0);
+ VSD_CAS : out std_logic;
+ VSD_CKE : out std_logic;
+ VSD_CLOCK : out std_logic;
+ VSD_CSEH : out std_logic;
+ VSD_CSEL : out std_logic;
+ VSD_D : inout std_logic_vector (31 downto 0);
+ VSD_DQML : out std_logic_vector (3 downto 0);
+ VSD_RAS : out std_logic;
+ VSD_WE : out std_logic;
+ TLK_CLK : in std_logic;
+ TLK_ENABLE : out std_logic;
+ TLK_LCKREFN : out std_logic;
+ TLK_LOOPEN : out std_logic;
+ TLK_PRBSEN : out std_logic;
+ TLK_RXD : in std_logic_vector (15 downto 0);
+ TLK_RX_CLK : in std_logic;
+ TLK_RX_DV : in std_logic;
+ TLK_RX_ER : in std_logic;
+ TLK_TXD : out std_logic_vector (15 downto 0);
+ TLK_TX_EN : out std_logic;
+ TLK_TX_ER : out std_logic;
+ SFP_LOS : in std_logic;
+ SFP_TX_DIS : out std_logic;
+ SFP_TX_FAULT : in std_logic;
+ ADO_CLK1 : in std_logic;
+ ADO_CLK2 : in std_logic;
+ ADO_LV : in std_logic_vector(51 downto 0);
+ ADO_TTL : inout std_logic_vector(46 downto 2));
+ end component;
+ signal LVDS_CLK_200P_i : std_logic;
+ signal ADO_TTL_i : std_logic_vector(46 downto 2);
+ signal DBAD_i : std_logic;
+ signal DGOOD_i : std_logic;
+ signal DINT_i : std_logic;
+ signal DWAIT_i : std_logic;
+ signal LOK_i : std_logic_vector(16 downto 1);
+ signal RT_i : std_logic_vector(16 downto 1);
+ signal TX_DIS_i : std_logic_vector(16 downto 1);
+ signal IPLL_i : std_logic;
+ signal OPLL_i : std_logic;
+ signal SFP_INP_N_i : std_logic_vector(15 downto 0);
+ signal SFP_INP_P_i : std_logic_vector(15 downto 0);
+ signal SFP_OUT_N_i : std_logic_vector(15 downto 0);
+ signal SFP_OUT_P_i : std_logic_vector(15 downto 0);
+ signal OPT_DATA_IN_i : std_logic_vector(31 downto 0);
+ signal OPT_DATA_OUT_i : std_logic_vector(31 downto 0);
+ signal OPT_DATA_VALID_IN_i : std_logic_vector(1 downto 0);
+ signal OPT_DATA_VALID_OUT_i : std_logic_vector(1 downto 0);
+
+ signal VIRT_CLK_i : std_logic;
+ signal VIRT_CLKB_i : std_logic;
+ signal RESET_VIRT_i : std_logic;
+
+ signal A_RESERVED_i : std_logic;
+ signal A_TEMP_i : std_logic;
+ signal B_RESERVED_i : std_logic;
+ signal B_TEMP_i : std_logic;
+ signal C_RESERVED_i : std_logic;
+ signal C_TEMP_i : std_logic;
+ signal D_RESERVED_i : std_logic;
+ signal D_TEMP_i : std_logic;
+ signal VIR_TRIG_i : std_logic;
+ signal VIR_TRIGB_i : std_logic;
+ signal A_TDC_ERROR_i : std_logic;
+ signal B_TDC_ERROR_i : std_logic;
+ signal C_TDC_ERROR_i : std_logic;
+ signal D_TDC_ERROR_i : std_logic;
+ signal A_TDC_POWERUP_i : std_logic;
+ signal B_TDC_POWERUP_i : std_logic;
+ signal C_TDC_POWERUP_i : std_logic;
+ signal D_TDC_POWERUP_i : std_logic;
+ signal TOKEN_IN_i : std_logic;
+ signal TOKEN_OUT_i : std_logic;
+ signal C_TOKEN_OUT_TTL_i : std_logic;
+ signal GET_DATA_i : std_logic;
+ signal A_DATA_READY_i : std_logic;
+ signal B_DATA_READY_i : std_logic;
+ signal C_DATA_READY_i : std_logic;
+ signal D_DATA_READY_i : std_logic;
+ signal REF_TDC_CLK_i : std_logic;
+ signal REF_TDC_CLKB_i : std_logic;
+ signal A_TDC_BU_RESET_i : std_logic;
+ signal A_TDC_BU_RESETB_i : std_logic;
+ signal A_TDC_EV_RESET_i : std_logic;
+ signal A_TDC_EV_RESETB_i : std_logic;
+ signal B_TDC_BU_RESET_i : std_logic;
+ signal B_TDC_BU_RESETB_i : std_logic;
+ signal B_TDC_EV_RESET_i : std_logic;
+ signal B_TDC_EV_RESETB_i : std_logic;
+ signal C_TDC_BU_RESET_i : std_logic;
+ signal C_TDC_BU_RESETB_i : std_logic;
+ signal C_TDC_EV_RESET_i : std_logic;
+ signal C_TDC_EV_RESETB_i : std_logic;
+ signal D_TDC_BU_RESET_i : std_logic;
+ signal D_TDC_BU_RESETB_i : std_logic;
+ signal D_TDC_EV_RESET_i : std_logic;
+ signal D_TDC_EV_RESETB_i : std_logic;
+ signal TDC_OUT_i : std_logic_vector (31 downto 0);
+ signal TDC_RESET_i : std_logic;
+ signal A_TRIGGER_i : std_logic;
+ signal A_TRIGGERB_i : std_logic;
+ signal B_TRIGGER_i : std_logic;
+ signal B_TRIGGERB_i : std_logic;
+ signal C_TRIGGER_i : std_logic;
+ signal C_TRIGGERB_i : std_logic;
+ signal D_TRIGGER_i : std_logic;
+ signal D_TRIGGERB_i : std_logic;
+ signal FS_PB_i : std_logic_vector (17 downto 0);
+ signal FS_PC_i : std_logic_vector (17 downto 0);
+ signal ETRAX_IRQ_i : std_logic;
+ signal A_SCK_i : std_logic;
+ signal A_SCKB_i : std_logic;
+ signal A_SDI_i : std_logic;
+ signal A_SDIB_i : std_logic;
+ signal A_SDO_i : std_logic;
+ signal A_SDOB_i : std_logic;
+ signal A_CSB_i : std_logic;
+ signal A_CS_i : std_logic;
+ signal B_SCK_i : std_logic;
+ signal B_SCKB_i : std_logic;
+ signal B_SDI_i : std_logic;
+ signal B_SDIB_i : std_logic;
+ signal B_SDO_i : std_logic;
+ signal B_SDOB_i : std_logic;
+ signal B_CSB_i : std_logic;
+ signal B_CS_i : std_logic;
+ signal C_SCK_i : std_logic;
+ signal C_SCKB_i : std_logic;
+ signal C_SDI_i : std_logic;
+ signal C_SDIB_i : std_logic;
+ signal C_SDO_i : std_logic;
+ signal C_SDOB_i : std_logic;
+ signal C_CSB_i : std_logic;
+ signal C_CS_i : std_logic;
+ signal D_SCK_i : std_logic;
+ signal D_SCKB_i : std_logic;
+ signal D_SDI_i : std_logic;
+ signal D_SDIB_i : std_logic;
+ signal D_SDO_i : std_logic;
+ signal D_SDOB_i : std_logic;
+ signal D_CSB_i : std_logic;
+ signal D_CS_i : std_logic;
+ signal A_TEST1_i : std_logic;
+ signal A_TEST1B_i : std_logic;
+ signal A_TEST2_i : std_logic;
+ signal A_TEST2B_i : std_logic;
+ signal B_TEST1_i : std_logic;
+ signal B_TEST1B_i : std_logic;
+ signal B_TEST2_i : std_logic;
+ signal B_TEST2B_i : std_logic;
+ signal C_TEST1_i : std_logic;
+ signal C_TEST1B_i : std_logic;
+ signal C_TEST2_i : std_logic;
+ signal C_TEST2B_i : std_logic;
+ signal D_TEST1_i : std_logic;
+ signal D_TEST1B_i : std_logic;
+ signal D_TEST2_i : std_logic;
+ signal D_TEST2B_i : std_logic;
+ signal DSPADDR_i : std_logic_vector (31 downto 0);
+ signal DSPDAT_i : std_logic_vector (31 downto 0);
+ signal DSP_ACK_i : std_logic;
+ signal DSP_BM_i : std_logic;
+ signal DSP_BMS_i : std_logic;
+ signal DSP_BOFF_i : std_logic;
+ signal DSP_BRST_i : std_logic;
+ signal DSP_HBG_i : std_logic;
+ signal DSP_HBR_i : std_logic;
+ signal DSP_IRQ_i : std_logic_vector (3 downto 0);
+ signal DSP_RD_i : std_logic;
+ signal DSP_RESET_i : std_logic;
+ signal DSP_RESET_OUT_i : std_logic;
+ signal DSP_WRH_i : std_logic;
+ signal DSP_WRL_i : std_logic;
+ signal VSD_A_i : std_logic_vector (12 downto 0);
+ signal VSD_BA_i : std_logic_vector (1 downto 0);
+ signal VSD_CAS_i : std_logic;
+ signal VSD_CKE_i : std_logic;
+ signal VSD_CLOCK_i : std_logic;
+ signal VSD_CSEH_i : std_logic;
+ signal VSD_CSEL_i : std_logic;
+ signal VSD_D_i : std_logic_vector (31 downto 0);
+ signal VSD_DQML_i : std_logic_vector (3 downto 0);
+ signal VSD_RAS_i : std_logic;
+ signal VSD_WE_i : std_logic;
+ signal TLK_CLK_i : std_logic;
+ signal TLK_ENABLE_i : std_logic;
+ signal TLK_LCKREFN_i : std_logic;
+ signal TLK_LOOPEN_i : std_logic;
+ signal TLK_PRBSEN_i : std_logic;
+ signal TLK_RXD_i : std_logic_vector (15 downto 0);
+ signal TLK_RX_CLK_i : std_logic;
+ signal TLK_RX_DV_i : std_logic;
+ signal TLK_RX_ER_i : std_logic;
+ signal TLK_TXD_i : std_logic_vector (15 downto 0);
+ signal TLK_TX_EN_i : std_logic;
+ signal TLK_TX_ER_i : std_logic;
+ signal SFP_LOS_i : std_logic;
+ signal SFP_TX_DIS_i : std_logic;
+ signal SFP_TX_FAULT_i : std_logic;
+ signal ADO_LV_i : std_logic_vector(51 downto 0);
+
+ signal VIRT_TCK_i : std_logic;
+ signal VIRT_TDI_i : std_logic;
+ signal VIRT_TDO_i : std_logic;
+ signal VIRT_TMS_i : std_logic;
+ signal VIRT_TRST_i : std_logic;
+
+ signal FS_PB_CTS_i : std_logic_vector (17 downto 0);
+ signal FS_PC_CTS_i : std_logic_vector (17 downto 0);
+ signal TLK_CLK_CTS_i : std_logic;
+ signal TLK_ENABLE_CTS_i : std_logic;
+ signal TLK_LCKREFN_CTS_i : std_logic;
+ signal TLK_LOOPEN_CTS_i : std_logic;
+ signal TLK_PRBSEN_CTS_i : std_logic;
+ signal TLK_RXD_CTS_i : std_logic_vector (15 downto 0);
+ signal TLK_RX_CLK_CTS_i : std_logic;
+ signal TLK_RX_DV_CTS_i : std_logic;
+ signal TLK_RX_ER_CTS_i : std_logic;
+ signal TLK_TXD_CTS_i : std_logic_vector (15 downto 0);
+ signal TLK_TX_EN_CTS_i : std_logic;
+ signal TLK_TX_ER_CTS_i : std_logic;
+ signal SFP_LOS_CTS_i : std_logic;
+ signal SFP_TX_DIS_CTS_i : std_logic;
+ signal SFP_TX_FAULT_CTS_i : std_logic;
+ signal ADO_CLK1_i : std_logic;
+ signal ADO_CLK2_i : std_logic;
+ signal ADO_LV_CTS_i : std_logic_vector(51 downto 0);
+ signal ADO_TTL_CTS_i : std_logic_vector(46 downto 2);
+ signal vulom_lvl1_tag : std_logic_vector(15 downto 0);
+ signal test_synch_00 : std_logic;
+begin
+ HUB_INST: hub
+ port map (
+ LVDS_CLK_200P => LVDS_CLK_200P_i,
+ ADO_TTL => open,
+ DBAD => DBAD_i,
+ DGOOD => DGOOD_i,
+ DINT => DINT_i,
+ DWAIT => DWAIT_i,
+ LOK => LOK_i,
+ RT => RT_i,
+ TX_DIS => TX_DIS_i,
+ IPLL => IPLL_i,
+ OPLL => OPLL_i,
+ SFP_INP_N => SFP_INP_N_i,
+ SFP_INP_P => SFP_INP_P_i,
+ SFP_OUT_N => SFP_OUT_N_i,
+ SFP_OUT_P => SFP_OUT_P_i,
+ OPT_DATA_IN => OPT_DATA_IN_i,
+ OPT_DATA_OUT => OPT_DATA_OUT_i,
+ OPT_DATA_VALID_IN => OPT_DATA_VALID_IN_i,
+ OPT_DATA_VALID_OUT => OPT_DATA_VALID_OUT_i);
+ TRB_INST: trb_v2b_fpga
+ port map (
+ VIRT_CLK => VIRT_CLK_i,
+ VIRT_CLKB => VIRT_CLKB_i,
+ RESET_VIRT => '0',
+ DBAD => DBAD_i,
+ DGOOD => DGOOD_i,
+ DINT => DINT_i,
+ DWAIT => DWAIT_i,
+ A_RESERVED => A_RESERVED_i,
+ A_TEMP => A_TEMP_i,
+ B_RESERVED => B_RESERVED_i,
+ B_TEMP => B_TEMP_i,
+ C_RESERVED => C_RESERVED_i,
+ C_TEMP => C_TEMP_i,
+ D_RESERVED => D_RESERVED_i,
+ D_TEMP => D_TEMP_i,
+ VIR_TRIG => VIR_TRIG_i,
+ VIR_TRIGB => VIR_TRIGB_i,
+ A_TDC_ERROR => A_TDC_ERROR_i,
+ B_TDC_ERROR => B_TDC_ERROR_i,
+ C_TDC_ERROR => C_TDC_ERROR_i,
+ D_TDC_ERROR => D_TDC_ERROR_i,
+ A_TDC_POWERUP => A_TDC_POWERUP_i,
+ B_TDC_POWERUP => B_TDC_POWERUP_i,
+ C_TDC_POWERUP => C_TDC_POWERUP_i,
+ D_TDC_POWERUP => D_TDC_POWERUP_i,
+ TOKEN_IN => TOKEN_IN_i,
+ TOKEN_OUT => TOKEN_OUT_i,
+ C_TOKEN_OUT_TTL => C_TOKEN_OUT_TTL_i,
+ GET_DATA => GET_DATA_i,
+ A_DATA_READY => A_DATA_READY_i,
+ B_DATA_READY => B_DATA_READY_i,
+ C_DATA_READY => C_DATA_READY_i,
+ D_DATA_READY => D_DATA_READY_i,
+ REF_TDC_CLK => REF_TDC_CLK_i,
+ REF_TDC_CLKB => REF_TDC_CLKB_i,
+ A_TDC_BU_RESET => A_TDC_BU_RESET_i,
+ A_TDC_BU_RESETB => A_TDC_BU_RESETB_i,
+ A_TDC_EV_RESET => A_TDC_EV_RESET_i,
+ A_TDC_EV_RESETB => A_TDC_EV_RESETB_i,
+ B_TDC_BU_RESET => B_TDC_BU_RESET_i,
+ B_TDC_BU_RESETB => B_TDC_BU_RESETB_i,
+ B_TDC_EV_RESET => B_TDC_EV_RESET_i,
+ B_TDC_EV_RESETB => B_TDC_EV_RESETB_i,
+ C_TDC_BU_RESET => C_TDC_BU_RESET_i,
+ C_TDC_BU_RESETB => C_TDC_BU_RESETB_i,
+ C_TDC_EV_RESET => C_TDC_EV_RESET_i,
+ C_TDC_EV_RESETB => C_TDC_EV_RESETB_i,
+ D_TDC_BU_RESET => D_TDC_BU_RESET_i,
+ D_TDC_BU_RESETB => D_TDC_BU_RESETB_i,
+ D_TDC_EV_RESET => D_TDC_EV_RESET_i,
+ D_TDC_EV_RESETB => D_TDC_EV_RESETB_i,
+ TDC_OUT => TDC_OUT_i,
+ TDC_RESET => TDC_RESET_i,
+ A_TRIGGER => A_TRIGGER_i,
+ A_TRIGGERB => A_TRIGGERB_i,
+ B_TRIGGER => B_TRIGGER_i,
+ B_TRIGGERB => B_TRIGGERB_i,
+ C_TRIGGER => C_TRIGGER_i,
+ C_TRIGGERB => C_TRIGGERB_i,
+ D_TRIGGER => D_TRIGGER_i,
+ D_TRIGGERB => D_TRIGGERB_i,
+ FS_PB => FS_PB_i,
+ FS_PC => FS_PC_i,
+ ETRAX_IRQ => ETRAX_IRQ_i,
+ A_SCK => A_SCK_i,
+ A_SCKB => A_SCKB_i,
+ A_SDI => A_SDI_i,
+ A_SDIB => A_SDIB_i,
+ A_SDO => A_SDO_i,
+ A_SDOB => A_SDOB_i,
+ A_CSB => A_CSB_i,
+ A_CS => A_CS_i,
+ B_SCK => B_SCK_i,
+ B_SCKB => B_SCKB_i,
+ B_SDI => B_SDI_i,
+ B_SDIB => B_SDIB_i,
+ B_SDO => B_SDO_i,
+ B_SDOB => B_SDOB_i,
+ B_CSB => B_CSB_i,
+ B_CS => B_CS_i,
+ C_SCK => C_SCK_i,
+ C_SCKB => C_SCKB_i,
+ C_SDI => C_SDI_i,
+ C_SDIB => C_SDIB_i,
+ C_SDO => C_SDO_i,
+ C_SDOB => C_SDOB_i,
+ C_CSB => C_CSB_i,
+ C_CS => C_CS_i,
+ D_SCK => D_SCK_i,
+ D_SCKB => D_SCKB_i,
+ D_SDI => D_SDI_i,
+ D_SDIB => D_SDIB_i,
+ D_SDO => D_SDO_i,
+ D_SDOB => D_SDOB_i,
+ D_CSB => D_CSB_i,
+ D_CS => D_CS_i,
+ A_TEST1 => A_TEST1_i,
+ A_TEST1B => A_TEST1B_i,
+ A_TEST2 => A_TEST2_i,
+ A_TEST2B => A_TEST2B_i,
+ B_TEST1 => B_TEST1_i,
+ B_TEST1B => B_TEST1B_i,
+ B_TEST2 => B_TEST2_i,
+ B_TEST2B => B_TEST2B_i,
+ C_TEST1 => C_TEST1_i,
+ C_TEST1B => C_TEST1B_i,
+ C_TEST2 => C_TEST2_i,
+ C_TEST2B => C_TEST2B_i,
+ D_TEST1 => D_TEST1_i,
+ D_TEST1B => D_TEST1B_i,
+ D_TEST2 => D_TEST2_i,
+ D_TEST2B => D_TEST2B_i,
+ DSPADDR => DSPADDR_i,
+ DSPDAT => DSPDAT_i,
+ DSP_ACK => DSP_ACK_i,
+ DSP_BM => DSP_BM_i,
+ DSP_BMS => DSP_BMS_i,
+ DSP_BOFF => DSP_BOFF_i,
+ DSP_BRST => DSP_BRST_i,
+ DSP_HBG => DSP_HBG_i,
+ DSP_HBR => DSP_HBR_i,
+ DSP_IRQ => DSP_IRQ_i,
+ DSP_RD => DSP_RD_i,
+ DSP_RESET => DSP_RESET_i,
+ DSP_RESET_OUT => DSP_RESET_OUT_i,
+ DSP_WRH => DSP_WRH_i,
+ DSP_WRL => DSP_WRL_i,
+ VSD_A => VSD_A_i,
+ VSD_BA => VSD_BA_i,
+ VSD_CAS => VSD_CAS_i,
+ VSD_CKE => VSD_CKE_i,
+ VSD_CLOCK => VSD_CLOCK_i,
+ VSD_CSEH => VSD_CSEH_i,
+ VSD_CSEL => VSD_CSEL_i,
+ VSD_D => VSD_D_i,
+ VSD_DQML => VSD_DQML_i,
+ VSD_RAS => VSD_RAS_i,
+ VSD_WE => VSD_WE_i,
+ TLK_CLK => TLK_CLK_i,
+ TLK_ENABLE => TLK_ENABLE_i,
+ TLK_LCKREFN => TLK_LCKREFN_i,
+ TLK_LOOPEN => TLK_LOOPEN_i,
+ TLK_PRBSEN => TLK_PRBSEN_i,
+ TLK_RXD => OPT_DATA_OUT_i(31 downto 16), --TLK_RXD_i,
+ TLK_RX_CLK => TLK_RX_CLK_i,
+ TLK_RX_DV => OPT_DATA_VALID_OUT_i(1),--TLK_RX_DV_i,
+ TLK_RX_ER => '0',--TLK_RX_ER_i,
+ TLK_TXD => OPT_DATA_IN_i(31 downto 16),-- TLK_TXD_i,
+ TLK_TX_EN => OPT_DATA_VALID_IN_i(1),--TLK_TX_EN_i,
+ TLK_TX_ER => TLK_TX_ER_i,
+ SFP_LOS => SFP_LOS_i,
+ SFP_TX_DIS => SFP_TX_DIS_i,
+ SFP_TX_FAULT => SFP_TX_FAULT_i,
+ ADO_LV => ADO_LV_i,
+ ADO_TTL => open,--ADO_TTL_i,
+ VIRT_TCK => VIRT_TCK_i,
+ VIRT_TDI => VIRT_TDI_i,
+ VIRT_TDO => VIRT_TDO_i,
+ VIRT_TMS => VIRT_TMS_i,
+ VIRT_TRST => VIRT_TRST_i);
+ CTS_INST: cts
+ port map (
+ VIRT_CLK => VIRT_CLK_i,
+ VIRT_CLKB => VIRT_CLKB_i,
+ RESET_VIRT => '0',
+ DBAD => open,--DBAD_i,
+ DGOOD => open,--DGOOD_i,
+ DINT => open,
+ DWAIT => open,
+ FS_PB => FS_PB_CTS_i,
+ FS_PC => FS_PC_CTS_i,
+ ETRAX_IRQ => open,
+ DSPADDR => open,--DSPADDR_i,
+ DSPDAT => open,--DSPDAT_i,
+ DSP_ACK => '0',--DSP_ACK_i,
+ DSP_BM => open,--DSP_BM_i,
+ DSP_BMS => open,--DSP_BMS_i,
+ DSP_BOFF => open,--DSP_BOFF_i,
+ DSP_BRST => open,--DSP_BRST_i,
+ DSP_HBG => '0',--DSP_HBG_i,
+ DSP_HBR => open,--DSP_HBR_i,
+ DSP_IRQ => open,--DSP_IRQ_i,
+ DSP_RD => open,--DSP_RD_i,
+ DSP_RESET => open,--DSP_RESET_i,
+ DSP_RESET_OUT => '0',--open,--DSP_RESET_OUT_i,
+ DSP_WRH => open,--DSP_WRH_i,
+ DSP_WRL => open,--DSP_WRL_i,
+ VSD_A => open,--VSD_A_i,
+ VSD_BA => open,--VSD_BA_i,
+ VSD_CAS => open,--VSD_CAS_i,
+ VSD_CKE => open,--VSD_CKE_i,
+ VSD_CLOCK => open,--VSD_CLOCK_i,
+ VSD_CSEH => open,--VSD_CSEH_i,
+ VSD_CSEL => open,--VSD_CSEL_i,
+ VSD_D => open,--VSD_D_i,
+ VSD_DQML => open,--VSD_DQML_i,
+ VSD_RAS => open,--VSD_RAS_i,
+ VSD_WE => open,--VSD_WE_i,
+ TLK_CLK => TLK_CLK_i,
+ TLK_ENABLE => open,--TLK_ENABLE_i,
+ TLK_LCKREFN => open,--TLK_LCKREFN_i,
+ TLK_LOOPEN => open,--TLK_LOOPEN_i,
+ TLK_PRBSEN => open,--TLK_PRBSEN_i,
+ TLK_RXD => OPT_DATA_OUT_i(15 downto 0),--TLK_RXD_i,
+ TLK_RX_CLK => TLK_RX_CLK_i,
+ TLK_RX_DV => OPT_DATA_VALID_OUT_i(0),--TLK_RX_DV_i,
+ TLK_RX_ER => TLK_RX_ER_i,
+ TLK_TXD => OPT_DATA_IN_i(15 downto 0),--TLK_TXD_i,
+ TLK_TX_EN => OPT_DATA_VALID_IN_i(0),--TLK_TX_EN_i,
+ TLK_TX_ER => open,--TLK_TX_ER_i,
+ SFP_LOS => SFP_LOS_i,
+ SFP_TX_DIS => open,--SFP_TX_DIS_i,
+ SFP_TX_FAULT => '0',--SFP_TX_FAULT_i,
+ ADO_CLK1 => ADO_CLK1_i,
+ ADO_CLK2 => ADO_CLK2_i,
+ ADO_LV => (others => '0'),--ADO_LV_i,
+ ADO_TTL => ADO_TTL_i);
+ -----------------------------------------------------------------------------
+ -- --------------------------------------------------------------------------
+ -- CTS
+ -----------------------------------------------------------------------------
+ -----------------------------------------------------------------------------
+ -----------------------------------------------------------------------------
+ -- vulom to cts
+ -----------------------------------------------------------------------------
+
+ ADO_TTL_i(4) <= 'Z';
+
+ VULOM_SENDS_TRIGGER: process
+ variable i,y : integer;
+ begin
+ vulom_lvl1_tag <= (others => '0');
+ wait for 310 ns;
+
+ loop
+ y := 0;
+ ADO_TTL_i(3 downto 2) <= "01";
+ ADO_CLK2_i <= '1';
+ wait for 10 ns;
+ ADO_CLK2_i <= '0';
+ wait for 10 ns;
+ for i in 0 to 159 loop
+ ADO_TTL_i(3 downto 2) <= vulom_lvl1_tag (((y mod 15)+1) downto (y mod 15));
+ ADO_CLK2_i <= '1';
+ wait for 10 ns;
+ ADO_CLK2_i <= '0';
+ wait for 10 ns;
+ y := y + 2;
+ end loop; -- 40ns;
+ wait on VIRT_CLK_i until ADO_TTL_i(4) = '0';
+ vulom_lvl1_tag <= vulom_lvl1_tag + 1;
+ end loop;
+ end process VULOM_SENDS_TRIGGER;
+
+ clock_gclk : process
+ begin
+ VIRT_CLK_i <= '0';
+ VIRT_CLKB_i <= '1';
+ wait for 5 ns;
+ VIRT_CLKB_i <= '0';
+ VIRT_CLK_i <= '1';
+ wait for 5 ns;
+ end process;
+ clock_tlk_clk : process
+ begin
+ TLK_CLK_i <= '0';
+ wait for 5 ns;
+ TLK_CLK_i <= '1';
+ wait for 5 ns;
+ end process;
+ clock_tlk_rx_clk : process
+ begin
+ TLK_RX_CLK_i <= '0';
+ wait for 5 ns;
+ TLK_RX_CLK_i <= '1';
+ wait for 5 ns;
+ end process;
+ etrax_interface : process
+ begin
+
+ --reading DSP(dev number 1)
+ wait for 10 ns;
+ RESET_VIRT_i <= '0';
+
+ wait for 10 ns;
+ FS_PC_CTS_i(16) <= '1';
+ FS_PC_CTS_i(17) <= '1';
+ RESET_VIRT_i <= '1';
+ wait for 10 ns;
+
+ wait for 30 ns;
+ FS_PC_CTS_i(15 downto 0) <= x"0000";
+ FS_PC_CTS_i(16) <= '0';
+ FS_PC_CTS_i(17) <= '0';
+ wait on VIRT_CLK_i until FS_PB_CTS_i(16) = '0';
+ wait for 20 ns;
+ FS_PC_CTS_i(16) <= '1';
+ wait for 20 ns;
+ FS_PC_CTS_i(15) <= '1'; --read mode(1)
+ FS_PC_CTS_i(14 downto 8) <= (others => '0');
+ FS_PC_CTS_i(7 downto 0) <= x"00"; --device
+ FS_PC_CTS_i(16) <= '0';
+ FS_PC_CTS_i(17) <= '0';
+ wait for 20 ns;
+ FS_PC_CTS_i(15 downto 0) <= x"0000"; --address upper part
+ FS_PC_CTS_i(16) <= '1';
+ FS_PC_CTS_i(17) <= '0';
+ wait for 20 ns;
+ FS_PC_CTS_i(16) <= '0';
+ wait for 20 ns;
+ FS_PC_CTS_i(16) <= '1';
+ FS_PC_CTS_i(15 downto 0) <= x"0025"; --adrees lower part
+ FS_PC_CTS_i(16) <= '1';
+ FS_PC_CTS_i(17) <= '0';
+ wait for 20 ns;
+ FS_PC_CTS_i(16) <= '0';
+ wait on VIRT_CLK_i until FS_PB_CTS_i(16) = '1';
+ FS_PC_CTS_i(16) <= '1';
+ wait for 20 ns;
+ FS_PC_CTS_i(16) <= '0';
+ wait on VIRT_CLK_i until FS_PB_CTS_i(16) = '0';
+ FS_PC_CTS_i(16) <= '1';
+ wait for 20 ns;
+ FS_PC_CTS_i(16) <= '0';
+ wait on VIRT_CLK_i until FS_PB_CTS_i(16) = '1';
+ FS_PC_CTS_i(16) <= '1';
+ wait for 20 ns;
+ FS_PC_CTS_i(16) <= '0';
+ --writing DSP
+ wait for 20 ns;
+ FS_PC_CTS_i(16) <= '1';
+ wait for 20 ns;
+ FS_PC_CTS_i(15) <= '0'; --write mode
+ FS_PC_CTS_i(14 downto 8) <= (others => '0');
+ FS_PC_CTS_i(7 downto 0) <= x"00"; --device
+ FS_PC_CTS_i(16) <= '0';
+ FS_PC_CTS_i(17) <= '0';
+ wait for 20 ns;
+ FS_PC_CTS_i(15 downto 0) <= x"0000"; --address upper part
+ FS_PC_CTS_i(16) <= '1';
+ FS_PC_CTS_i(17) <= '0';
+ wait for 20 ns;
+ FS_PC_CTS_i(16) <= '0';
+ wait for 20 ns;
+ FS_PC_CTS_i(16) <= '1';
+ FS_PC_CTS_i(15 downto 0) <= x"0000"; --adrees lower part
+ FS_PC_CTS_i(16) <= '1';
+ FS_PC_CTS_i(17) <= '0';
+ wait for 20 ns;
+ FS_PC_CTS_i(16) <= '0';
+ wait for 20 ns;
+ FS_PC_CTS_i(15 downto 0) <= x"0000"; --data upper part
+ FS_PC_CTS_i(16) <= '1';
+ FS_PC_CTS_i(17) <= '0';
+ wait for 20 ns;
+ FS_PC_CTS_i(16) <= '0';
+ wait for 20 ns;
+ FS_PC_CTS_i(15 downto 0) <= x"0080"; --data lower part - 1 switch on
+ --internal generation of trigger
+ FS_PC_CTS_i(16) <= '1';
+ FS_PC_CTS_i(17) <= '0';
+ wait for 20 ns;
+ FS_PC_CTS_i(16) <= '0';
+ wait for 20 ns;
+ FS_PC_CTS_i(16) <= '1';
+ wait for 20 ns;
+ FS_PC_CTS_i(16) <= '0';
+-- wait on VIRT_CLK_i until FS_PB_CTS_i(16)= '1';
+ loop
+ wait on VIRT_CLK_i until FS_PB_CTS_i(16) = '1';
+ FS_PC_CTS_i(17) <= '1';
+ wait for 100 ns;
+ FS_PC_CTS_i(17) <= '0';
+ wait for 100 ns;
+ end loop;
+ wait; -- will wait forever
+ end process;
+
+-------------------------------------------------------------------------------
+-- trb
+-------------------------------------------------------------------------------
+ etrax_intf : process
+ begin
+
+ --reading DSP(dev number 1)
+ wait for 10 ns;
+ RESET_VIRT_i <= '0';
+
+ wait for 10 ns;
+ FS_PC_i(16) <= '1';
+ FS_PC_i(17) <= '1';
+ RESET_VIRT_i <= '1';
+ wait for 10 ns;
+
+ wait for 30 ns;
+ -- FS_PC_i(16) <= '0';
+ -- FS_PC_i(17) <= '0';
+ -- wait for 10 ns;
+ FS_PC_i(15 downto 0) <= x"0000";
+ FS_PC_i(16) <= '0';
+ FS_PC_i(17) <= '0';
+ wait on VIRT_CLK_i until FS_PB_i(16) = '0';
+ wait for 20 ns;
+ FS_PC_i(16) <= '1';
+ wait for 20 ns;
+ FS_PC_i(15) <= '1'; --read mode(1)
+ FS_PC_i(14 downto 8) <= (others => '0');
+ FS_PC_i(7 downto 0) <= x"00"; --device
+ FS_PC_i(16) <= '0';
+ FS_PC_i(17) <= '0';
+ wait for 20 ns;
+ FS_PC_i(15 downto 0) <= x"0000"; --address upper part
+ FS_PC_i(16) <= '1';
+ FS_PC_i(17) <= '0';
+ wait for 20 ns;
+ FS_PC_i(16) <= '0';
+ wait for 20 ns;
+ FS_PC_i(16) <= '1';
+ FS_PC_i(15 downto 0) <= x"0025"; --adrees lower part
+ FS_PC_i(16) <= '1';
+ FS_PC_i(17) <= '0';
+ wait for 20 ns;
+ FS_PC_i(16) <= '0';
+ wait on VIRT_CLK_i until FS_PB_i(16) = '1';
+ FS_PC_i(16) <= '1';
+ wait for 20 ns;
+ FS_PC_i(16) <= '0';
+ wait on VIRT_CLK_i until FS_PB_i(16) = '0';
+ FS_PC_i(16) <= '1';
+ wait for 20 ns;
+ FS_PC_i(16) <= '0';
+ wait on VIRT_CLK_i until FS_PB_i(16) = '1';
+ FS_PC_i(16) <= '1';
+ wait for 20 ns;
+ FS_PC_i(16) <= '0';
+ --writing DSP
+ wait for 20 ns;
+ FS_PC_i(16) <= '1';
+ test_synch_00 <= '1';
+ wait for 20 ns;
+ FS_PC_i(15) <= '0'; --write mode
+ FS_PC_i(14 downto 8) <= (others => '0');
+ FS_PC_i(7 downto 0) <= x"00"; --device
+ FS_PC_i(16) <= '0';
+ FS_PC_i(17) <= '0';
+ wait for 20 ns;
+ FS_PC_i(15 downto 0) <= x"0000"; --address upper part
+ FS_PC_i(16) <= '1';
+ FS_PC_i(17) <= '0';
+ wait for 20 ns;
+ FS_PC_i(16) <= '0';
+ wait for 20 ns;
+ FS_PC_i(16) <= '1';
+ FS_PC_i(15 downto 0) <= x"0006"; --adrees lower part
+ FS_PC_i(16) <= '1';
+ FS_PC_i(17) <= '0';
+ wait for 20 ns;
+ FS_PC_i(16) <= '0';
+ wait for 20 ns;
+ FS_PC_i(15 downto 0) <= x"0004"; --data upper part
+ FS_PC_i(16) <= '1';
+ FS_PC_i(17) <= '0';
+ wait for 20 ns;
+ FS_PC_i(16) <= '0';
+ wait for 20 ns;
+ FS_PC_i(15 downto 0) <= x"0000"; --data lower part - 1 switch on
+ --internal generation of trigger
+ FS_PC_i(16) <= '1';
+ FS_PC_i(17) <= '0';
+ wait for 20 ns;
+ FS_PC_i(16) <= '0';
+ wait for 20 ns;
+ test_synch_00 <= '0';
+ FS_PC_i(16) <= '1';
+ wait for 20 ns;
+ FS_PC_i(16) <= '0';
+ FS_PC_i(15 downto 0) <= (others => 'Z');
+-- wait on VIRT_CLK until FS_PB_i(16)= '1';
+ loop
+ wait on VIRT_CLK_i until FS_PB_i(16) = '1';
+ FS_PC_i(17) <= '1';
+ wait for 50 ns;
+ FS_PC_i(17) <= '0';
+ wait for 50 ns;
+ end loop;
+
+ wait; -- will wait forever
+ end process;
+
+ -----------------------------------------------------------------------
+ -- TDC
+ -----------------------------------------------------------------------
+ clock_tdcclk : process
+ begin
+ wait for 12 ns;
+ loop
+ REF_TDC_CLK_i <= '0';
+ REF_TDC_CLKB_i <= '1';
+ wait for 12.5 ns;
+ REF_TDC_CLK_i <= '1';
+ REF_TDC_CLKB_i <= '0';
+ wait for 12.5 ns;
+ end loop;
+ end process;
+ trigger_lvl1 : process
+ begin
+-- ADO_TTL(7) <= '0';
+ A_DATA_READY_i <= '0';
+ B_DATA_READY_i <= '0';
+ C_DATA_READY_i <= '0';
+ D_DATA_READY_i <= '0';
+ TOKEN_IN_i <= '0';
+ TDC_OUT_i <= x"bedebabe";
+-- A_TEMP <= '0';
+-- wait for 50 ns;
+-- A_TEMP <= '1';
+-- wait for 10 ns;
+-- A_TEMP <= '0';
+-- wait for 10 ns;
+ wait on REF_TDC_CLK_i until TOKEN_OUT_i = '1';
+ wait on REF_TDC_CLK_i until TOKEN_OUT_i = '0';
+ wait for 10 ns;
+-- ADO_TTL(7) <= '0';
+ A_DATA_READY_i <= '1';
+ wait for 50 ns;
+ A_DATA_READY_i <= '0';
+ B_DATA_READY_i <= '1';
+ wait for 50 ns;
+ B_DATA_READY_i <= '0';
+ C_DATA_READY_i <= '1';
+ wait for 50 ns;
+-- ADO_TTL(7) <= '0';
+ C_DATA_READY_i <= '0';
+ D_DATA_READY_i <= '1';
+ wait for 50 ns;
+ D_DATA_READY_i <= '0';
+ wait for 0 ns;
+-- ADO_TTL(6) <= '1';
+ TOKEN_IN_i <= '1';
+ wait for 25 ns;
+-- ADO_TTL(6) <= '0';
+ TOKEN_IN_i <= '0';
+ -- wait on REF_TDC_CLK until DBAD = '0';
+ end process;
+-- trigger_lvl2 : process
+-- begin
+-- B_TEMP <= '0';
+-- C_TEMP <= '0';
+-- wait until DBAD = '1';
+-- wait until DBAD = '0';
+-- wait for 30 ns;
+-- wait on VIRT_CLK until DGOOD = '0';
+-- B_TEMP <= '0';
+-- C_TEMP <= '1';
+-- wait for 30 ns;
+-- end process;
+
+end system;
jspc29 / trbv2.git / commitdiff