*** empty log message ***

diff --git a/base/trb3_periph.lpf b/base/trb3_periph.lpf
index 4276f177d1072ad3eb3402c5044add40924bd155..92a7d5235bccbb5b5c1e453680355f7574e7fd94 100644 (file)
--- a/base/trb3_periph.lpf
+++ b/base/trb3_periph.lpf
@@ -7,10 +7,11 @@ BLOCK RD_DURING_WR_PATHS ;
 #################################################################
 
   SYSCONFIG MCCLK_FREQ = 2.5;
+
   FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz;
   FREQUENCY PORT CLK_PCLK_LEFT  200 MHz;
   FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz;
-  FREQUENCY PORT CLK_GPLL_LEFT  100 MHz;
+  FREQUENCY PORT CLK_GPLL_LEFT  125 MHz;
 
 #################################################################
 # Clock I/O
@@ -33,8 +34,9 @@ IOBUF GROUP  "CLK_group" IO_TYPE=LVDS25;
 #Trigger from fan-out
 LOCATE COMP  "TRIGGER_LEFT"   SITE "V3";
 LOCATE COMP  "TRIGGER_RIGHT"   SITE "N24";
-IOBUF  PORT  "TRIGGER_RIGHT" IO_TYPE=LVDS25; 
-IOBUF  PORT  "TRIGGER_LEFT"  IO_TYPE=LVDS25;
+IOBUF  PORT  "TRIGGER_RIGHT" IO_TYPE=LVDS25 ; 
+IOBUF  PORT  "TRIGGER_LEFT"  IO_TYPE=LVDS25 ;
+
 
 
 

diff --git a/base/trb3_periph.vhd b/base/trb3_periph.vhd
index 8986c1747f9622814f63e89cb3c0e40629add5a0..72dccf8be75098d2f9ba4119cd0918107b8deebe 100644 (file)
--- a/base/trb3_periph.vhd
+++ b/base/trb3_periph.vhd
@@ -139,7 +139,12 @@ architecture trb3_periph_arch of trb3_periph is
   signal trg_code_i            : std_logic_vector(7 downto 0);
   signal trg_information_i     : std_logic_vector(23 downto 0);
   signal trg_int_number_i      : std_logic_vector(15 downto 0);
-
+  signal trg_multiple_trg_i    : std_logic;
+  signal trg_timeout_detected_i: std_logic;
+  signal trg_spurious_trg_i    : std_logic;
+  signal trg_missing_tmg_trg_i : std_logic;
+  signal trg_spike_detected_i  : std_logic;
+  
   --Data channel
   signal fee_trg_release_i    : std_logic;
   signal fee_trg_statusbits_i : std_logic_vector(31 downto 0);
@@ -248,6 +253,7 @@ begin
 ---------------------------------------------------------------------------
 -- Clock Handling
 ---------------------------------------------------------------------------
+
   THE_MAIN_PLL : pll_in200_out100
     port map(
       CLK   => CLK_GPLL_RIGHT,
@@ -353,6 +359,13 @@ begin
       LVL1_TRG_INFORMATION_OUT => trg_information_i,
       LVL1_INT_TRG_NUMBER_OUT  => trg_int_number_i,
 
+      --Information about trigger handler errors
+      TRG_MULTIPLE_TRG_OUT         => trg_multiple_trg_i,
+      TRG_TIMEOUT_DETECTED_OUT     => trg_timeout_detected_i,
+      TRG_SPURIOUS_TRG_OUT         => trg_spurious_trg_i,
+      TRG_MISSING_TMG_TRG_OUT      => trg_missing_tmg_trg_i,
+      TRG_SPIKE_DETECTED_OUT       => trg_spike_detected_i,
+      
       --Response from FEE
       FEE_TRG_RELEASE_IN(0)       => fee_trg_release_i,
       FEE_TRG_STATUSBITS_IN       => fee_trg_statusbits_i,

diff --git a/base/trb3_periph_ada.lpf b/base/trb3_periph_ada.lpf
index 073eb801947eb02d10baac0bc51a961197bd9800..f9188791890a22b3a410214709094a9cba94327b 100644 (file)
--- a/base/trb3_periph_ada.lpf
+++ b/base/trb3_periph_ada.lpf
@@ -105,7 +105,7 @@ LOCATE COMP  "CLK_GPLL_RIGHT"       SITE "W1";
 LOCATE COMP  "CLK_GPLL_LEFT"        SITE "U25";
 
 DEFINE PORT GROUP "CLK_group" "CLK*" ;
-IOBUF GROUP  "CLK_group" IO_TYPE=LVDS25 DIFFRESISTOR=100;
+IOBUF GROUP  "CLK_group" IO_TYPE=LVDS25 ;
 
 
 #################################################################
@@ -115,8 +115,8 @@ IOBUF GROUP  "CLK_group" IO_TYPE=LVDS25 DIFFRESISTOR=100;
 #Trigger from fan-out
 LOCATE COMP  "TRIGGER_LEFT"   SITE "V3";
 LOCATE COMP  "TRIGGER_RIGHT"   SITE "N24";
-IOBUF  PORT  "TRIGGER_RIGHT" IO_TYPE=LVDS25 DIFFRESISTOR=100 ; 
-IOBUF  PORT  "TRIGGER_LEFT"  IO_TYPE=LVDS25 DIFFRESISTOR=100;
+IOBUF  PORT  "TRIGGER_RIGHT" IO_TYPE=LVDS25; 
+IOBUF  PORT  "TRIGGER_LEFT"  IO_TYPE=LVDS25;
 
 
 

diff --git a/base/trb3_periph_constraints.lpf b/base/trb3_periph_constraints.lpf
index aa9e43bb116d0447c5a20e59345e6e8082e68551..9441786b01f7b4740cfba46762c51dab58eb586e 100644 (file)
--- a/base/trb3_periph_constraints.lpf
+++ b/base/trb3_periph_constraints.lpf
@@ -7,11 +7,11 @@ BLOCK RD_DURING_WR_PATHS ;
 #################################################################
 
   SYSCONFIG MCCLK_FREQ = 2.5;
+
   FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz;
   FREQUENCY PORT CLK_PCLK_LEFT  200 MHz;
   FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz;
-  FREQUENCY PORT CLK_GPLL_LEFT  100 MHz;
-
+  FREQUENCY PORT CLK_GPLL_LEFT  125 MHz;
   
 #################################################################
 # Reset Nets