]> jspc29.x-matter.uni-frankfurt.de Git - trb3.git/commitdiff
nxyter update
authorLudwig Maier <lmaier@crius.e12.ph.tum.de>
Mon, 26 May 2014 18:37:47 +0000 (20:37 +0200)
committerLudwig Maier <lmaier@crius.e12.ph.tum.de>
Mon, 26 May 2014 18:37:47 +0000 (20:37 +0200)
nxyter/cores/ram_dp_512x40.ipx [new file with mode: 0644]
nxyter/cores/ram_dp_512x40.lpc [new file with mode: 0644]
nxyter/cores/ram_dp_512x40.vhd [new file with mode: 0644]
nxyter/trb3_periph_multi.p2t

diff --git a/nxyter/cores/ram_dp_512x40.ipx b/nxyter/cores/ram_dp_512x40.ipx
new file mode 100644 (file)
index 0000000..163fa87
--- /dev/null
@@ -0,0 +1,10 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="ram_dp_512x40" module="RAM_DP" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2014 05 20 16:10:46.289" version="6.1" type="Module" synthesis="" source_format="VHDL">
+  <Package>
+               <File name="" type="mem" modified="2014 05 20 16:10:46.000"/>
+               <File name="ram_dp_512x40.lpc" type="lpc" modified="2014 05 20 16:10:44.000"/>
+               <File name="ram_dp_512x40.vhd" type="top_level_vhdl" modified="2014 05 20 16:10:44.000"/>
+               <File name="ram_dp_512x40_tmpl.vhd" type="template_vhdl" modified="2014 05 20 16:10:44.000"/>
+               <File name="tb_ram_dp_512x40_tmpl.vhd" type="testbench_vhdl" modified="2014 05 20 16:10:44.000"/>
+  </Package>
+</DiamondModule>
diff --git a/nxyter/cores/ram_dp_512x40.lpc b/nxyter/cores/ram_dp_512x40.lpc
new file mode 100644 (file)
index 0000000..5e87568
--- /dev/null
@@ -0,0 +1,53 @@
+[Device]
+Family=latticeecp3
+PartType=LFE3-150EA
+PartName=LFE3-150EA-8FN672C
+SpeedGrade=8
+Package=FPBGA672
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=RAM_DP
+CoreRevision=6.1
+ModuleName=ram_dp_512x40
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=05/20/2014
+Time=16:10:44
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+RAddress=512
+RData=40
+WAddress=512
+WData=40
+enByte=0
+ByteSize=9
+adPipeline=0
+inPipeline=0
+outPipeline=0
+MOR=0
+InData=Registered
+AdControl=Registered
+MemFile=
+MemFormat=bin
+Reset=Sync
+GSR=Enabled
+Pad=0
+EnECC=0
+Optimization=Speed
+EnSleep=ENABLED
+Pipeline=0
+
+[FilesGenerated]
+=mem
diff --git a/nxyter/cores/ram_dp_512x40.vhd b/nxyter/cores/ram_dp_512x40.vhd
new file mode 100644 (file)
index 0000000..66d80e8
--- /dev/null
@@ -0,0 +1,201 @@
+-- VHDL netlist generated by SCUBA Diamond_2.1_Production (100)
+-- Module  Version: 6.1
+--/usr/local/opt/lattice_diamond/diamond/2.1/ispfpga/bin/lin64/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type bram -wp 10 -rp 0011 -rdata_width 40 -data_width 40 -num_rows 512 -cascade -1 -e 
+
+-- Tue May 20 16:10:44 2014
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp3;
+use ecp3.components.all;
+-- synopsys translate_on
+
+entity ram_dp_512x40 is
+    port (
+        WrAddress: in  std_logic_vector(8 downto 0); 
+        RdAddress: in  std_logic_vector(8 downto 0); 
+        Data: in  std_logic_vector(39 downto 0); 
+        WE: in  std_logic; 
+        RdClock: in  std_logic; 
+        RdClockEn: in  std_logic; 
+        Reset: in  std_logic; 
+        WrClock: in  std_logic; 
+        WrClockEn: in  std_logic; 
+        Q: out  std_logic_vector(39 downto 0));
+end ram_dp_512x40;
+
+architecture Structure of ram_dp_512x40 is
+
+    -- internal signal declarations
+    signal scuba_vhi: std_logic;
+    signal scuba_vlo: std_logic;
+
+    -- local component declarations
+    component VHI
+        port (Z: out  std_logic);
+    end component;
+    component VLO
+        port (Z: out  std_logic);
+    end component;
+    component PDPW16KC
+        generic (GSR : in String; CSDECODE_R : in String; 
+                CSDECODE_W : in String; REGMODE : in String; 
+                DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer);
+        port (DI0: in  std_logic; DI1: in  std_logic; DI2: in  std_logic; 
+            DI3: in  std_logic; DI4: in  std_logic; DI5: in  std_logic; 
+            DI6: in  std_logic; DI7: in  std_logic; DI8: in  std_logic; 
+            DI9: in  std_logic; DI10: in  std_logic; DI11: in  std_logic; 
+            DI12: in  std_logic; DI13: in  std_logic; 
+            DI14: in  std_logic; DI15: in  std_logic; 
+            DI16: in  std_logic; DI17: in  std_logic; 
+            DI18: in  std_logic; DI19: in  std_logic; 
+            DI20: in  std_logic; DI21: in  std_logic; 
+            DI22: in  std_logic; DI23: in  std_logic; 
+            DI24: in  std_logic; DI25: in  std_logic; 
+            DI26: in  std_logic; DI27: in  std_logic; 
+            DI28: in  std_logic; DI29: in  std_logic; 
+            DI30: in  std_logic; DI31: in  std_logic; 
+            DI32: in  std_logic; DI33: in  std_logic; 
+            DI34: in  std_logic; DI35: in  std_logic; 
+            ADW0: in  std_logic; ADW1: in  std_logic; 
+            ADW2: in  std_logic; ADW3: in  std_logic; 
+            ADW4: in  std_logic; ADW5: in  std_logic; 
+            ADW6: in  std_logic; ADW7: in  std_logic; 
+            ADW8: in  std_logic; BE0: in  std_logic; BE1: in  std_logic; 
+            BE2: in  std_logic; BE3: in  std_logic; CEW: in  std_logic; 
+            CLKW: in  std_logic; CSW0: in  std_logic; 
+            CSW1: in  std_logic; CSW2: in  std_logic; 
+            ADR0: in  std_logic; ADR1: in  std_logic; 
+            ADR2: in  std_logic; ADR3: in  std_logic; 
+            ADR4: in  std_logic; ADR5: in  std_logic; 
+            ADR6: in  std_logic; ADR7: in  std_logic; 
+            ADR8: in  std_logic; ADR9: in  std_logic; 
+            ADR10: in  std_logic; ADR11: in  std_logic; 
+            ADR12: in  std_logic; ADR13: in  std_logic; 
+            CER: in  std_logic; CLKR: in  std_logic; CSR0: in  std_logic; 
+            CSR1: in  std_logic; CSR2: in  std_logic; RST: in  std_logic; 
+            DO0: out  std_logic; DO1: out  std_logic; 
+            DO2: out  std_logic; DO3: out  std_logic; 
+            DO4: out  std_logic; DO5: out  std_logic; 
+            DO6: out  std_logic; DO7: out  std_logic; 
+            DO8: out  std_logic; DO9: out  std_logic; 
+            DO10: out  std_logic; DO11: out  std_logic; 
+            DO12: out  std_logic; DO13: out  std_logic; 
+            DO14: out  std_logic; DO15: out  std_logic; 
+            DO16: out  std_logic; DO17: out  std_logic; 
+            DO18: out  std_logic; DO19: out  std_logic; 
+            DO20: out  std_logic; DO21: out  std_logic; 
+            DO22: out  std_logic; DO23: out  std_logic; 
+            DO24: out  std_logic; DO25: out  std_logic; 
+            DO26: out  std_logic; DO27: out  std_logic; 
+            DO28: out  std_logic; DO29: out  std_logic; 
+            DO30: out  std_logic; DO31: out  std_logic; 
+            DO32: out  std_logic; DO33: out  std_logic; 
+            DO34: out  std_logic; DO35: out  std_logic);
+    end component;
+    attribute MEM_LPC_FILE : string; 
+    attribute MEM_INIT_FILE : string; 
+    attribute RESETMODE : string; 
+    attribute MEM_LPC_FILE of ram_dp_512x40_0_0_1 : label is "ram_dp_512x40.lpc";
+    attribute MEM_INIT_FILE of ram_dp_512x40_0_0_1 : label is "";
+    attribute RESETMODE of ram_dp_512x40_0_0_1 : label is "SYNC";
+    attribute MEM_LPC_FILE of ram_dp_512x40_0_1_0 : label is "ram_dp_512x40.lpc";
+    attribute MEM_INIT_FILE of ram_dp_512x40_0_1_0 : label is "";
+    attribute RESETMODE of ram_dp_512x40_0_1_0 : label is "SYNC";
+    attribute NGD_DRC_MASK : integer;
+    attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+    -- component instantiation statements
+    ram_dp_512x40_0_0_1: PDPW16KC
+        generic map (CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "DISABLED", 
+        REGMODE=> "NOREG", DATA_WIDTH_R=>  36, DATA_WIDTH_W=>  36)
+        port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), 
+            DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7), 
+            DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11), 
+            DI12=>Data(12), DI13=>Data(13), DI14=>Data(14), 
+            DI15=>Data(15), DI16=>Data(16), DI17=>Data(17), 
+            DI18=>Data(18), DI19=>Data(19), DI20=>Data(20), 
+            DI21=>Data(21), DI22=>Data(22), DI23=>Data(23), 
+            DI24=>Data(24), DI25=>Data(25), DI26=>Data(26), 
+            DI27=>Data(27), DI28=>Data(28), DI29=>Data(29), 
+            DI30=>Data(30), DI31=>Data(31), DI32=>Data(32), 
+            DI33=>Data(33), DI34=>Data(34), DI35=>Data(35), 
+            ADW0=>WrAddress(0), ADW1=>WrAddress(1), ADW2=>WrAddress(2), 
+            ADW3=>WrAddress(3), ADW4=>WrAddress(4), ADW5=>WrAddress(5), 
+            ADW6=>WrAddress(6), ADW7=>WrAddress(7), ADW8=>WrAddress(8), 
+            BE0=>scuba_vhi, BE1=>scuba_vhi, BE2=>scuba_vhi, 
+            BE3=>scuba_vhi, CEW=>WrClockEn, CLKW=>WrClock, CSW0=>WE, 
+            CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo, 
+            ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>scuba_vlo, 
+            ADR4=>scuba_vlo, ADR5=>RdAddress(0), ADR6=>RdAddress(1), 
+            ADR7=>RdAddress(2), ADR8=>RdAddress(3), ADR9=>RdAddress(4), 
+            ADR10=>RdAddress(5), ADR11=>RdAddress(6), 
+            ADR12=>RdAddress(7), ADR13=>RdAddress(8), CER=>RdClockEn, 
+            CLKR=>RdClock, CSR0=>scuba_vlo, CSR1=>scuba_vlo, 
+            CSR2=>scuba_vlo, RST=>Reset, DO0=>Q(18), DO1=>Q(19), 
+            DO2=>Q(20), DO3=>Q(21), DO4=>Q(22), DO5=>Q(23), DO6=>Q(24), 
+            DO7=>Q(25), DO8=>Q(26), DO9=>Q(27), DO10=>Q(28), DO11=>Q(29), 
+            DO12=>Q(30), DO13=>Q(31), DO14=>Q(32), DO15=>Q(33), 
+            DO16=>Q(34), DO17=>Q(35), DO18=>Q(0), DO19=>Q(1), DO20=>Q(2), 
+            DO21=>Q(3), DO22=>Q(4), DO23=>Q(5), DO24=>Q(6), DO25=>Q(7), 
+            DO26=>Q(8), DO27=>Q(9), DO28=>Q(10), DO29=>Q(11), 
+            DO30=>Q(12), DO31=>Q(13), DO32=>Q(14), DO33=>Q(15), 
+            DO34=>Q(16), DO35=>Q(17));
+
+    scuba_vhi_inst: VHI
+        port map (Z=>scuba_vhi);
+
+    scuba_vlo_inst: VLO
+        port map (Z=>scuba_vlo);
+
+    ram_dp_512x40_0_1_0: PDPW16KC
+        generic map (CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "DISABLED", 
+        REGMODE=> "NOREG", DATA_WIDTH_R=>  36, DATA_WIDTH_W=>  36)
+        port map (DI0=>Data(36), DI1=>Data(37), DI2=>Data(38), 
+            DI3=>Data(39), DI4=>scuba_vlo, DI5=>scuba_vlo, 
+            DI6=>scuba_vlo, DI7=>scuba_vlo, DI8=>scuba_vlo, 
+            DI9=>scuba_vlo, DI10=>scuba_vlo, DI11=>scuba_vlo, 
+            DI12=>scuba_vlo, DI13=>scuba_vlo, DI14=>scuba_vlo, 
+            DI15=>scuba_vlo, DI16=>scuba_vlo, DI17=>scuba_vlo, 
+            DI18=>scuba_vlo, DI19=>scuba_vlo, DI20=>scuba_vlo, 
+            DI21=>scuba_vlo, DI22=>scuba_vlo, DI23=>scuba_vlo, 
+            DI24=>scuba_vlo, DI25=>scuba_vlo, DI26=>scuba_vlo, 
+            DI27=>scuba_vlo, DI28=>scuba_vlo, DI29=>scuba_vlo, 
+            DI30=>scuba_vlo, DI31=>scuba_vlo, DI32=>scuba_vlo, 
+            DI33=>scuba_vlo, DI34=>scuba_vlo, DI35=>scuba_vlo, 
+            ADW0=>WrAddress(0), ADW1=>WrAddress(1), ADW2=>WrAddress(2), 
+            ADW3=>WrAddress(3), ADW4=>WrAddress(4), ADW5=>WrAddress(5), 
+            ADW6=>WrAddress(6), ADW7=>WrAddress(7), ADW8=>WrAddress(8), 
+            BE0=>scuba_vhi, BE1=>scuba_vhi, BE2=>scuba_vhi, 
+            BE3=>scuba_vhi, CEW=>WrClockEn, CLKW=>WrClock, CSW0=>WE, 
+            CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo, 
+            ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>scuba_vlo, 
+            ADR4=>scuba_vlo, ADR5=>RdAddress(0), ADR6=>RdAddress(1), 
+            ADR7=>RdAddress(2), ADR8=>RdAddress(3), ADR9=>RdAddress(4), 
+            ADR10=>RdAddress(5), ADR11=>RdAddress(6), 
+            ADR12=>RdAddress(7), ADR13=>RdAddress(8), CER=>RdClockEn, 
+            CLKR=>RdClock, CSR0=>scuba_vlo, CSR1=>scuba_vlo, 
+            CSR2=>scuba_vlo, RST=>Reset, DO0=>open, DO1=>open, DO2=>open, 
+            DO3=>open, DO4=>open, DO5=>open, DO6=>open, DO7=>open, 
+            DO8=>open, DO9=>open, DO10=>open, DO11=>open, DO12=>open, 
+            DO13=>open, DO14=>open, DO15=>open, DO16=>open, DO17=>open, 
+            DO18=>Q(36), DO19=>Q(37), DO20=>Q(38), DO21=>Q(39), 
+            DO22=>open, DO23=>open, DO24=>open, DO25=>open, DO26=>open, 
+            DO27=>open, DO28=>open, DO29=>open, DO30=>open, DO31=>open, 
+            DO32=>open, DO33=>open, DO34=>open, DO35=>open);
+
+end Structure;
+
+-- synopsys translate_off
+library ecp3;
+configuration Structure_CON of ram_dp_512x40 is
+    for Structure
+        for all:VHI use entity ecp3.VHI(V); end for;
+        for all:VLO use entity ecp3.VLO(V); end for;
+        for all:PDPW16KC use entity ecp3.PDPW16KC(V); end for;
+    end for;
+end Structure_CON;
+
+-- synopsys translate_on
index 9b397c237fe62421ec58764bddda6c82f25fa36d..d55c38c1332e4f7de48d0b86e272eacfeab2498a 100644 (file)
@@ -1,7 +1,7 @@
 -w 
 -i 2
 -l 5
--n 8
+-n 28
 -t 50
 -s 1
 -c 1