-- VHDL netlist generated by SCUBA ispLever_v72_SP2_Build (23)
-- Module Version: 4.6
---/storage120/lattice/isplever7.2/isptools/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -depth 512 -width 72 -depth 512 -regout -no_enable -pe 0 -pf 0 -fill -e
+--/storage120/lattice/isplever7.2/isptools/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -depth 512 -width 72 -depth 512 -regout -no_enable -pe 0 -pf 0 -fill -e
-- Fri Sep 18 16:09:46 2009
entity fifo_512depth_72width_reg_out is
port (
- Data: in std_logic_vector(71 downto 0);
- Clock: in std_logic;
- WrEn: in std_logic;
- RdEn: in std_logic;
- Reset: in std_logic;
- AmEmptyThresh: in std_logic_vector(8 downto 0);
- AmFullThresh: in std_logic_vector(8 downto 0);
- Q: out std_logic_vector(71 downto 0);
- WCNT: out std_logic_vector(9 downto 0);
- Empty: out std_logic;
- Full: out std_logic;
- AlmostEmpty: out std_logic;
+ Data: in std_logic_vector(71 downto 0);
+ Clock: in std_logic;
+ WrEn: in std_logic;
+ RdEn: in std_logic;
+ Reset: in std_logic;
+ AmEmptyThresh: in std_logic_vector(8 downto 0);
+ AmFullThresh: in std_logic_vector(8 downto 0);
+ Q: out std_logic_vector(71 downto 0);
+ WCNT: out std_logic_vector(9 downto 0);
+ Empty: out std_logic;
+ Full: out std_logic;
+ AlmostEmpty: out std_logic;
AlmostFull: out std_logic);
end fifo_512depth_72width_reg_out;
-- local component declarations
component AGEB2
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
B1: in std_logic; CI: in std_logic; GE: out std_logic);
end component;
component ALEB2
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
B1: in std_logic; CI: in std_logic; LE: out std_logic);
end component;
component AND2
port (A: in std_logic; B: in std_logic; Z: out std_logic);
end component;
component CU2
- port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
+ port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
CO: out std_logic; NC0: out std_logic; NC1: out std_logic);
end component;
component CB2
- port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
- CON: in std_logic; CO: out std_logic; NC0: out std_logic;
+ port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
+ CON: in std_logic; CO: out std_logic; NC0: out std_logic;
NC1: out std_logic);
end component;
component FADD2B
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; COUT: out std_logic;
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; CI: in std_logic; COUT: out std_logic;
S0: out std_logic; S1: out std_logic);
end component;
component FSUB2B
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; BI: in std_logic; BOUT: out std_logic;
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; BI: in std_logic; BOUT: out std_logic;
S0: out std_logic; S1: out std_logic);
end component;
component FD1P3BX
-- synopsys translate_off
generic (GSR : in String);
-- synopsys translate_on
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
+ port (D: in std_logic; SP: in std_logic; CK: in std_logic;
PD: in std_logic; Q: out std_logic);
end component;
component FD1P3DX
-- synopsys translate_off
generic (GSR : in String);
-- synopsys translate_on
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
+ port (D: in std_logic; SP: in std_logic; CK: in std_logic;
CD: in std_logic; Q: out std_logic);
end component;
component FD1S3BX
-- synopsys translate_off
generic (GSR : in String);
-- synopsys translate_on
- port (D: in std_logic; CK: in std_logic; PD: in std_logic;
+ port (D: in std_logic; CK: in std_logic; PD: in std_logic;
Q: out std_logic);
end component;
component FD1S3DX
-- synopsys translate_off
generic (GSR : in String);
-- synopsys translate_on
- port (D: in std_logic; CK: in std_logic; CD: in std_logic;
+ port (D: in std_logic; CK: in std_logic; CD: in std_logic;
Q: out std_logic);
end component;
component INV
-- synopsys translate_off
generic (initval : in String);
-- synopsys translate_on
- port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
+ port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
AD0: in std_logic; DO0: out std_logic);
end component;
component VHI
end component;
component PDPW16KB
-- synopsys translate_off
- generic (CSDECODE_R : in std_logic_vector(2 downto 0);
- CSDECODE_W : in std_logic_vector(2 downto 0);
- GSR : in String; RESETMODE : in String;
- REGMODE : in String; DATA_WIDTH_R : in Integer;
+ generic (CSDECODE_R : in std_logic_vector(2 downto 0);
+ CSDECODE_W : in std_logic_vector(2 downto 0);
+ GSR : in String; RESETMODE : in String;
+ REGMODE : in String; DATA_WIDTH_R : in Integer;
DATA_WIDTH_W : in Integer);
-- synopsys translate_on
- port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic;
- DI3: in std_logic; DI4: in std_logic; DI5: in std_logic;
- DI6: in std_logic; DI7: in std_logic; DI8: in std_logic;
- DI9: in std_logic; DI10: in std_logic; DI11: in std_logic;
- DI12: in std_logic; DI13: in std_logic;
- DI14: in std_logic; DI15: in std_logic;
- DI16: in std_logic; DI17: in std_logic;
- DI18: in std_logic; DI19: in std_logic;
- DI20: in std_logic; DI21: in std_logic;
- DI22: in std_logic; DI23: in std_logic;
- DI24: in std_logic; DI25: in std_logic;
- DI26: in std_logic; DI27: in std_logic;
- DI28: in std_logic; DI29: in std_logic;
- DI30: in std_logic; DI31: in std_logic;
- DI32: in std_logic; DI33: in std_logic;
- DI34: in std_logic; DI35: in std_logic;
- ADW0: in std_logic; ADW1: in std_logic;
- ADW2: in std_logic; ADW3: in std_logic;
- ADW4: in std_logic; ADW5: in std_logic;
- ADW6: in std_logic; ADW7: in std_logic;
- ADW8: in std_logic; BE0: in std_logic; BE1: in std_logic;
- BE2: in std_logic; BE3: in std_logic; CEW: in std_logic;
- CLKW: in std_logic; CSW0: in std_logic;
- CSW1: in std_logic; CSW2: in std_logic;
- ADR0: in std_logic; ADR1: in std_logic;
- ADR2: in std_logic; ADR3: in std_logic;
- ADR4: in std_logic; ADR5: in std_logic;
- ADR6: in std_logic; ADR7: in std_logic;
- ADR8: in std_logic; ADR9: in std_logic;
- ADR10: in std_logic; ADR11: in std_logic;
- ADR12: in std_logic; ADR13: in std_logic;
- CER: in std_logic; CLKR: in std_logic; CSR0: in std_logic;
- CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic;
- DO0: out std_logic; DO1: out std_logic;
- DO2: out std_logic; DO3: out std_logic;
- DO4: out std_logic; DO5: out std_logic;
- DO6: out std_logic; DO7: out std_logic;
- DO8: out std_logic; DO9: out std_logic;
- DO10: out std_logic; DO11: out std_logic;
- DO12: out std_logic; DO13: out std_logic;
- DO14: out std_logic; DO15: out std_logic;
- DO16: out std_logic; DO17: out std_logic;
- DO18: out std_logic; DO19: out std_logic;
- DO20: out std_logic; DO21: out std_logic;
- DO22: out std_logic; DO23: out std_logic;
- DO24: out std_logic; DO25: out std_logic;
- DO26: out std_logic; DO27: out std_logic;
- DO28: out std_logic; DO29: out std_logic;
- DO30: out std_logic; DO31: out std_logic;
- DO32: out std_logic; DO33: out std_logic;
+ port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic;
+ DI3: in std_logic; DI4: in std_logic; DI5: in std_logic;
+ DI6: in std_logic; DI7: in std_logic; DI8: in std_logic;
+ DI9: in std_logic; DI10: in std_logic; DI11: in std_logic;
+ DI12: in std_logic; DI13: in std_logic;
+ DI14: in std_logic; DI15: in std_logic;
+ DI16: in std_logic; DI17: in std_logic;
+ DI18: in std_logic; DI19: in std_logic;
+ DI20: in std_logic; DI21: in std_logic;
+ DI22: in std_logic; DI23: in std_logic;
+ DI24: in std_logic; DI25: in std_logic;
+ DI26: in std_logic; DI27: in std_logic;
+ DI28: in std_logic; DI29: in std_logic;
+ DI30: in std_logic; DI31: in std_logic;
+ DI32: in std_logic; DI33: in std_logic;
+ DI34: in std_logic; DI35: in std_logic;
+ ADW0: in std_logic; ADW1: in std_logic;
+ ADW2: in std_logic; ADW3: in std_logic;
+ ADW4: in std_logic; ADW5: in std_logic;
+ ADW6: in std_logic; ADW7: in std_logic;
+ ADW8: in std_logic; BE0: in std_logic; BE1: in std_logic;
+ BE2: in std_logic; BE3: in std_logic; CEW: in std_logic;
+ CLKW: in std_logic; CSW0: in std_logic;
+ CSW1: in std_logic; CSW2: in std_logic;
+ ADR0: in std_logic; ADR1: in std_logic;
+ ADR2: in std_logic; ADR3: in std_logic;
+ ADR4: in std_logic; ADR5: in std_logic;
+ ADR6: in std_logic; ADR7: in std_logic;
+ ADR8: in std_logic; ADR9: in std_logic;
+ ADR10: in std_logic; ADR11: in std_logic;
+ ADR12: in std_logic; ADR13: in std_logic;
+ CER: in std_logic; CLKR: in std_logic; CSR0: in std_logic;
+ CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic;
+ DO0: out std_logic; DO1: out std_logic;
+ DO2: out std_logic; DO3: out std_logic;
+ DO4: out std_logic; DO5: out std_logic;
+ DO6: out std_logic; DO7: out std_logic;
+ DO8: out std_logic; DO9: out std_logic;
+ DO10: out std_logic; DO11: out std_logic;
+ DO12: out std_logic; DO13: out std_logic;
+ DO14: out std_logic; DO15: out std_logic;
+ DO16: out std_logic; DO17: out std_logic;
+ DO18: out std_logic; DO19: out std_logic;
+ DO20: out std_logic; DO21: out std_logic;
+ DO22: out std_logic; DO23: out std_logic;
+ DO24: out std_logic; DO25: out std_logic;
+ DO26: out std_logic; DO27: out std_logic;
+ DO28: out std_logic; DO29: out std_logic;
+ DO30: out std_logic; DO31: out std_logic;
+ DO32: out std_logic; DO33: out std_logic;
DO34: out std_logic; DO35: out std_logic);
end component;
- attribute initval : string;
- attribute MEM_LPC_FILE : string;
- attribute MEM_INIT_FILE : string;
- attribute CSDECODE_R : string;
- attribute CSDECODE_W : string;
- attribute RESETMODE : string;
- attribute REGMODE : string;
- attribute DATA_WIDTH_R : string;
- attribute DATA_WIDTH_W : string;
- attribute GSR : string;
+ attribute initval : string;
+ attribute MEM_LPC_FILE : string;
+ attribute MEM_INIT_FILE : string;
+ attribute CSDECODE_R : string;
+ attribute CSDECODE_W : string;
+ attribute RESETMODE : string;
+ attribute REGMODE : string;
+ attribute DATA_WIDTH_R : string;
+ attribute DATA_WIDTH_W : string;
+ attribute GSR : string;
attribute initval of LUT4_1 : label is "0x3232";
attribute initval of LUT4_0 : label is "0x3232";
attribute MEM_LPC_FILE of pdp_ram_0_0_1 : label is "fifo_512depth_72width_reg_out.lpc";
-- synopsys translate_off
generic map (initval=> "0x3232")
-- synopsys translate_on
- port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i,
+ port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i,
AD0=>empty_i, DO0=>empty_d);
LUT4_0: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x3232")
-- synopsys translate_on
- port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i,
+ port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i,
AD0=>full_i, DO0=>full_d);
AND2_t4: AND2
pdp_ram_0_0_1: PDPW16KB
-- synopsys translate_off
- generic map (CSDECODE_R=> "000", CSDECODE_W=> "001", GSR=> "DISABLED",
- RESETMODE=> "ASYNC", REGMODE=> "NOREG", DATA_WIDTH_R=> 36,
+ generic map (CSDECODE_R=> "000", CSDECODE_W=> "001", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "NOREG", DATA_WIDTH_R=> 36,
DATA_WIDTH_W=> 36)
-- synopsys translate_on
- port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
- DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
- DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11),
- DI12=>Data(12), DI13=>Data(13), DI14=>Data(14),
- DI15=>Data(15), DI16=>Data(16), DI17=>Data(17),
- DI18=>Data(18), DI19=>Data(19), DI20=>Data(20),
- DI21=>Data(21), DI22=>Data(22), DI23=>Data(23),
- DI24=>Data(24), DI25=>Data(25), DI26=>Data(26),
- DI27=>Data(27), DI28=>Data(28), DI29=>Data(29),
- DI30=>Data(30), DI31=>Data(31), DI32=>Data(32),
- DI33=>Data(33), DI34=>Data(34), DI35=>Data(35), ADW0=>wptr_0,
- ADW1=>wptr_1, ADW2=>wptr_2, ADW3=>wptr_3, ADW4=>wptr_4,
- ADW5=>wptr_5, ADW6=>wptr_6, ADW7=>wptr_7, ADW8=>wptr_8,
- BE0=>scuba_vhi, BE1=>scuba_vhi, BE2=>scuba_vhi,
- BE3=>scuba_vhi, CEW=>wren_i, CLKW=>Clock, CSW0=>scuba_vhi,
- CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo,
- ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>scuba_vlo,
- ADR4=>scuba_vlo, ADR5=>rptr_0, ADR6=>rptr_1, ADR7=>rptr_2,
- ADR8=>rptr_3, ADR9=>rptr_4, ADR10=>rptr_5, ADR11=>rptr_6,
- ADR12=>rptr_7, ADR13=>rptr_8, CER=>rden_i, CLKR=>Clock,
- CSR0=>scuba_vlo, CSR1=>scuba_vlo, CSR2=>scuba_vlo,
- RST=>Reset, DO0=>ffidata_18, DO1=>ffidata_19,
- DO2=>ffidata_20, DO3=>ffidata_21, DO4=>ffidata_22,
- DO5=>ffidata_23, DO6=>ffidata_24, DO7=>ffidata_25,
- DO8=>ffidata_26, DO9=>ffidata_27, DO10=>ffidata_28,
- DO11=>ffidata_29, DO12=>ffidata_30, DO13=>ffidata_31,
- DO14=>ffidata_32, DO15=>ffidata_33, DO16=>ffidata_34,
- DO17=>ffidata_35, DO18=>ffidata_0, DO19=>ffidata_1,
- DO20=>ffidata_2, DO21=>ffidata_3, DO22=>ffidata_4,
- DO23=>ffidata_5, DO24=>ffidata_6, DO25=>ffidata_7,
- DO26=>ffidata_8, DO27=>ffidata_9, DO28=>ffidata_10,
- DO29=>ffidata_11, DO30=>ffidata_12, DO31=>ffidata_13,
- DO32=>ffidata_14, DO33=>ffidata_15, DO34=>ffidata_16,
+ port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
+ DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
+ DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11),
+ DI12=>Data(12), DI13=>Data(13), DI14=>Data(14),
+ DI15=>Data(15), DI16=>Data(16), DI17=>Data(17),
+ DI18=>Data(18), DI19=>Data(19), DI20=>Data(20),
+ DI21=>Data(21), DI22=>Data(22), DI23=>Data(23),
+ DI24=>Data(24), DI25=>Data(25), DI26=>Data(26),
+ DI27=>Data(27), DI28=>Data(28), DI29=>Data(29),
+ DI30=>Data(30), DI31=>Data(31), DI32=>Data(32),
+ DI33=>Data(33), DI34=>Data(34), DI35=>Data(35), ADW0=>wptr_0,
+ ADW1=>wptr_1, ADW2=>wptr_2, ADW3=>wptr_3, ADW4=>wptr_4,
+ ADW5=>wptr_5, ADW6=>wptr_6, ADW7=>wptr_7, ADW8=>wptr_8,
+ BE0=>scuba_vhi, BE1=>scuba_vhi, BE2=>scuba_vhi,
+ BE3=>scuba_vhi, CEW=>wren_i, CLKW=>Clock, CSW0=>scuba_vhi,
+ CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo,
+ ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>scuba_vlo,
+ ADR4=>scuba_vlo, ADR5=>rptr_0, ADR6=>rptr_1, ADR7=>rptr_2,
+ ADR8=>rptr_3, ADR9=>rptr_4, ADR10=>rptr_5, ADR11=>rptr_6,
+ ADR12=>rptr_7, ADR13=>rptr_8, CER=>rden_i, CLKR=>Clock,
+ CSR0=>scuba_vlo, CSR1=>scuba_vlo, CSR2=>scuba_vlo,
+ RST=>Reset, DO0=>ffidata_18, DO1=>ffidata_19,
+ DO2=>ffidata_20, DO3=>ffidata_21, DO4=>ffidata_22,
+ DO5=>ffidata_23, DO6=>ffidata_24, DO7=>ffidata_25,
+ DO8=>ffidata_26, DO9=>ffidata_27, DO10=>ffidata_28,
+ DO11=>ffidata_29, DO12=>ffidata_30, DO13=>ffidata_31,
+ DO14=>ffidata_32, DO15=>ffidata_33, DO16=>ffidata_34,
+ DO17=>ffidata_35, DO18=>ffidata_0, DO19=>ffidata_1,
+ DO20=>ffidata_2, DO21=>ffidata_3, DO22=>ffidata_4,
+ DO23=>ffidata_5, DO24=>ffidata_6, DO25=>ffidata_7,
+ DO26=>ffidata_8, DO27=>ffidata_9, DO28=>ffidata_10,
+ DO29=>ffidata_11, DO30=>ffidata_12, DO31=>ffidata_13,
+ DO32=>ffidata_14, DO33=>ffidata_15, DO34=>ffidata_16,
DO35=>ffidata_17);
pdp_ram_0_1_0: PDPW16KB
-- synopsys translate_off
- generic map (CSDECODE_R=> "000", CSDECODE_W=> "001", GSR=> "DISABLED",
- RESETMODE=> "ASYNC", REGMODE=> "NOREG", DATA_WIDTH_R=> 36,
+ generic map (CSDECODE_R=> "000", CSDECODE_W=> "001", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "NOREG", DATA_WIDTH_R=> 36,
DATA_WIDTH_W=> 36)
-- synopsys translate_on
- port map (DI0=>Data(36), DI1=>Data(37), DI2=>Data(38),
- DI3=>Data(39), DI4=>Data(40), DI5=>Data(41), DI6=>Data(42),
- DI7=>Data(43), DI8=>Data(44), DI9=>Data(45), DI10=>Data(46),
- DI11=>Data(47), DI12=>Data(48), DI13=>Data(49),
- DI14=>Data(50), DI15=>Data(51), DI16=>Data(52),
- DI17=>Data(53), DI18=>Data(54), DI19=>Data(55),
- DI20=>Data(56), DI21=>Data(57), DI22=>Data(58),
- DI23=>Data(59), DI24=>Data(60), DI25=>Data(61),
- DI26=>Data(62), DI27=>Data(63), DI28=>Data(64),
- DI29=>Data(65), DI30=>Data(66), DI31=>Data(67),
- DI32=>Data(68), DI33=>Data(69), DI34=>Data(70),
- DI35=>Data(71), ADW0=>wptr_0, ADW1=>wptr_1, ADW2=>wptr_2,
- ADW3=>wptr_3, ADW4=>wptr_4, ADW5=>wptr_5, ADW6=>wptr_6,
- ADW7=>wptr_7, ADW8=>wptr_8, BE0=>scuba_vhi, BE1=>scuba_vhi,
- BE2=>scuba_vhi, BE3=>scuba_vhi, CEW=>wren_i, CLKW=>Clock,
- CSW0=>scuba_vhi, CSW1=>scuba_vlo, CSW2=>scuba_vlo,
- ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo,
- ADR3=>scuba_vlo, ADR4=>scuba_vlo, ADR5=>rptr_0, ADR6=>rptr_1,
- ADR7=>rptr_2, ADR8=>rptr_3, ADR9=>rptr_4, ADR10=>rptr_5,
- ADR11=>rptr_6, ADR12=>rptr_7, ADR13=>rptr_8, CER=>rden_i,
- CLKR=>Clock, CSR0=>scuba_vlo, CSR1=>scuba_vlo,
- CSR2=>scuba_vlo, RST=>Reset, DO0=>ffidata_54,
- DO1=>ffidata_55, DO2=>ffidata_56, DO3=>ffidata_57,
- DO4=>ffidata_58, DO5=>ffidata_59, DO6=>ffidata_60,
- DO7=>ffidata_61, DO8=>ffidata_62, DO9=>ffidata_63,
- DO10=>ffidata_64, DO11=>ffidata_65, DO12=>ffidata_66,
- DO13=>ffidata_67, DO14=>ffidata_68, DO15=>ffidata_69,
- DO16=>ffidata_70, DO17=>ffidata_71, DO18=>ffidata_36,
- DO19=>ffidata_37, DO20=>ffidata_38, DO21=>ffidata_39,
- DO22=>ffidata_40, DO23=>ffidata_41, DO24=>ffidata_42,
- DO25=>ffidata_43, DO26=>ffidata_44, DO27=>ffidata_45,
- DO28=>ffidata_46, DO29=>ffidata_47, DO30=>ffidata_48,
- DO31=>ffidata_49, DO32=>ffidata_50, DO33=>ffidata_51,
+ port map (DI0=>Data(36), DI1=>Data(37), DI2=>Data(38),
+ DI3=>Data(39), DI4=>Data(40), DI5=>Data(41), DI6=>Data(42),
+ DI7=>Data(43), DI8=>Data(44), DI9=>Data(45), DI10=>Data(46),
+ DI11=>Data(47), DI12=>Data(48), DI13=>Data(49),
+ DI14=>Data(50), DI15=>Data(51), DI16=>Data(52),
+ DI17=>Data(53), DI18=>Data(54), DI19=>Data(55),
+ DI20=>Data(56), DI21=>Data(57), DI22=>Data(58),
+ DI23=>Data(59), DI24=>Data(60), DI25=>Data(61),
+ DI26=>Data(62), DI27=>Data(63), DI28=>Data(64),
+ DI29=>Data(65), DI30=>Data(66), DI31=>Data(67),
+ DI32=>Data(68), DI33=>Data(69), DI34=>Data(70),
+ DI35=>Data(71), ADW0=>wptr_0, ADW1=>wptr_1, ADW2=>wptr_2,
+ ADW3=>wptr_3, ADW4=>wptr_4, ADW5=>wptr_5, ADW6=>wptr_6,
+ ADW7=>wptr_7, ADW8=>wptr_8, BE0=>scuba_vhi, BE1=>scuba_vhi,
+ BE2=>scuba_vhi, BE3=>scuba_vhi, CEW=>wren_i, CLKW=>Clock,
+ CSW0=>scuba_vhi, CSW1=>scuba_vlo, CSW2=>scuba_vlo,
+ ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo,
+ ADR3=>scuba_vlo, ADR4=>scuba_vlo, ADR5=>rptr_0, ADR6=>rptr_1,
+ ADR7=>rptr_2, ADR8=>rptr_3, ADR9=>rptr_4, ADR10=>rptr_5,
+ ADR11=>rptr_6, ADR12=>rptr_7, ADR13=>rptr_8, CER=>rden_i,
+ CLKR=>Clock, CSR0=>scuba_vlo, CSR1=>scuba_vlo,
+ CSR2=>scuba_vlo, RST=>Reset, DO0=>ffidata_54,
+ DO1=>ffidata_55, DO2=>ffidata_56, DO3=>ffidata_57,
+ DO4=>ffidata_58, DO5=>ffidata_59, DO6=>ffidata_60,
+ DO7=>ffidata_61, DO8=>ffidata_62, DO9=>ffidata_63,
+ DO10=>ffidata_64, DO11=>ffidata_65, DO12=>ffidata_66,
+ DO13=>ffidata_67, DO14=>ffidata_68, DO15=>ffidata_69,
+ DO16=>ffidata_70, DO17=>ffidata_71, DO18=>ffidata_36,
+ DO19=>ffidata_37, DO20=>ffidata_38, DO21=>ffidata_39,
+ DO22=>ffidata_40, DO23=>ffidata_41, DO24=>ffidata_42,
+ DO25=>ffidata_43, DO26=>ffidata_44, DO27=>ffidata_45,
+ DO28=>ffidata_46, DO29=>ffidata_47, DO30=>ffidata_48,
+ DO31=>ffidata_49, DO32=>ffidata_50, DO33=>ffidata_51,
DO34=>ffidata_52, DO35=>ffidata_53);
FF_145: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_0);
FF_144: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_1);
FF_143: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_2);
FF_142: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_3);
FF_141: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_4);
FF_140: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_5);
FF_139: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ifcount_6, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ port map (D=>ifcount_6, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_6);
FF_138: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ifcount_7, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ port map (D=>ifcount_7, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_7);
FF_137: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ifcount_8, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ port map (D=>ifcount_8, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_8);
FF_136: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ifcount_9, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ port map (D=>ifcount_9, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_9);
FF_135: FD1S3BX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, PD=>Reset,
+ port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, PD=>Reset,
Q=>wcount_0);
FF_132: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_1);
FF_131: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_2);
FF_130: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_3);
FF_129: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_4);
FF_128: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_5);
FF_127: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>iwcount_6, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>iwcount_6, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_6);
FF_126: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>iwcount_7, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>iwcount_7, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_7);
FF_125: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>iwcount_8, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>iwcount_8, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_8);
FF_124: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>iwcount_9, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>iwcount_9, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_9);
FF_123: FD1P3BX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ircount_0, SP=>rden_i, CK=>Clock, PD=>Reset,
+ port map (D=>ircount_0, SP=>rden_i, CK=>Clock, PD=>Reset,
Q=>rcount_0);
FF_122: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_1);
FF_121: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_2);
FF_120: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_3);
FF_119: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_4);
FF_118: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_5);
FF_117: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ircount_6, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>ircount_6, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_6);
FF_116: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ircount_7, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>ircount_7, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_7);
FF_115: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ircount_8, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>ircount_8, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_8);
FF_114: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ircount_9, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>ircount_9, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_9);
FF_113: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>wcount_0, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>wcount_0, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wptr_0);
FF_112: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>wcount_1, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>wcount_1, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wptr_1);
FF_111: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>wcount_2, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>wcount_2, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wptr_2);
FF_110: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>wcount_3, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>wcount_3, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wptr_3);
FF_109: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>wcount_4, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>wcount_4, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wptr_4);
FF_108: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>wcount_5, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>wcount_5, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wptr_5);
FF_107: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>wcount_6, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>wcount_6, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wptr_6);
FF_106: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>wcount_7, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>wcount_7, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wptr_7);
FF_105: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>wcount_8, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>wcount_8, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wptr_8);
FF_104: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>wcount_9, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>wcount_9, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wptr_9);
FF_103: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>rcount_0, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>rcount_0, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rptr_0);
FF_102: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>rcount_1, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>rcount_1, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rptr_1);
FF_101: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>rcount_2, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>rcount_2, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rptr_2);
FF_100: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>rcount_3, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>rcount_3, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rptr_3);
FF_99: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>rcount_4, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>rcount_4, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rptr_4);
FF_98: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>rcount_5, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>rcount_5, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rptr_5);
FF_97: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>rcount_6, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>rcount_6, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rptr_6);
FF_96: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>rcount_7, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>rcount_7, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rptr_7);
FF_95: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>rcount_8, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>rcount_8, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rptr_8);
FF_94: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>rcount_9, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>rcount_9, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rptr_9);
FF_93: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ffidata_0, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
+ port map (D=>ffidata_0, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
Q=>Q(0));
FF_92: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ffidata_1, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
+ port map (D=>ffidata_1, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
Q=>Q(1));
FF_91: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ffidata_2, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
+ port map (D=>ffidata_2, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
Q=>Q(2));
FF_90: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ffidata_3, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
+ port map (D=>ffidata_3, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
Q=>Q(3));
FF_89: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ffidata_4, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
+ port map (D=>ffidata_4, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
Q=>Q(4));
FF_88: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ffidata_5, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
+ port map (D=>ffidata_5, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
Q=>Q(5));
FF_87: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ffidata_6, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
+ port map (D=>ffidata_6, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
Q=>Q(6));
FF_86: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ffidata_7, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
+ port map (D=>ffidata_7, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
Q=>Q(7));
FF_85: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ffidata_8, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
+ port map (D=>ffidata_8, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
Q=>Q(8));
FF_84: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ffidata_9, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
+ port map (D=>ffidata_9, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
Q=>Q(9));
FF_83: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ffidata_10, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
+ port map (D=>ffidata_10, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
Q=>Q(10));
FF_82: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ffidata_11, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
+ port map (D=>ffidata_11, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
Q=>Q(11));
FF_81: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ffidata_12, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
+ port map (D=>ffidata_12, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
Q=>Q(12));
FF_80: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ffidata_13, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
+ port map (D=>ffidata_13, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
Q=>Q(13));
FF_79: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ffidata_14, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
+ port map (D=>ffidata_14, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
Q=>Q(14));
FF_78: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ffidata_15, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
+ port map (D=>ffidata_15, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
Q=>Q(15));
FF_77: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ffidata_16, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
+ port map (D=>ffidata_16, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
Q=>Q(16));
FF_76: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ffidata_17, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
+ port map (D=>ffidata_17, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
Q=>Q(17));
FF_75: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ffidata_18, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
+ port map (D=>ffidata_18, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
Q=>Q(18));
FF_74: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ffidata_19, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
+ port map (D=>ffidata_19, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
Q=>Q(19));
FF_73: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ffidata_20, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
+ port map (D=>ffidata_20, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
Q=>Q(20));
FF_72: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ffidata_21, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
+ port map (D=>ffidata_21, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
Q=>Q(21));
FF_71: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ffidata_22, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
+ port map (D=>ffidata_22, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
Q=>Q(22));
FF_70: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ffidata_23, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
+ port map (D=>ffidata_23, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
Q=>Q(23));
FF_69: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ffidata_24, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
+ port map (D=>ffidata_24, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
Q=>Q(24));
FF_68: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ffidata_25, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
+ port map (D=>ffidata_25, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
Q=>Q(25));
FF_67: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ffidata_26, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
+ port map (D=>ffidata_26, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
Q=>Q(26));
FF_66: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ffidata_27, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
+ port map (D=>ffidata_27, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
Q=>Q(27));
FF_65: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ffidata_28, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
+ port map (D=>ffidata_28, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
Q=>Q(28));
FF_64: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ffidata_29, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
+ port map (D=>ffidata_29, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
Q=>Q(29));
FF_63: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ffidata_30, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
+ port map (D=>ffidata_30, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
Q=>Q(30));
FF_62: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ffidata_31, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
+ port map (D=>ffidata_31, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
Q=>Q(31));
FF_61: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ffidata_32, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
+ port map (D=>ffidata_32, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
Q=>Q(32));
FF_60: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ffidata_33, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
+ port map (D=>ffidata_33, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
Q=>Q(33));
FF_59: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ffidata_34, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
+ port map (D=>ffidata_34, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
Q=>Q(34));
FF_58: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ffidata_35, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
+ port map (D=>ffidata_35, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
Q=>Q(35));
FF_57: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ffidata_36, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
+ port map (D=>ffidata_36, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
Q=>Q(36));
FF_56: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ffidata_37, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
+ port map (D=>ffidata_37, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
Q=>Q(37));
FF_55: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ffidata_38, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
+ port map (D=>ffidata_38, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
Q=>Q(38));
FF_54: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ffidata_39, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
+ port map (D=>ffidata_39, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
Q=>Q(39));
FF_53: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ffidata_40, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
+ port map (D=>ffidata_40, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
Q=>Q(40));
FF_52: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ffidata_41, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
+ port map (D=>ffidata_41, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
Q=>Q(41));
FF_51: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ffidata_42, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
+ port map (D=>ffidata_42, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
Q=>Q(42));
FF_50: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ffidata_43, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
+ port map (D=>ffidata_43, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
Q=>Q(43));
FF_49: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ffidata_44, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
+ port map (D=>ffidata_44, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
Q=>Q(44));
FF_48: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ffidata_45, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
+ port map (D=>ffidata_45, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
Q=>Q(45));
FF_47: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ffidata_46, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
+ port map (D=>ffidata_46, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
Q=>Q(46));
FF_46: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ffidata_47, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
+ port map (D=>ffidata_47, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
Q=>Q(47));
FF_45: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ffidata_48, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
+ port map (D=>ffidata_48, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
Q=>Q(48));
FF_44: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ffidata_49, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
+ port map (D=>ffidata_49, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
Q=>Q(49));
FF_43: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ffidata_50, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
+ port map (D=>ffidata_50, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
Q=>Q(50));
FF_42: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ffidata_51, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
+ port map (D=>ffidata_51, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
Q=>Q(51));
FF_41: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ffidata_52, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
+ port map (D=>ffidata_52, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
Q=>Q(52));
FF_40: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ffidata_53, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
+ port map (D=>ffidata_53, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
Q=>Q(53));
FF_39: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ffidata_54, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
+ port map (D=>ffidata_54, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
Q=>Q(54));
FF_38: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ffidata_55, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
+ port map (D=>ffidata_55, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
Q=>Q(55));
FF_37: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ffidata_56, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
+ port map (D=>ffidata_56, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
Q=>Q(56));
FF_36: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ffidata_57, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
+ port map (D=>ffidata_57, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
Q=>Q(57));
FF_35: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ffidata_58, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
+ port map (D=>ffidata_58, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
Q=>Q(58));
FF_34: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ffidata_59, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
+ port map (D=>ffidata_59, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
Q=>Q(59));
FF_33: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ffidata_60, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
+ port map (D=>ffidata_60, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
Q=>Q(60));
FF_32: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ffidata_61, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
+ port map (D=>ffidata_61, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
Q=>Q(61));
FF_31: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ffidata_62, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
+ port map (D=>ffidata_62, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
Q=>Q(62));
FF_30: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ffidata_63, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
+ port map (D=>ffidata_63, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
Q=>Q(63));
FF_29: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ffidata_64, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
+ port map (D=>ffidata_64, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
Q=>Q(64));
FF_28: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ffidata_65, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
+ port map (D=>ffidata_65, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
Q=>Q(65));
FF_27: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ffidata_66, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
+ port map (D=>ffidata_66, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
Q=>Q(66));
FF_26: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ffidata_67, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
+ port map (D=>ffidata_67, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
Q=>Q(67));
FF_25: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ffidata_68, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
+ port map (D=>ffidata_68, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
Q=>Q(68));
FF_24: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ffidata_69, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
+ port map (D=>ffidata_69, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
Q=>Q(69));
FF_23: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ffidata_70, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
+ port map (D=>ffidata_70, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
Q=>Q(70));
FF_22: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ffidata_71, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
+ port map (D=>ffidata_71, SP=>scuba_vhi, CK=>Clock, CD=>Reset,
Q=>Q(71));
FF_21: FD1S3DX
port map (D=>af_set, CK=>Clock, CD=>Reset, Q=>AlmostFull);
bdcnt_bctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>cnt_con, B0=>scuba_vlo, B1=>cnt_con,
+ port map (A0=>scuba_vlo, A1=>cnt_con, B0=>scuba_vlo, B1=>cnt_con,
CI=>scuba_vlo, COUT=>bdcnt_bctr_ci, S0=>open, S1=>open);
bdcnt_bctr_0: CB2
- port map (CI=>bdcnt_bctr_ci, PC0=>fcount_0, PC1=>fcount_1,
+ port map (CI=>bdcnt_bctr_ci, PC0=>fcount_0, PC1=>fcount_1,
CON=>cnt_con, CO=>co0, NC0=>ifcount_0, NC1=>ifcount_1);
bdcnt_bctr_1: CB2
- port map (CI=>co0, PC0=>fcount_2, PC1=>fcount_3, CON=>cnt_con,
+ port map (CI=>co0, PC0=>fcount_2, PC1=>fcount_3, CON=>cnt_con,
CO=>co1, NC0=>ifcount_2, NC1=>ifcount_3);
bdcnt_bctr_2: CB2
- port map (CI=>co1, PC0=>fcount_4, PC1=>fcount_5, CON=>cnt_con,
+ port map (CI=>co1, PC0=>fcount_4, PC1=>fcount_5, CON=>cnt_con,
CO=>co2, NC0=>ifcount_4, NC1=>ifcount_5);
bdcnt_bctr_3: CB2
- port map (CI=>co2, PC0=>fcount_6, PC1=>fcount_7, CON=>cnt_con,
+ port map (CI=>co2, PC0=>fcount_6, PC1=>fcount_7, CON=>cnt_con,
CO=>co3, NC0=>ifcount_6, NC1=>ifcount_7);
bdcnt_bctr_4: CB2
- port map (CI=>co3, PC0=>fcount_8, PC1=>fcount_9, CON=>cnt_con,
+ port map (CI=>co3, PC0=>fcount_8, PC1=>fcount_9, CON=>cnt_con,
CO=>co4, NC0=>ifcount_8, NC1=>ifcount_9);
e_cmp_ci_a: FADD2B
- port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci, S0=>open,
+ port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci, S0=>open,
S1=>open);
e_cmp_0: ALEB2
- port map (A0=>fcount_0, A1=>fcount_1, B0=>rden_i, B1=>scuba_vlo,
+ port map (A0=>fcount_0, A1=>fcount_1, B0=>rden_i, B1=>scuba_vlo,
CI=>cmp_ci, LE=>co0_1);
e_cmp_1: ALEB2
- port map (A0=>fcount_2, A1=>fcount_3, B0=>scuba_vlo,
+ port map (A0=>fcount_2, A1=>fcount_3, B0=>scuba_vlo,
B1=>scuba_vlo, CI=>co0_1, LE=>co1_1);
e_cmp_2: ALEB2
- port map (A0=>fcount_4, A1=>fcount_5, B0=>scuba_vlo,
+ port map (A0=>fcount_4, A1=>fcount_5, B0=>scuba_vlo,
B1=>scuba_vlo, CI=>co1_1, LE=>co2_1);
e_cmp_3: ALEB2
- port map (A0=>fcount_6, A1=>fcount_7, B0=>scuba_vlo,
+ port map (A0=>fcount_6, A1=>fcount_7, B0=>scuba_vlo,
B1=>scuba_vlo, CI=>co2_1, LE=>co3_1);
e_cmp_4: ALEB2
- port map (A0=>fcount_8, A1=>fcount_9, B0=>scuba_vlo,
+ port map (A0=>fcount_8, A1=>fcount_9, B0=>scuba_vlo,
B1=>scuba_vlo, CI=>co3_1, LE=>cmp_le_1_c);
a0: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>cmp_le_1_c, COUT=>open, S0=>cmp_le_1,
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>cmp_le_1_c, COUT=>open, S0=>cmp_le_1,
S1=>open);
g_cmp_ci_a: FADD2B
- port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open,
+ port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open,
S1=>open);
g_cmp_0: AGEB2
- port map (A0=>fcount_0, A1=>fcount_1, B0=>wren_i, B1=>wren_i,
+ port map (A0=>fcount_0, A1=>fcount_1, B0=>wren_i, B1=>wren_i,
CI=>cmp_ci_1, GE=>co0_2);
g_cmp_1: AGEB2
- port map (A0=>fcount_2, A1=>fcount_3, B0=>wren_i, B1=>wren_i,
+ port map (A0=>fcount_2, A1=>fcount_3, B0=>wren_i, B1=>wren_i,
CI=>co0_2, GE=>co1_2);
g_cmp_2: AGEB2
- port map (A0=>fcount_4, A1=>fcount_5, B0=>wren_i, B1=>wren_i,
+ port map (A0=>fcount_4, A1=>fcount_5, B0=>wren_i, B1=>wren_i,
CI=>co1_2, GE=>co2_2);
g_cmp_3: AGEB2
- port map (A0=>fcount_6, A1=>fcount_7, B0=>wren_i, B1=>wren_i,
+ port map (A0=>fcount_6, A1=>fcount_7, B0=>wren_i, B1=>wren_i,
CI=>co2_2, GE=>co3_2);
g_cmp_4: AGEB2
- port map (A0=>fcount_8, A1=>fcount_9, B0=>wren_i, B1=>wren_i_inv,
+ port map (A0=>fcount_8, A1=>fcount_9, B0=>wren_i, B1=>wren_i_inv,
CI=>co3_2, GE=>cmp_ge_d1_c);
a1: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>cmp_ge_d1_c, COUT=>open, S0=>cmp_ge_d1,
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>cmp_ge_d1_c, COUT=>open, S0=>cmp_ge_d1,
S1=>open);
w_ctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_ctr_ci, S0=>open,
+ port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_ctr_ci, S0=>open,
S1=>open);
w_ctr_0: CU2
- port map (CI=>w_ctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0_3,
+ port map (CI=>w_ctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0_3,
NC0=>iwcount_0, NC1=>iwcount_1);
w_ctr_1: CU2
- port map (CI=>co0_3, PC0=>wcount_2, PC1=>wcount_3, CO=>co1_3,
+ port map (CI=>co0_3, PC0=>wcount_2, PC1=>wcount_3, CO=>co1_3,
NC0=>iwcount_2, NC1=>iwcount_3);
w_ctr_2: CU2
- port map (CI=>co1_3, PC0=>wcount_4, PC1=>wcount_5, CO=>co2_3,
+ port map (CI=>co1_3, PC0=>wcount_4, PC1=>wcount_5, CO=>co2_3,
NC0=>iwcount_4, NC1=>iwcount_5);
w_ctr_3: CU2
- port map (CI=>co2_3, PC0=>wcount_6, PC1=>wcount_7, CO=>co3_3,
+ port map (CI=>co2_3, PC0=>wcount_6, PC1=>wcount_7, CO=>co3_3,
NC0=>iwcount_6, NC1=>iwcount_7);
w_ctr_4: CU2
- port map (CI=>co3_3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4_1,
+ port map (CI=>co3_3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4_1,
NC0=>iwcount_8, NC1=>iwcount_9);
scuba_vhi_inst: VHI
port map (Z=>scuba_vhi);
r_ctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_ctr_ci, S0=>open,
+ port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_ctr_ci, S0=>open,
S1=>open);
r_ctr_0: CU2
- port map (CI=>r_ctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_4,
+ port map (CI=>r_ctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_4,
NC0=>ircount_0, NC1=>ircount_1);
r_ctr_1: CU2
- port map (CI=>co0_4, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_4,
+ port map (CI=>co0_4, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_4,
NC0=>ircount_2, NC1=>ircount_3);
r_ctr_2: CU2
- port map (CI=>co1_4, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_4,
+ port map (CI=>co1_4, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_4,
NC0=>ircount_4, NC1=>ircount_5);
r_ctr_3: CU2
- port map (CI=>co2_4, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_4,
+ port map (CI=>co2_4, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_4,
NC0=>ircount_6, NC1=>ircount_7);
r_ctr_4: CU2
- port map (CI=>co3_4, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_2,
+ port map (CI=>co3_4, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_2,
NC0=>ircount_8, NC1=>ircount_9);
rcnt_0: FSUB2B
- port map (A0=>r_nw_inv, A1=>wcount_0, B0=>r_nw_inv_inv,
- B1=>rcount_0, BI=>scuba_vlo, BOUT=>co0_5, S0=>open,
+ port map (A0=>r_nw_inv, A1=>wcount_0, B0=>r_nw_inv_inv,
+ B1=>rcount_0, BI=>scuba_vlo, BOUT=>co0_5, S0=>open,
S1=>rcnt_sub_0);
rcnt_1: FSUB2B
- port map (A0=>wcount_1, A1=>wcount_2, B0=>rcount_1, B1=>rcount_2,
+ port map (A0=>wcount_1, A1=>wcount_2, B0=>rcount_1, B1=>rcount_2,
BI=>co0_5, BOUT=>co1_5, S0=>rcnt_sub_1, S1=>rcnt_sub_2);
rcnt_2: FSUB2B
- port map (A0=>wcount_3, A1=>wcount_4, B0=>rcount_3, B1=>rcount_4,
+ port map (A0=>wcount_3, A1=>wcount_4, B0=>rcount_3, B1=>rcount_4,
BI=>co1_5, BOUT=>co2_5, S0=>rcnt_sub_3, S1=>rcnt_sub_4);
rcnt_3: FSUB2B
- port map (A0=>wcount_5, A1=>wcount_6, B0=>rcount_5, B1=>rcount_6,
+ port map (A0=>wcount_5, A1=>wcount_6, B0=>rcount_5, B1=>rcount_6,
BI=>co2_5, BOUT=>co3_5, S0=>rcnt_sub_5, S1=>rcnt_sub_6);
rcnt_4: FSUB2B
- port map (A0=>wcount_7, A1=>wcount_8, B0=>rcount_7, B1=>rcount_8,
+ port map (A0=>wcount_7, A1=>wcount_8, B0=>rcount_7, B1=>rcount_8,
BI=>co3_5, BOUT=>co4_3, S0=>rcnt_sub_7, S1=>rcnt_sub_8);
rcnt_5: FSUB2B
- port map (A0=>rcnt_sub_msb, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, BI=>co4_3, BOUT=>open, S0=>rcnt_sub_9,
+ port map (A0=>rcnt_sub_msb, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, BI=>co4_3, BOUT=>open, S0=>rcnt_sub_9,
S1=>open);
ae_set_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i,
+ port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i,
CI=>scuba_vlo, COUT=>cmp_ci_2, S0=>open, S1=>open);
ae_set_cmp_0: AGEB2
- port map (A0=>AmEmptyThresh(0), A1=>AmEmptyThresh(1),
+ port map (A0=>AmEmptyThresh(0), A1=>AmEmptyThresh(1),
B0=>rcnt_reg_0, B1=>rcnt_reg_1, CI=>cmp_ci_2, GE=>co0_6);
ae_set_cmp_1: AGEB2
- port map (A0=>AmEmptyThresh(2), A1=>AmEmptyThresh(3),
+ port map (A0=>AmEmptyThresh(2), A1=>AmEmptyThresh(3),
B0=>rcnt_reg_2, B1=>rcnt_reg_3, CI=>co0_6, GE=>co1_6);
ae_set_cmp_2: AGEB2
- port map (A0=>AmEmptyThresh(4), A1=>AmEmptyThresh(5),
+ port map (A0=>AmEmptyThresh(4), A1=>AmEmptyThresh(5),
B0=>rcnt_reg_4, B1=>rcnt_reg_5, CI=>co1_6, GE=>co2_6);
ae_set_cmp_3: AGEB2
- port map (A0=>AmEmptyThresh(6), A1=>AmEmptyThresh(7),
+ port map (A0=>AmEmptyThresh(6), A1=>AmEmptyThresh(7),
B0=>rcnt_reg_6, B1=>rcnt_reg_7, CI=>co2_6, GE=>co3_6);
ae_set_cmp_4: AGEB2
- port map (A0=>AmEmptyThresh(8), A1=>ae_set_setsig,
+ port map (A0=>AmEmptyThresh(8), A1=>ae_set_setsig,
B0=>rcnt_reg_8, B1=>ae_set_clrsig, CI=>co3_6, GE=>ae_set_d_c);
a2: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>ae_set_d_c, COUT=>open, S0=>ae_set_d,
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>ae_set_d_c, COUT=>open, S0=>ae_set_d,
S1=>open);
wcnt_0: FSUB2B
- port map (A0=>cnt_con, A1=>wcount_0, B0=>cnt_con_inv, B1=>rptr_0,
+ port map (A0=>cnt_con, A1=>wcount_0, B0=>cnt_con_inv, B1=>rptr_0,
BI=>scuba_vlo, BOUT=>co0_7, S0=>open, S1=>wcnt_sub_0);
wcnt_1: FSUB2B
- port map (A0=>wcount_1, A1=>wcount_2, B0=>rptr_1, B1=>rptr_2,
+ port map (A0=>wcount_1, A1=>wcount_2, B0=>rptr_1, B1=>rptr_2,
BI=>co0_7, BOUT=>co1_7, S0=>wcnt_sub_1, S1=>wcnt_sub_2);
wcnt_2: FSUB2B
- port map (A0=>wcount_3, A1=>wcount_4, B0=>rptr_3, B1=>rptr_4,
+ port map (A0=>wcount_3, A1=>wcount_4, B0=>rptr_3, B1=>rptr_4,
BI=>co1_7, BOUT=>co2_7, S0=>wcnt_sub_3, S1=>wcnt_sub_4);
wcnt_3: FSUB2B
- port map (A0=>wcount_5, A1=>wcount_6, B0=>rptr_5, B1=>rptr_6,
+ port map (A0=>wcount_5, A1=>wcount_6, B0=>rptr_5, B1=>rptr_6,
BI=>co2_7, BOUT=>co3_7, S0=>wcnt_sub_5, S1=>wcnt_sub_6);
wcnt_4: FSUB2B
- port map (A0=>wcount_7, A1=>wcount_8, B0=>rptr_7, B1=>rptr_8,
+ port map (A0=>wcount_7, A1=>wcount_8, B0=>rptr_7, B1=>rptr_8,
BI=>co3_7, BOUT=>co4_4, S0=>wcnt_sub_7, S1=>wcnt_sub_8);
wcnt_5: FSUB2B
- port map (A0=>wcnt_sub_msb, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, BI=>co4_4, BOUT=>open, S0=>wcnt_sub_9,
+ port map (A0=>wcnt_sub_msb, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, BI=>co4_4, BOUT=>open, S0=>wcnt_sub_9,
S1=>open);
af_set_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
+ port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
CI=>scuba_vlo, COUT=>cmp_ci_3, S0=>open, S1=>open);
af_set_cmp_0: AGEB2
- port map (A0=>wcnt_reg_0, A1=>wcnt_reg_1, B0=>AmFullThresh(0),
+ port map (A0=>wcnt_reg_0, A1=>wcnt_reg_1, B0=>AmFullThresh(0),
B1=>AmFullThresh(1), CI=>cmp_ci_3, GE=>co0_8);
af_set_cmp_1: AGEB2
- port map (A0=>wcnt_reg_2, A1=>wcnt_reg_3, B0=>AmFullThresh(2),
+ port map (A0=>wcnt_reg_2, A1=>wcnt_reg_3, B0=>AmFullThresh(2),
B1=>AmFullThresh(3), CI=>co0_8, GE=>co1_8);
af_set_cmp_2: AGEB2
- port map (A0=>wcnt_reg_4, A1=>wcnt_reg_5, B0=>AmFullThresh(4),
+ port map (A0=>wcnt_reg_4, A1=>wcnt_reg_5, B0=>AmFullThresh(4),
B1=>AmFullThresh(5), CI=>co1_8, GE=>co2_8);
af_set_cmp_3: AGEB2
- port map (A0=>wcnt_reg_6, A1=>wcnt_reg_7, B0=>AmFullThresh(6),
+ port map (A0=>wcnt_reg_6, A1=>wcnt_reg_7, B0=>AmFullThresh(6),
B1=>AmFullThresh(7), CI=>co2_8, GE=>co3_8);
af_set_cmp_4: AGEB2
- port map (A0=>wcnt_reg_8, A1=>wcnt_reg_9, B0=>AmFullThresh(8),
+ port map (A0=>wcnt_reg_8, A1=>wcnt_reg_9, B0=>AmFullThresh(8),
B1=>scuba_vlo, CI=>co3_8, GE=>af_set_c);
scuba_vlo_inst: VLO
port map (Z=>scuba_vlo);
a3: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>af_set_c, COUT=>open, S0=>af_set,
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>af_set_c, COUT=>open, S0=>af_set,
S1=>open);
WCNT(0) <= fcount_0;
LVL1_TRG_RECEIVED_IN : in std_logic;
LVL1_TRG_NUMBER_IN : in std_logic_vector(15 downto 0);
LVL1_TRG_CODE_IN : in std_logic_vector(7 downto 0);
- LVL1_TRG_INFORMATION_IN : in std_logic_vector(7 downto 0);
+ LVL1_TRG_INFORMATION_IN : in std_logic_vector(23 downto 0);
LVL1_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0) := x"00000000";
LVL1_TRG_RELEASE_OUT : out std_logic := '0';
+ LVL1_INT_TRG_NUMBER_OUT : in std_logic_vector(15 downto 0);
--Data Port
IPU_NUMBER_IN : in std_logic_vector (15 downto 0);
type state_type is (idle_state, wait_for_token,
send_second_header_state, send_data_state,
- send_data_1_state,busy_header_state);
+ send_data_1_state,busy_header_state,
+ wait_for_lvl1_information);
signal current_state, next_state : state_type;
signal words_in_event : std_logic_vector(15 downto 0):=(others => '0');
signal debug_register_tdc_readout_i : std_logic_vector(3 downto 0);
- signal reg_trigger_type : std_logic_vector(3 downto 0);
+-- signal reg_trigger_type : std_logic_vector(3 downto 0);
signal token_tdc_readout_i : std_logic_vector(3 downto 0);
signal reg_first_header : std_logic_vector(71 downto 0);
signal data_tdc_readout_i : std_logic_vector(35 downto 0);
signal write_fee_data_fifo_i : std_logic;
- signal flag_event_counter : std_logic_vector(3 downto 0);
+-- signal flag_event_counter : std_logic_vector(3 downto 0);
signal pulse_init_tdc_readout : std_logic;
- signal counter_timing_trigger : std_logic_vector (15 downto 0);
-
+-- signal counter_timing_trigger : std_logic_vector (15 downto 0);
+
signal next_debug_register_fsm_multiplexer : std_logic_vector(7 downto 0);
signal reg_debug_register_fsm_multiplexer : std_logic_vector(7 downto 0);
signal fee_data_fifo_out_i : std_logic_vector(35 downto 0);
signal header_data_fifo_out_i : std_logic_vector(71 downto 0);
- signal data_header_fifo_in_i : std_logic_vector(71 downto 0);
+-- signal data_header_fifo_in_i : std_logic_vector(71 downto 0);
signal reg_debug_register_fsm_header, next_debug_register_fsm_header : std_logic_vector(7 downto 0);
signal write_header_fifo_i, next_write_header_fifo_i : std_logic;
signal word_count_header_fifo : std_logic_vector(9 downto 0);
signal reg_lvl1_trg_received : std_logic;
- signal reg_lvl1_trg_type : std_logic_vector(3 downto 0);
- signal reg_lvl1_trg_code : std_logic_vector(7 downto 0);
- signal reg_lvl1_trg_information, reg_ipu_information : std_logic_vector(7 downto 0);
- signal reg_ipu_number : std_logic_vector (15 downto 0);
+ signal reg_lvl1_trg_type : std_logic_vector(3 downto 0);
+ signal reg_lvl1_trg_code : std_logic_vector(7 downto 0);
+ signal reg_lvl1_trg_information : std_logic_vector (23 downto 0);
+ signal reg_ipu_information : std_logic_vector (7 downto 0);
+ signal reg_ipu_number : std_logic_vector (15 downto 0);
signal next_ipu_data : std_logic_vector (31 downto 0);
signal reg_ipu_finished, next_ipu_finished : std_logic;
signal counter_word_read_from_trbnet : std_logic_vector(3 downto 0);
signal reg_flag_in_header : std_logic_vector(3 downto 0);
signal empty_flag_fee_data_fifo_i, empty_flag_header_data_fifo_i : std_logic;
- signal counter_token_back : std_logic_vector(31 downto 0);
+-- signal counter_token_back : std_logic_vector(31 downto 0);
signal full_flag_fee_data_fifo_i,almost_empty_flag_fee_data_fifo_i,almost_full_flag_fee_data_fifo_i : std_logic;
signal full_flag_header_data_fifo_i,almost_empty_flag_header_data_fifo_i,almost_full_flag_header_data_fifo_i : std_logic;
signal reg_ipu_start_readout_in : std_logic;
signal last2_read_fee_data_fifo : std_logic;
signal next_ipu_dataready : std_logic;
signal reg_ipu_error_pattern : std_logic_vector(31 downto 0);
- signal next_ipu_error_pattern : std_logic_vector(31 downto 0);
+-- signal next_ipu_error_pattern : std_logic_vector(31 downto 0);
signal next_flag_in_header : std_logic_vector(3 downto 0);
- signal init_tdc_readout_i : std_logic_vector(3 downto 0);
+-- signal init_tdc_readout_i : std_logic_vector(3 downto 0);
signal error_data_header_info_i : std_logic_vector(19 downto 0);
signal clear_counter_error_token_back : std_logic;
signal counter_error_token_back : std_logic_vector(12 downto 0);
-
+ signal internal_trigger_number : std_logic_vector(15 downto 0);
+
begin -- behavioral
- INIT_TDC_READOUT_IN_0_PULSE : edge_to_pulse
+ THE_INIT_TDC_READOUT_IN_0_PULSE : edge_to_pulse
port map (
CLOCK => CLK,
ENABLE_CLK_IN => '1',
SIGNAL_IN => INIT_TDC_READOUT_IN(0),
- PULSE_OUT => pulse_init_tdc_readout);
+ PULSE_OUT => pulse_init_tdc_readout
+ );
-TDC_READOUT_INTERFACE : tdc_readout
+ THE_TDC_READOUT_INTERFACE : tdc_readout
port map (
CLK => CLK,
RESET => RESET,
TOKEN_IN => TOKEN_IN, --here from tld
TOKEN_TDC_READOUT_OUT => token_tdc_readout_i,
- FLAG_EVENT_COUNTER_IN => flag_event_counter,
+ FLAG_EVENT_COUNTER_IN => internal_trigger_number(3 downto 0), --flag_event_counter,
DATA_VALID_OUT => write_fee_data_fifo_i,
DATA_BUS_OUT => data_tdc_readout_i,
--generator after send
--token
FULL_FIFO_IN => '0',
- ERROR_DATA_INFO_IN => (others => '0'),
+ ERROR_DATA_INFO_IN => (others => '0'),
DATA_TYPE_SELECT_IN => DATA_TYPE_SELECT_IN,
- DEBUG_REGISTER_OUT => debug_register_tdc_readout_i);
+ DEBUG_REGISTER_OUT => debug_register_tdc_readout_i
+ );
-------------------------------------------------------------------------------
-- OENP point test token back
-------------------------------------------------------------------------------
-- FIFO for Data and Header Information
-------------------------------------------------------------------------------
- FEE_DATA_FIFO : fifo_8192depth_36width_dual_thresh_reg_out
+ THE_FEE_DATA_FIFO : fifo_8192depth_36width_dual_thresh_reg_out
port map (
Data => data_tdc_readout_i,
Clock => CLK,
Empty => empty_flag_fee_data_fifo_i,
Full => full_flag_fee_data_fifo_i,
AlmostEmpty => almost_empty_flag_fee_data_fifo_i,
- AlmostFull => almost_full_flag_fee_data_fifo_i);
+ AlmostFull => almost_full_flag_fee_data_fifo_i
+ );
- HEADER_FIFO: fifo_512depth_72width_reg_out
+ THE_HEADER_FIFO: fifo_512depth_72width_reg_out
port map (
- Data => reg_first_header,
- Clock => CLK,
+ Data => reg_first_header,
+ Clock => CLK,
WrEn => write_header_fifo_i,
RdEn => read_header_fifo,
Reset => RESET,
AmEmptyThresh => '0'& x"00",
- AmFullThresh => '0'& x"00",
+ AmFullThresh => '1'& x"00",
Q => header_data_fifo_out_i,
WCNT => word_count_header_fifo,
Empty => empty_flag_header_data_fifo_i,
Full => full_flag_header_data_fifo_i,
- AlmostEmpty => almost_empty_flag_header_data_fifo_i,
- AlmostFull => almost_full_flag_header_data_fifo_i);
-
+ AlmostEmpty => almost_empty_flag_header_data_fifo_i,
+ AlmostFull => almost_full_flag_header_data_fifo_i
+ );
+
-- HEADER_FIFO: fifo_fall_through_512depth_52width_reg_out
-- port map (
-- Data => reg_first_header,
-- AlmostEmpty => almost_empty_flag_header_data_fifo_i,
-- AlmostFull => almost_full_flag_header_data_fifo_i);
-
+
-- Count number of dataword per event written to fifo
- a_add_data_counter : process (CLK)
- begin
- if rising_edge(CLK) then
- if (RESET = '1' or pulse_init_tdc_readout = '1') then --reset at every trigger
- words_in_event <= (others => '0');
- elsif (write_fee_data_fifo_i = '1') then
- words_in_event <= words_in_event + 1;
+ proc_a_add_data_counter : process (CLK)
+ begin
+ if rising_edge(CLK) then
+ if (RESET = '1' or pulse_init_tdc_readout = '1') then --reset at every trigger
+ words_in_event <= (others => '0');
+ elsif (write_fee_data_fifo_i = '1') then
+ words_in_event <= words_in_event + 1;
+ end if;
end if;
- end if;
- end process a_add_data_counter;
+ end process proc_a_add_data_counter;
-------------------------------------------------------------------------------
-- OUTPUT CONNECTIONS
-------------------------------------------------------------------------------
--counter number of token back
--reset it when the event has been transferred to trbnet
-process (CLK, RESET,token_tdc_readout_i)
- begin
- if rising_edge(CLK) then
- if (RESET = '1') then
- counter_token_back <= (others => '0');
- elsif (token_tdc_readout_i(0) = '1') then
- counter_token_back <= counter_token_back + 1;
- end if;
- end if;
- end process;
+-- proc_token_back_counter : process (CLK)
+-- begin
+-- if rising_edge(CLK) then
+-- if (RESET = '1') then
+-- counter_token_back <= (others => '0');
+-- elsif (token_tdc_readout_i(0) = '1') then
+-- counter_token_back <= counter_token_back + 1;
+-- end if;
+-- end if;
+-- end process;
-------------------------------------------------------------------------------
-- Make headers 36 bit
-------------------------------------------------------------------------------
--register header
-process (CLK)
- begin
- if rising_edge(CLK) then
- reg_first_header <= error_data_header_info_i &-- (71 downto 52)
- words_in_event & --(15 downto 0)
- flag_event_counter & --(3 downto 0)
- "0000" & --(3 downto 0)
- reg_lvl1_trg_type & --(3 downto 0)
- reg_lvl1_trg_code & --(7 downto 0)
- reg_lvl1_trg_number; --(15 downto 0);
- end if;
- end process;
+ proc_dhdr_word : process (CLK)
+ begin
+ if rising_edge(CLK) then
+ reg_first_header <= error_data_header_info_i &-- (71 downto 52)
+ words_in_event & --(15 downto 0)
+ internal_trigger_number(3 downto 0) & --flag_event_counter & --(3 downto 0)
+ "0000" & --(3 downto 0)
+ reg_lvl1_trg_type & --(3 downto 0)
+ reg_lvl1_trg_code & --(7 downto 0)
+ reg_lvl1_trg_number; --(15 downto 0);
+ end if;
+ end process;
-------------------------------------------------------------------------------
--FSM: Control writing to FIFOs
-------------------------------------------------------------------------------
- process (CLK)
- begin
- if rising_edge(CLK) then
- if RESET = '1' then
- current_state <= idle_state;
- reg_debug_register_fsm_header <= (others => '0');
- write_header_fifo_i <= '0';
- reg_lvl1_busy_i <= '0';
- else
- current_state <= next_state;
- reg_debug_register_fsm_header <= next_debug_register_fsm_header;
- write_header_fifo_i <= next_write_header_fifo_i;
- reg_lvl1_busy_i <= next_lvl1_busy_i;
- end if;
- end if;
- end process;
-
-
- process(current_state, token_tdc_readout_i, reg_first_header, almost_full_flag_fee_data_fifo_i,
- INIT_TDC_READOUT_IN)
- begin
-
- next_write_header_fifo_i <= '0';
- next_debug_register_fsm_header <= (others => '0');
- next_lvl1_busy_i <= '0';
- data_header_fifo_in_i <= reg_first_header;
- clear_counter_error_token_back <= '0';
- next_state <= current_state;
-
- case current_state is
-
--------------------------------------------------------------------------------
--- with INIT_TDC_READOUT_IN(0) = '1' the timing trigger has been sended, the
--- TDCs deliver data and the HEADER is build and written into the fifo after TOKEN
--- and LVL1 info has been read.
--------------------------------------------------------------------------------
- when idle_state =>
- next_debug_register_fsm_header <= x"00";
- next_write_header_fifo_i <= '0';
- data_header_fifo_in_i <= reg_first_header;
- next_lvl1_busy_i <= '0';
- if (INIT_TDC_READOUT_IN(0) = '1') then
- next_state <= wait_for_token;
+ proc_fifo_write_fsm_reg : process (CLK)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ current_state <= idle_state;
+ reg_debug_register_fsm_header <= (others => '0');
+ write_header_fifo_i <= '0';
+ reg_lvl1_busy_i <= '0';
else
- next_state <= idle_state;
+ current_state <= next_state;
+ reg_debug_register_fsm_header <= next_debug_register_fsm_header;
+ write_header_fifo_i <= next_write_header_fifo_i;
+ reg_lvl1_busy_i <= next_lvl1_busy_i;
end if;
+ end if;
+ end process;
------------------------------------------------------------------------
---WAIT FOR TOKEN:
---I have to wait the event which is being collected is complete.
---When the event is complete the header is generated and loaded
---in the fifo.
---When I wait in this state the TDC data is written in the data_fifo.
------------------------------------------------------------------------
- when wait_for_token =>
- next_debug_register_fsm_header <= x"02";
- next_write_header_fifo_i <= '0';
- data_header_fifo_in_i <= reg_first_header;
- next_lvl1_busy_i <= '1';
- --are we sure firt we get the timing trigger and then lvl1 info???
- if (token_tdc_readout_i(0) = '1' and almost_full_flag_fee_data_fifo_i = '0' and reg_lvl1_trg_received = '1') then
- next_state <= send_second_header_state;
- elsif (token_tdc_readout_i(0) = '1' and almost_full_flag_fee_data_fifo_i = '1') then
- next_state <= busy_header_state;
- else
- next_state <= wait_for_token;
- end if;
--------------------------------------------------------------------------------
--- SEND HEADER
--------------------------------------------------------------------------------
- when send_second_header_state =>
- next_debug_register_fsm_header <= x"03";
- next_write_header_fifo_i <= '1'; --write in header fifo
- data_header_fifo_in_i <= reg_first_header;
- next_lvl1_busy_i <= '1';
- next_state <= idle_state;
-
- when busy_header_state =>
- next_debug_register_fsm_header <= x"04";
- next_write_header_fifo_i <= '0';
- data_header_fifo_in_i <= reg_first_header;
- next_lvl1_busy_i <= '1';
- clear_counter_error_token_back <= '1';
- if (almost_full_flag_fee_data_fifo_i = '0') then
- -- clear_counter_pulse_not_empty <= '1';
- next_state <= send_second_header_state;
- else
- next_state <= busy_header_state;
- end if;
+ proc_fifo_write_fsm : process (current_state, token_tdc_readout_i, reg_lvl1_trg_received,
+ almost_full_flag_fee_data_fifo_i, INIT_TDC_READOUT_IN, reg_lvl1_busy_i)
+ begin
+
+ next_write_header_fifo_i <= '0';
+ next_debug_register_fsm_header <= (others => '0');
+ next_lvl1_busy_i <= reg_lvl1_busy_i;
+ clear_counter_error_token_back <= '0';
+ next_state <= current_state;
+
+ case current_state is
+ --wait for start of trigger
+ when idle_state =>
+ next_debug_register_fsm_header <= x"00";
+ next_lvl1_busy_i <= '0';
+ if (INIT_TDC_READOUT_IN(0) = '1') then
+ next_state <= wait_for_token;
+ next_lvl1_busy_i <= '1';
+ end if;
+
+ --wait for token back
+ when wait_for_token =>
+ next_debug_register_fsm_header <= x"01";
+ if token_tdc_readout_i(0) = '0' then --stuck when no token back!
+ next_state <= wait_for_token;
+ elsif reg_lvl1_trg_received = '0' then
+ next_state <= wait_for_lvl1_information;
+ elsif almost_full_flag_fee_data_fifo_i = '0' then
+ next_state <= send_second_header_state;
+ else
+ next_state <= busy_header_state;
+ end if;
+
+ -- Waiting for necessities
+ when wait_for_lvl1_information =>
+ next_debug_register_fsm_header <= x"07";
+ if reg_lvl1_trg_received = '1' then
+ if almost_full_flag_fee_data_fifo_i = '0' then
+ next_state <= send_second_header_state;
+ else
+ next_state <= busy_header_state;
+ end if;
+ end if;
+
+ when busy_header_state =>
+ next_debug_register_fsm_header <= x"06";
+ clear_counter_error_token_back <= '1'; --????? why in this state?
+ if (almost_full_flag_fee_data_fifo_i = '0') then
+ -- clear_counter_pulse_not_empty <= '1';
+ next_state <= send_second_header_state;
+ end if;
+
+ -- write header
+ when send_second_header_state =>
+ next_debug_register_fsm_header <= x"02";
+ next_write_header_fifo_i <= '1';
+ next_state <= idle_state;
+
+ when others =>
+ next_debug_register_fsm_header <= x"0F";
+ next_lvl1_busy_i <= '0';
+ next_state <= idle_state;
+ end case;
+ end process;
- when others =>
- next_debug_register_fsm_header <= x"00";
- next_write_header_fifo_i <= '0';
- data_header_fifo_in_i <= reg_first_header;
- next_lvl1_busy_i <= '0';
- next_state <= idle_state;
- end case;
- end process;
-----------------------------------------------------------------------------
-- Syncronization and reset FSM_FIFO_MULTIPLEXER
-----------------------------------------------------------------------------
- process (CLK, RESET)
- begin
- if (rising_edge(CLK)) then
- if RESET = '1' then
- current_state_fsm_multiplexer <= idle_state_fsm_multiplexer;
- reg_debug_register_fsm_multiplexer <= (others => '0');
- reg_ipu_finished <= '0';
- else
- current_state_fsm_multiplexer <= next_state_fsm_multiplexer;
- reg_debug_register_fsm_multiplexer <= next_debug_register_fsm_multiplexer;
- reg_flag_in_header <= next_flag_in_header;
- reg_ipu_error_pattern <= next_ipu_error_pattern;
- reg_ipu_finished <= next_ipu_finished;
+ proc_reg_write_to_ipu : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ current_state_fsm_multiplexer <= idle_state_fsm_multiplexer;
+ reg_debug_register_fsm_multiplexer <= (others => '0');
+ reg_ipu_finished <= '0';
+ else
+ current_state_fsm_multiplexer <= next_state_fsm_multiplexer;
+ reg_debug_register_fsm_multiplexer <= next_debug_register_fsm_multiplexer;
+ reg_flag_in_header <= next_flag_in_header;
+ reg_ipu_finished <= next_ipu_finished;
+ end if;
end if;
- end if;
- end process;
+ end process;
-------------------------------------------------------------------------------
-- FSM_FIFO_MULTIPLEXER:
-- this fsm multiplex data and header into TRB net entity.
-------------------------------------------------------------------------------
-process(current_state_fsm_multiplexer, header_data_fifo_out_i, reg_ipu_start_readout_in,
- empty_flag_header_data_fifo_i, last_read_header_fifo, IPU_READ_IN, reg_flag_in_header,
- fee_data_fifo_out_i, fee_data_fifo_data_valid, last_read_fee_data_fifo,
- empty_flag_fee_data_fifo_i, reg_ipu_error_pattern)
- begin
- next_state_fsm_multiplexer <= current_state_fsm_multiplexer;
- next_debug_register_fsm_multiplexer <= (others => '0');
- read_fee_data_fifo <= '0';
- read_header_fifo <= '0';
- next_ipu_dataready <= '0';
- next_ipu_finished <= '0';
- next_flag_in_header<= reg_flag_in_header;
- next_ipu_data <= header_data_fifo_out_i(31 downto 0);
- --next_ipu_error_pattern <= reg_ipu_error_pattern;
-
- case current_state_fsm_multiplexer is
- when idle_state_fsm_multiplexer =>
- -- next_ipu_error_pattern <= (others => '0');
- next_debug_register_fsm_multiplexer <= x"00";
- if (reg_ipu_start_readout_in = '1' and empty_flag_header_data_fifo_i = '0') then
- read_header_fifo <= '1';
- next_state_fsm_multiplexer <= wait_for_header_fifo_ready;
- end if;
+ proc_write_to_ipu_channel : process(current_state_fsm_multiplexer, header_data_fifo_out_i,
+ reg_ipu_start_readout_in, empty_flag_header_data_fifo_i,
+ last_read_header_fifo, IPU_READ_IN, reg_flag_in_header,
+ fee_data_fifo_out_i, fee_data_fifo_data_valid,
+ last_read_fee_data_fifo, empty_flag_fee_data_fifo_i)
+ begin
+ next_state_fsm_multiplexer <= current_state_fsm_multiplexer;
+ next_debug_register_fsm_multiplexer <= (others => '0');
+ read_fee_data_fifo <= '0';
+ read_header_fifo <= '0';
+ next_ipu_dataready <= '0';
+ next_ipu_finished <= '0';
+ next_flag_in_header<= reg_flag_in_header;
+ next_ipu_data <= header_data_fifo_out_i(31 downto 0);
+
+ case current_state_fsm_multiplexer is
+ when idle_state_fsm_multiplexer =>
+ next_debug_register_fsm_multiplexer <= x"00";
+ if (reg_ipu_start_readout_in = '1' and empty_flag_header_data_fifo_i = '0') then
+ read_header_fifo <= '1';
+ next_state_fsm_multiplexer <= wait_for_header_fifo_ready;
+ end if;
- when wait_for_header_fifo_ready =>
- if last_read_header_fifo = '1' then
- next_state_fsm_multiplexer <= send_first_and_second_header_state_fsm_multiplexer;
- end if;
+ when wait_for_header_fifo_ready =>
+ if last_read_header_fifo = '1' then
+ next_state_fsm_multiplexer <= send_first_and_second_header_state_fsm_multiplexer;
+ end if;
- when send_first_and_second_header_state_fsm_multiplexer =>
- next_ipu_data <= header_data_fifo_out_i(31 downto 0);
- next_flag_in_header <= header_data_fifo_out_i(35 downto 32);
- next_ipu_dataready <= '1';
- if IPU_READ_IN = '1' then
- next_state_fsm_multiplexer <= send_data_state_fsm_multiplexer;
- if fee_data_fifo_data_valid = '0' then
- read_fee_data_fifo <= '1';
+ when send_first_and_second_header_state_fsm_multiplexer =>
+ next_ipu_data <= header_data_fifo_out_i(31 downto 0);
+ next_flag_in_header <= header_data_fifo_out_i(35 downto 32);
+ next_ipu_dataready <= '1';
+ if IPU_READ_IN = '1' then
+ next_state_fsm_multiplexer <= send_data_state_fsm_multiplexer;
+ if fee_data_fifo_data_valid = '0' then
+ read_fee_data_fifo <= '1';
+ end if;
end if;
- end if;
- when send_data_state_fsm_multiplexer =>
- next_ipu_data <= fee_data_fifo_out_i(31 downto 0);
- next_ipu_dataready <= fee_data_fifo_data_valid;
- read_fee_data_fifo <= IPU_READ_IN or (not fee_data_fifo_data_valid and not last_read_fee_data_fifo);
+ when send_data_state_fsm_multiplexer =>
+ next_ipu_data <= fee_data_fifo_out_i(31 downto 0);
+ next_ipu_dataready <= fee_data_fifo_data_valid;
+ read_fee_data_fifo <= IPU_READ_IN or (not fee_data_fifo_data_valid and not last_read_fee_data_fifo);
- if (empty_flag_fee_data_fifo_i = '1' and last_read_fee_data_fifo = '0' and fee_data_fifo_data_valid = '0')
- or ( fee_data_fifo_out_i(35 downto 32) /= reg_flag_in_header and fee_data_fifo_data_valid = '1') then
- next_state_fsm_multiplexer <= end_of_event_transfer_fsm_multiplexer;
- next_ipu_dataready <= '0';
- next_ipu_finished <= '1';
- end if;
+ if (empty_flag_fee_data_fifo_i = '1' and last_read_fee_data_fifo = '0' and fee_data_fifo_data_valid = '0')
+ or ( fee_data_fifo_out_i(35 downto 32) /= reg_flag_in_header and fee_data_fifo_data_valid = '1') then
+ next_state_fsm_multiplexer <= end_of_event_transfer_fsm_multiplexer;
+ next_ipu_dataready <= '0';
+ next_ipu_finished <= '1';
+ end if;
- when end_of_event_transfer_fsm_multiplexer =>
- if reg_ipu_start_readout_in = '0' then
- next_state_fsm_multiplexer <= idle_state_fsm_multiplexer;
- end if;
+ when end_of_event_transfer_fsm_multiplexer =>
+ if reg_ipu_start_readout_in = '0' then
+ next_state_fsm_multiplexer <= idle_state_fsm_multiplexer;
+ end if;
- end case;
- end process;
+ end case;
+ end process;
PROC_FIFO_DATA_VALID : process(CLK)
-- For each event I generate a flag (4 bits), which will be used to distinguish
-- the events. The flag marks the dataword and the header.
-------------------------------------------------------------------------------
- process (CLK, RESET, pulse_init_tdc_readout)
- begin
- if (rising_edge(CLK)) then
- if RESET = '1' then
- flag_event_counter <= (others => '0');
- elsif (pulse_init_tdc_readout = '1') then
- flag_event_counter <= flag_event_counter + 1;
- end if;
- end if;
- end process;
+-- proc_event_flag_counter : process (CLK, RESET, pulse_init_tdc_readout)
+-- begin
+-- if (rising_edge(CLK)) then
+-- if RESET = '1' then
+-- flag_event_counter <= (others => '0');
+-- elsif (pulse_init_tdc_readout = '1') then
+-- flag_event_counter <= flag_event_counter + 1;
+-- end if;
+-- end if;
+-- end process;
--use bigger width, compare to trbnet trigger number
-- I see which trigger has been processed and I store it. I use this
-- information in the first dataword
-------------------------------------------------------------------------------
-init_tdc_readout_i <= x"0";
-
-process (CLK)
-begin
- if rising_edge(CLK) then
- if RESET = '1' then
- reg_trigger_type <= (others => '0');
- elsif init_tdc_readout_i = x"1" then --normal trigger
- reg_trigger_type <= x"1";
- elsif init_tdc_readout_i = x"9" then --calibration trigger
- reg_trigger_type <= x"9";
- end if;
- end if;
-end process;
+-- init_tdc_readout_i <= x"0";
+--
+-- proc_trigger_type : process (CLK)
+-- begin
+-- if rising_edge(CLK) then
+-- if RESET = '1' then
+-- reg_trigger_type <= (others => '0');
+-- elsif init_tdc_readout_i = x"1" then --normal trigger
+-- reg_trigger_type <= x"1";
+-- elsif init_tdc_readout_i = x"9" then --calibration trigger
+-- reg_trigger_type <= x"9";
+-- end if;
+-- end if;
+-- end process;
reg_ipu_information <= IPU_INFORMATION_IN;
--start strobe
reg_ipu_start_readout_in <= IPU_START_READOUT_IN;
+ internal_trigger_number <= LVL1_INT_TRG_NUMBER_OUT;
-- end if;
-- end if;
-- end process;
--------------------------------------------------------------------------------
--- check if the timing trigger received and the LVL1 trigger are the same
--------------------------------------------------------------------------------
- process (CLK)
- begin
- if (rising_edge(CLK)) then
- if (RESET = '1') then
- counter_timing_trigger <= (others => '0');
- elsif (pulse_init_tdc_readout = '1') then
- counter_timing_trigger <= counter_timing_trigger + 1;
- else
- counter_timing_trigger <= counter_timing_trigger;
- end if;
- end if;
- end process;
-
-------------------------------------------------------------------------------
-- write debug info in the data header event
-------------------------------------------------------------------------------
- error_data_header_info_i(0) <= '1' when (counter_error_token_back(0) = '1') else '0';--TOKEN NOT BACK
+ error_data_header_info_i(0) <= '1' when (counter_error_token_back(0) = '1') else '0';--TOKEN NOT BACK
+
+ error_data_header_info_i(1) <= '1';
+ error_data_header_info_i(19 downto 2) <= (others => '0');
- error_data_header_info_i(1) <= '1'; --test
-------------------------------------------------------------------------------
-- decoder debug info in the data header event for error pattern
-------------------------------------------------------------------------------
- process (CLK)
- begin
- if (rising_edge(CLK)) then
- if (RESET = '1' or next_ipu_finished = '1') then
- next_ipu_error_pattern <= (others => '0');
- elsif (last_read_header_fifo = '1') then
- next_ipu_error_pattern(25) <= header_data_fifo_out_i(52); --TOKEN NOT BACK
- next_ipu_error_pattern(26) <= header_data_fifo_out_i(53); --TEST
- else
- next_ipu_error_pattern <= next_ipu_error_pattern;
- end if;
- end if;
- end process;
-
+ proc_ipu_error_pattern : process (CLK)
+ begin
+ if (rising_edge(CLK)) then
+ if (RESET = '1' or reg_ipu_finished = '1') then
+ reg_ipu_error_pattern <= (others => '0');
+ elsif (last_read_header_fifo = '1') then
+ reg_ipu_error_pattern(25) <= header_data_fifo_out_i(52); --TOKEN NOT BACK
+-- reg_ipu_error_pattern(26) <= header_data_fifo_out_i(53); --TEST
+ end if;
+ end if;
+ end process;
+
-------------------------------------------------------------------------------
-- counter token not back
-------------------------------------------------------------------------------
- process (CLK)
- begin
- if (rising_edge(CLK)) then
- if (RESET = '1' or clear_counter_error_token_back = '1') then
- counter_error_token_back <= (others => '0');
- elsif (TOKEN_IN = x"2") then
- counter_error_token_back <= counter_error_token_back + 1;
- else
- counter_error_token_back <= counter_error_token_back;
- end if;
- end if;
- end process;
-
--------------------------------------------------------------------------------
--- PROCESS to count how many word the TRB net reads from the FIFO_HADER
--------------------------------------------------------------------------------
-process (CLK)
-begin
- if (rising_edge(CLK)) then
- if (RESET = '1') then
- counter_word_read_from_trbnet <= (others => '0');
- elsif read_fee_data_fifo = '1' then
- counter_word_read_from_trbnet <= counter_word_read_from_trbnet + 1;
- end if;
- end if;
-end process;
+--why do you need a 12bit counter here?
+ proc_count_token_errors : process (CLK)
+ begin
+ if (rising_edge(CLK)) then
+ if (RESET = '1' or clear_counter_error_token_back = '1') then
+ counter_error_token_back <= (others => '0');
+ elsif (TOKEN_IN = x"2") then --token in is only one clock cycle long
+ counter_error_token_back <= counter_error_token_back + 1;
+ end if;
+ end if;
+ end process;
+
+-------------------------------------------------------------------------------
+-- PROCESS to count how many word the TRB net reads from the data FIFO
+-------------------------------------------------------------------------------
+ proc_count_read_dataw_words : process (CLK)
+ begin
+ if (rising_edge(CLK)) then
+ if (RESET = '1') then
+ counter_word_read_from_trbnet <= (others => '0');
+ elsif read_fee_data_fifo = '1' then
+ counter_word_read_from_trbnet <= counter_word_read_from_trbnet + 1;
+ end if;
+ end if;
+ end process;
-------------------------------------------------------------------------------
-- Keep track of read operations
-----------------------------------------------------------------------------
-
- PROC_REG_READ_SIGS : process(CLK)
+ proc_reg_read_sigs : process(CLK)
begin
if rising_edge(CLK) then
last_read_header_fifo <= read_header_fifo;
last_read_fee_data_fifo <= read_fee_data_fifo and not empty_flag_fee_data_fifo_i;
last2_read_fee_data_fifo <= last_read_fee_data_fifo;
-
end if;
end process;
-------------------------------------------------------------------------------
-
-
-
-------------------------------------------------------------------------------
-- Debug
-------------------------------------------------------------------------------
use work.trb_net_components.all;
use work.version.all;
+
+---------------------------------------------------------------------
+-- Memory Map
+---------------------------------------------------------------------
+-- Data Bus Handler full range: 8000 - FFFF
+-- 8000 - 80FF ADC (1)
+-- D000 - D13F SPI (2-3)
+-- D200 Flash Select (4)
+-- A000 - A0FF Threshold Bytes (0)
+--
+-- 0x20 Bit 0 -> reset internal logic
+-- 0x20 Bit 15 -> reboot fpga
+-- 0x20 Bit 16 -> pseudo timing trigger
+-- 0x20 Bit 24 -> begin run trigger
+--
+-- 0xc0 0x0010 -> select short
+-- 0xc0 0x0020 -> select long
+-- 0xc1 0x0C10 -> x"C" set calibration trigger, x"0" normal
+-- 0xc1 0x0000 -> select verbose mode data
+-- 0xc1 0x1000 -> select compact mode data
+-- 0xc1 0x2000 -> select test data
+-- 0xc1 0x0ABC0000 -> x"ABC" number of test data words
+-- 0xc1 0x10000000 -> x"1" external cms
+-- 0xc1 0x00000000 -> x"0" internal generated cms
+---------------------------------------------------------------------
+---------------------------------------------------------------------
+
entity mdc_oepb is
+ generic(
+ INCLUDE_READOUT : integer range 0 to 1 := c_YES
+ );
port(
--Clocks
CLK : in std_logic;
SPI_DIN : in std_logic;
SPI_DOUT : out std_logic;
--MB
- --MRES : out std_logic; --global reset
TAOD : inout std_logic; --address or data
TACK : in std_logic; --MB address
CMS : out std_logic; --common stop
- COM_STOP_P : in std_logic; --common stop input from transceiner
+ COM_STOP_P : in std_logic; --common stop input from transceiver
TDST : inout std_logic; --data strobe
GDE : out std_logic; --global disable
RDYI : out std_logic; --ready TO first motherboard token out to MB (on AddOn RDM)
RES : out std_logic; -- TDC working mode
TOK : out std_logic; -- TDC working mode
WRM : out std_logic; -- TDC working mode
- TAD : inout std_logic_vector(8 downto 0) --TAD 8 downto 0
+ TAD : inout std_logic_vector(8 downto 0); --TAD 8 downto 0
+ J2_P : out std_logic
);
end entity;
signal LVL1_TRG_RECEIVED_OUT : std_logic;
signal LVL1_TRG_NUMBER_OUT : std_logic_vector(15 downto 0);
signal LVL1_TRG_CODE_OUT : std_logic_vector(7 downto 0);
- signal LVL1_TRG_INFORMATION_OUT : std_logic_vector(7 downto 0);
+ signal LVL1_TRG_INFORMATION_OUT : std_logic_vector(23 downto 0);
signal LVL1_ERROR_PATTERN_IN : std_logic_vector(31 downto 0);
signal LVL1_TRG_RELEASE_IN : std_logic;
+ signal LVL1_INT_TRG_NUMBER_OUT : std_logic_vector(15 downto 0);
signal IPU_NUMBER_OUT : std_logic_vector(15 downto 0);
signal IPU_INFORMATION_OUT : std_logic_vector(7 downto 0);
signal local_time : std_logic_vector(7 downto 0);
signal time_since_last_trg : std_logic_vector(31 downto 0);
signal timer_microsecond_tick : std_logic;
- signal trigger_monitor : std_logic;
+-- signal trigger_monitor : std_logic;
signal reg_REGIO_ADDR : std_logic_vector(15 downto 0);
signal reg_REGIO_READ : std_logic;
signal data_type_select_in_i : std_logic_vector(15 downto 0);
signal test_debug_i : std_logic_vector(7 downto 0);
- signal counter_led : unsigned(31 downto 0);
- signal test_pseudo_signal_i : std_logic;
+-- signal counter_led : unsigned(31 downto 0);
+-- signal test_pseudo_signal_i : std_logic;
signal delayed_restart_fpga : std_logic;
signal restart_fpga_counter : unsigned(11 downto 0);
signal reg_CS : std_logic_vector(2 downto 1);
signal real_flash_rom_select : std_logic_vector(1 downto 0);
-
+ signal COMMON_CTRL_REG_STROBE : std_logic_vector(std_COMCTRLREG-1 downto 0);
-- signal flash_mem_data : std_logic_vector(31 downto 0);
-- signal flash_mem_data_out : std_logic_vector(31 downto 0);
signal reset_mdc_addon_daq_bus_0, pulse_reset_internal_logic : std_logic;
+ type dummy_state_t is (IDLE, SEND_DHDR, WAIT_FOR_FINISHED);
+ signal dummy_state : dummy_state_t;
signal cms_select_in_i: std_logic_vector (3 downto 0);
signal a_cms_i : std_logic;
+ signal cms_counter : unsigned(3 downto 0);
+ signal cms_output : std_logic;
+
-- signal input_parity_gen : std_logic_vector(9 downto 0);
-- type tt is array (3000 downto 0) of std_logic_vector(3 downto 0);
THE_RESET_COUNTER_PROC: process(CLK)
begin
if rising_edge(CLK) then
- if MED_STAT_OP(13) = '1' or pll_locked = '0' then
+ if MED_STAT_OP(13) = '1' or pll_locked = '0' then --pll not locked or reset request received
reset_counter <= x"000F00";
reset_internal <= '1';
reset_startup <= '1';
- elsif MED_STAT_OP(14) = '1' then
+ elsif MED_STAT_OP(14) = '1' then --no cable connected
reset_counter <= x"000F00";
reset_startup <= '0';
reset_internal <= '1';
- elsif( reset_counter = x"000FEF" ) then
+ elsif( reset_counter = x"000FEF" ) then --end of reset cycle reached
reset_startup <= '0';
reset_internal <= '0';
reset_counter <= x"000FEF";
- else
+ else --update reset counter
reset_counter <= reset_counter + "1";
reset_internal <= '1';
end if;
---------------------------------------------------------------------
--- Flash FF
+-- Restart FPGA
---------------------------------------------------------------------
end process;
+---------------------------------------------------------------------
+-- Select Flash FF
+---------------------------------------------------------------------
+
PROC_CONTRL_FLASH_SELECT : process (CLK_100)
begin
if rising_edge(CLK_100) then
next_flash_rom_clk <= '0';
end if;
end if;
- end process;
+ end process PROC_CONTRL_FLASH_SELECT;
CLK_FF <= flash_rom_clk;
DATA_FF <= flash_rom_select;
--set to 0 for unused ctrl registers to save resources
REGIO_USED_CTRL_REGS => (others => '1'),
REGIO_USED_CTRL_BITMASK => (others => '1'),
- ADDRESS_MASK => x"FEFF",
+ ADDRESS_MASK => x"F37F",
BROADCAST_BITMASK => x"FD",
REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,32)),
CLOCK_FREQUENCY => 100
MED_READ_OUT => MED_READ_OUT,
MED_STAT_OP_IN => MED_STAT_OP,
MED_CTRL_OP_OUT => MED_CTRL_OP,
+
-- LVL1 trigger APL
LVL1_TRG_TYPE_OUT => LVL1_TRG_TYPE_OUT,
LVL1_TRG_RECEIVED_OUT => LVL1_TRG_RECEIVED_OUT,
LVL1_TRG_INFORMATION_OUT => LVL1_TRG_INFORMATION_OUT,
LVL1_ERROR_PATTERN_IN => LVL1_ERROR_PATTERN_IN,
LVL1_TRG_RELEASE_IN => LVL1_TRG_RELEASE_IN,
+ LVL1_INT_TRG_NUMBER_OUT => LVL1_INT_TRG_NUMBER_OUT,
--Data Port
IPU_NUMBER_OUT => IPU_NUMBER_OUT,
REGIO_REGISTERS_IN => REGIO_REGISTERS_IN, --start 0x80
REGIO_REGISTERS_OUT => REGIO_REGISTERS_OUT, --start 0xc0
+ COMMON_CTRL_REG_STROBE => COMMON_CTRL_REG_STROBE,
+
--following ports only used when using internal data port
REGIO_ADDR_OUT => REGIO_ADDR_OUT,
REGIO_READ_ENABLE_OUT => REGIO_READ_ENABLE_OUT,
REGIO_IDRAM_ADDR_IN <= (others => '0');
REGIO_IDRAM_WR_IN <= '0';
--- Memory map:
--- full range: 8000 - FFFF
--- 8000 - 80FF ADC (1)
--- D000 - D13F SPI (2-3)
--- D200 Flash Select (4)
--- A000 - A0FF Threshold Bytes (0)
-THE_REG_DAT_ADDR : process(CLK_100)
+ THE_REG_DAT_ADDR : process(CLK_100)
begin
if rising_edge(CLK_100) then
if (REGIO_READ_ENABLE_OUT = '1' or REGIO_WRITE_ENABLE_OUT = '1') then
end if;
end process;
-THE_REGIO_BUS_HANDLER : trb_net16_regio_bus_handler
- generic map(
- PORT_NUMBER => 5,
--- PORT_ADDRESSES => (0 => x"A000", 1 => x"8000", 2 => x"9000", others => x"0000"),
--- PORT_ADDR_MASK => (0 => 8, 1 => 6, 2 => 8, others => 0)
- PORT_ADDRESSES => (0 => x"A000", 1 => x"8000", 2 => x"d000", 3 => x"d100", 4 => x"d200", others => x"0000"),
- PORT_ADDR_MASK => (0 => 8, 1 => 6, 2 => 1, 3 => 6, 4 => 0, others => 0)
- )
- port map(
- CLK => CLK_100,
- RESET => reset_internal,
- --I/O to RegIO
- DAT_ADDR_IN => REGIO_ADDR_OUT,
- DAT_DATA_IN => REGIO_DATA_OUT,
- DAT_DATA_OUT => REGIO_DATA_IN,
- DAT_READ_ENABLE_IN => REGIO_READ_ENABLE_OUT,
- DAT_WRITE_ENABLE_IN => REGIO_WRITE_ENABLE_OUT,
- DAT_TIMEOUT_IN => REGIO_TIMEOUT_OUT,
- DAT_DATAREADY_OUT => REGIO_DATAREADY_IN,
- DAT_WRITE_ACK_OUT => REGIO_WRITE_ACK_IN,
- DAT_NO_MORE_DATA_OUT => REGIO_NO_MORE_DATA_IN,
- DAT_UNKNOWN_ADDR_OUT => REGIO_UNKNOWN_ADDR_IN,
- --Bus Handler (Threshold memory)
- BUS_READ_ENABLE_OUT(0) => thresh_mem_read,
- BUS_WRITE_ENABLE_OUT(0) => thresh_mem_write,
- BUS_DATA_OUT(0*32+15 downto 0*32) => thresh_mem_data,
- BUS_DATA_OUT(0*32+31 downto 0*32+16)=> open,
- BUS_ADDR_OUT(0*16+8 downto 0*16) => thresh_mem_addr,
- BUS_ADDR_OUT(0*16+15 downto 0*16+9) => open,
- BUS_TIMEOUT_OUT(0) => open,
- BUS_DATA_IN(0*32+15 downto 0*32) => thresh_mem_data_out,
- BUS_DATA_IN(0*32+31 downto 0*32+16) => x"0000",
- BUS_DATAREADY_IN(0) => very_last_reg_REGIO_READ,
- BUS_WRITE_ACK_IN(0) => reg_REGIO_WRITE,
- BUS_NO_MORE_DATA_IN(0) => '0',
- BUS_UNKNOWN_ADDR_IN(0) => '0',
- --Bus Handler (ADC)
- BUS_READ_ENABLE_OUT(1) => adc_read,
- BUS_WRITE_ENABLE_OUT(1) => adc_write,
- BUS_DATA_OUT(1*32+31 downto 1*32) => adc_data_in,
- BUS_ADDR_OUT(1*16+5 downto 1*16) => adc_addr,
- BUS_ADDR_OUT(1*16+15 downto 1*16+6) => open,
- BUS_TIMEOUT_OUT(1) => adc_timeout,
- BUS_DATA_IN(1*32+31 downto 1*32) => adc_data_out,
- BUS_DATAREADY_IN(1) => adc_dataready,
- BUS_WRITE_ACK_IN(1) => adc_write_ack,
- BUS_NO_MORE_DATA_IN(1) => adc_no_more_data,
- BUS_UNKNOWN_ADDR_IN(1) => adc_unknown_addr,
--- --Bus Handler (SPI-FLASH)
--- BUS_READ_ENABLE_OUT(2) => flash_mem_read,
--- BUS_WRITE_ENABLE_OUT(2) => flash_mem_write,
--- BUS_DATA_OUT(2*32+31 downto 2*32) => flash_mem_data,
--- BUS_ADDR_OUT(2*16+8 downto 2*16) => flash_mem_addr,
--- BUS_ADDR_OUT(2*16+15 downto 2*16+9) => open,
--- BUS_TIMEOUT_OUT(2) => open,
--- BUS_DATA_IN(2*32+31 downto 2*32) => flash_mem_data_out,
--- BUS_DATAREADY_IN(2) => very_last_reg_REGIO_READ,
--- BUS_WRITE_ACK_IN(2) => reg_REGIO_WRITE,
--- BUS_NO_MORE_DATA_IN(2) => '0',
--- BUS_UNKNOWN_ADDR_IN(2) => '0',
- --Bus Handler (SPI CTRL)
- BUS_READ_ENABLE_OUT(2) => spictrl_read_en,
- BUS_WRITE_ENABLE_OUT(2) => spictrl_write_en,
- BUS_DATA_OUT(2*32+31 downto 2*32) => spictrl_data_in,
- BUS_ADDR_OUT(2*16) => spictrl_addr,
- BUS_ADDR_OUT(2*16+15 downto 2*16+1) => open,
- BUS_TIMEOUT_OUT(2) => open,
- BUS_DATA_IN(2*32+31 downto 2*32) => spictrl_data_out,
- BUS_DATAREADY_IN(2) => spictrl_ack,
- BUS_WRITE_ACK_IN(2) => spictrl_ack,
- BUS_NO_MORE_DATA_IN(2) => spictrl_busy,
- BUS_UNKNOWN_ADDR_IN(2) => '0',
- --Bus Handler (SPI Memory)
- BUS_READ_ENABLE_OUT(3) => spimem_read_en,
- BUS_WRITE_ENABLE_OUT(3) => spimem_write_en,
- BUS_DATA_OUT(3*32+31 downto 3*32) => spimem_data_in,
- BUS_ADDR_OUT(3*16+5 downto 3*16) => spimem_addr,
- BUS_ADDR_OUT(3*16+15 downto 3*16+6) => open,
- BUS_TIMEOUT_OUT(3) => open,
- BUS_DATA_IN(3*32+31 downto 3*32) => spimem_data_out,
- BUS_DATAREADY_IN(3) => spimem_ack,
- BUS_WRITE_ACK_IN(3) => spimem_ack,
- BUS_NO_MORE_DATA_IN(3) => '0',
- BUS_UNKNOWN_ADDR_IN(3) => '0',
- --Flash ROM select
- BUS_READ_ENABLE_OUT(4) => flash_rom_read,
- BUS_WRITE_ENABLE_OUT(4) => flash_rom_write,
- BUS_DATA_OUT(4*32) => next_flash_rom_select,
- BUS_DATA_OUT(4*32+31 downto 4*32+1) => open,
- BUS_ADDR_OUT(4*16+15 downto 4*16) => open,
- BUS_TIMEOUT_OUT(4) => open,
- BUS_DATA_IN(4*32+1 downto 4*32) => real_flash_rom_select,
- BUS_DATA_IN(4*32+31 downto 4*32+2) => (others => '0'),
- BUS_DATAREADY_IN(4) => flash_rom_read,
- BUS_WRITE_ACK_IN(4) => flash_rom_write,
- BUS_NO_MORE_DATA_IN(4) => '0',
- BUS_UNKNOWN_ADDR_IN(4) => '0',
- --Debugging
- STAT_DEBUG => open
- );
+ THE_REGIO_BUS_HANDLER : trb_net16_regio_bus_handler
+ generic map(
+ PORT_NUMBER => 5,
+ PORT_ADDRESSES => (0 => x"A000", 1 => x"8000", 2 => x"d000", 3 => x"d100", 4 => x"d200", others => x"0000"),
+ PORT_ADDR_MASK => (0 => 8, 1 => 6, 2 => 1, 3 => 6, 4 => 0, others => 0)
+ )
+ port map(
+ CLK => CLK_100,
+ RESET => reset_internal,
+ --I/O to RegIO
+ DAT_ADDR_IN => REGIO_ADDR_OUT,
+ DAT_DATA_IN => REGIO_DATA_OUT,
+ DAT_DATA_OUT => REGIO_DATA_IN,
+ DAT_READ_ENABLE_IN => REGIO_READ_ENABLE_OUT,
+ DAT_WRITE_ENABLE_IN => REGIO_WRITE_ENABLE_OUT,
+ DAT_TIMEOUT_IN => REGIO_TIMEOUT_OUT,
+ DAT_DATAREADY_OUT => REGIO_DATAREADY_IN,
+ DAT_WRITE_ACK_OUT => REGIO_WRITE_ACK_IN,
+ DAT_NO_MORE_DATA_OUT => REGIO_NO_MORE_DATA_IN,
+ DAT_UNKNOWN_ADDR_OUT => REGIO_UNKNOWN_ADDR_IN,
+ --Bus Handler (Threshold memory)
+ BUS_READ_ENABLE_OUT(0) => thresh_mem_read,
+ BUS_WRITE_ENABLE_OUT(0) => thresh_mem_write,
+ BUS_DATA_OUT(0*32+15 downto 0*32) => thresh_mem_data,
+ BUS_DATA_OUT(0*32+31 downto 0*32+16)=> open,
+ BUS_ADDR_OUT(0*16+8 downto 0*16) => thresh_mem_addr,
+ BUS_ADDR_OUT(0*16+15 downto 0*16+9) => open,
+ BUS_TIMEOUT_OUT(0) => open,
+ BUS_DATA_IN(0*32+15 downto 0*32) => thresh_mem_data_out,
+ BUS_DATA_IN(0*32+31 downto 0*32+16) => x"0000",
+ BUS_DATAREADY_IN(0) => very_last_reg_REGIO_READ,
+ BUS_WRITE_ACK_IN(0) => reg_REGIO_WRITE,
+ BUS_NO_MORE_DATA_IN(0) => '0',
+ BUS_UNKNOWN_ADDR_IN(0) => '0',
+ --Bus Handler (ADC)
+ BUS_READ_ENABLE_OUT(1) => adc_read,
+ BUS_WRITE_ENABLE_OUT(1) => adc_write,
+ BUS_DATA_OUT(1*32+31 downto 1*32) => adc_data_in,
+ BUS_ADDR_OUT(1*16+5 downto 1*16) => adc_addr,
+ BUS_ADDR_OUT(1*16+15 downto 1*16+6) => open,
+ BUS_TIMEOUT_OUT(1) => adc_timeout,
+ BUS_DATA_IN(1*32+31 downto 1*32) => adc_data_out,
+ BUS_DATAREADY_IN(1) => adc_dataready,
+ BUS_WRITE_ACK_IN(1) => adc_write_ack,
+ BUS_NO_MORE_DATA_IN(1) => adc_no_more_data,
+ BUS_UNKNOWN_ADDR_IN(1) => adc_unknown_addr,
+ --Bus Handler (SPI CTRL)
+ BUS_READ_ENABLE_OUT(2) => spictrl_read_en,
+ BUS_WRITE_ENABLE_OUT(2) => spictrl_write_en,
+ BUS_DATA_OUT(2*32+31 downto 2*32) => spictrl_data_in,
+ BUS_ADDR_OUT(2*16) => spictrl_addr,
+ BUS_ADDR_OUT(2*16+15 downto 2*16+1) => open,
+ BUS_TIMEOUT_OUT(2) => open,
+ BUS_DATA_IN(2*32+31 downto 2*32) => spictrl_data_out,
+ BUS_DATAREADY_IN(2) => spictrl_ack,
+ BUS_WRITE_ACK_IN(2) => spictrl_ack,
+ BUS_NO_MORE_DATA_IN(2) => spictrl_busy,
+ BUS_UNKNOWN_ADDR_IN(2) => '0',
+ --Bus Handler (SPI Memory)
+ BUS_READ_ENABLE_OUT(3) => spimem_read_en,
+ BUS_WRITE_ENABLE_OUT(3) => spimem_write_en,
+ BUS_DATA_OUT(3*32+31 downto 3*32) => spimem_data_in,
+ BUS_ADDR_OUT(3*16+5 downto 3*16) => spimem_addr,
+ BUS_ADDR_OUT(3*16+15 downto 3*16+6) => open,
+ BUS_TIMEOUT_OUT(3) => open,
+ BUS_DATA_IN(3*32+31 downto 3*32) => spimem_data_out,
+ BUS_DATAREADY_IN(3) => spimem_ack,
+ BUS_WRITE_ACK_IN(3) => spimem_ack,
+ BUS_NO_MORE_DATA_IN(3) => '0',
+ BUS_UNKNOWN_ADDR_IN(3) => '0',
+ --Flash ROM select
+ BUS_READ_ENABLE_OUT(4) => flash_rom_read,
+ BUS_WRITE_ENABLE_OUT(4) => flash_rom_write,
+ BUS_DATA_OUT(4*32) => next_flash_rom_select,
+ BUS_DATA_OUT(4*32+31 downto 4*32+1) => open,
+ BUS_ADDR_OUT(4*16+15 downto 4*16) => open,
+ BUS_TIMEOUT_OUT(4) => open,
+ BUS_DATA_IN(4*32+1 downto 4*32) => real_flash_rom_select,
+ BUS_DATA_IN(4*32+31 downto 4*32+2) => (others => '0'),
+ BUS_DATAREADY_IN(4) => flash_rom_read,
+ BUS_WRITE_ACK_IN(4) => flash_rom_write,
+ BUS_NO_MORE_DATA_IN(4) => '0',
+ BUS_UNKNOWN_ADDR_IN(4) => '0',
+ --Debugging
+ STAT_DEBUG => open
+ );
-------------------------------------------------------------------------------
-- SPI
-------------------------------------------------------------------------------
--- process(CLK_100)
--- begin
--- if rising_edge(CLK_100) then
--- flash_mem_data_out <= (others => '0');
---
--- if (flash_mem_addr(3 downto 0) = x"0") then
--- write_cmd_register_in <= flash_mem_write;
--- flash_mem_data_out <= cmd_register_in;
---
--- elsif (flash_mem_addr(3 downto 0) = x"1") then
--- write_ctrl_register <= flash_mem_write;
--- flash_mem_data_out <= ctrl_register;
--- else
--- cmd_register_in <= cmd_register_in;
--- ctrl_register <= ctrl_register;
--- end if;
--- end if;
--- end process;
---
--- process(CLK_100)
--- begin
--- if rising_edge(CLK_100) then
--- if (write_cmd_register_in = '1') then
--- cmd_register_in <= flash_mem_data;
--- else
--- cmd_register_in <= cmd_register_in;
--- end if;
--- end if;
--- end process;
---
--- process(CLK_100)
--- begin
--- if rising_edge(CLK_100) then
--- if (write_ctrl_register = '1') then
--- ctrl_register <= flash_mem_data;
--- else
--- ctrl_register <= ctrl_register;
--- end if;
--- end if;
--- end process;
THE_SPI_MASTER: spi_master
port map(
CTRL_DEBUG => (others => '0')
);
----------------------------------------------------------------------
--- Transport trigger to FEE and FEE definition
----------------------------------------------------------------------
--- 0xc0 0x0010 -> select short
--- 0xc0 0x0020 -> select long
--- 0xc0 0x0C10 -> x"C" set calibration trigger, x"0" normal
--- 0xc0 0x0000 -> select verbose mode data
--- 0xc0 0x1000 -> select compact mode data
--- 0xc0 0x2000 -> select test data
-
--- 0xc0 0xABC2000 -> x"ABC" test data number
-
--- 0xc0 0x10000000 -> x"1" external cms
--- 0xc0 0x00000000 -> x"0" internal generated cms
-
-
-------------------------------------------------------------------------------
--- Select Internal or external common stop
+-- dummy answers without trigger & readout logic
-------------------------------------------------------------------------------
-CMS <= COM_STOP_P when (cms_select_in_i = x"1") else a_cms_i;
+ GEN_NO_READOUT_LOGIC : if INCLUDE_READOUT = c_NO generate
-timing_trigger_received <= pulse_timing_trigger when (cms_select_in_i = x"1") else pulse_pseudo_timing_trigger;
+ -- LVL1 trigger APL
+ LVL1_ERROR_PATTERN_IN <= x"00400000";
+ IPU_DATA_IN <= x"0000BEAF";
+ IPU_LENGTH_IN <= x"0000";
+ IPU_ERROR_PATTERN_IN <= x"00500000";
- THE_CMS_SYNC : signal_sync
+ THE_TRG_RELEASE_DELAY : signal_sync
generic map(
- DEPTH => 2,
+ DEPTH => 4,
WIDTH => 1
)
port map(
RESET => reset_internal,
- D_IN(0) => COM_STOP_P,
+ D_IN(0) => LVL1_TRG_RECEIVED_OUT,
CLK0 => CLK_100,
CLK1 => CLK_100,
- D_OUT(0) => timing_trigger_in
+ D_OUT(0) => LVL1_TRG_RELEASE_IN
);
--- 0xc0 0xABCD2000 -> x"ABCD" test data number
+ PROC_DUMMY_IPU : process(CLK_100)
+ begin
+ if rising_edge(CLK_100) then
+ IPU_READOUT_FINISHED_IN <= '0';
+ IPU_DATAREADY_IN <= '0';
+ case dummy_state is
+ when IDLE =>
+ if IPU_START_READOUT_OUT = '1' then
+ dummy_state <= SEND_DHDR;
+ IPU_DATAREADY_IN <= '1';
+ end if;
+ when SEND_DHDR =>
+ IPU_DATAREADY_IN <= '1';
+ if IPU_READ_OUT = '1' then
+ dummy_state <= WAIT_FOR_FINISHED;
+ IPU_DATAREADY_IN <= '0';
+ end if;
+ when WAIT_FOR_FINISHED =>
+ IPU_READOUT_FINISHED_IN <= '1';
+ if IPU_START_READOUT_OUT = '0' then
+ dummy_state <= IDLE;
+ end if;
+ end case;
+ end if;
+ end process;
+
+-- D(1) <= pulse_pseudo_timing_trigger;
+-- D(2) <= LVL1_TRG_RELEASE_IN;
+-- D(3) <= timing_trigger_received;
+-- D(4) <= COMMON_CTRL_REG_STROBE(1);
+ D <= not (LVL1_INT_TRG_NUMBER_OUT(1 downto 0) & LVL1_TRG_NUMBER_OUT(1 downto 0));
+ end generate;
- PROC_GEN_TIMING : process(CLK_100)
- begin
- if rising_edge(CLK_100) then
- motherboard_type_in_i <= REGIO_REGISTERS_OUT(7 downto 4);
- cal_trigger_register_in_i <= x"000" & REGIO_REGISTERS_OUT(11 downto 8);
- data_type_select_in_i <= REGIO_REGISTERS_OUT(27 downto 12);
- cms_select_in_i <= REGIO_REGISTERS_OUT(31 downto 28);
- end if;
- end process;
+-------------------------------------------------------------------------------
+-- Select Internal or external common stop
+-------------------------------------------------------------------------------
+ CMS <= COM_STOP_P when (cms_select_in_i = x"1") else a_cms_i;
+ timing_trigger_received <= pulse_timing_trigger when (cms_select_in_i = x"1") else pulse_pseudo_timing_trigger;
+
+ pulse_pseudo_timing_trigger <= REGIO_COMMON_CTRL_REG_OUT(16);
+ pulse_reset_internal_logic <= REGIO_COMMON_CTRL_REG_OUT(0);
+ pulse_begin_run_trigger_i <= REGIO_COMMON_CTRL_REG_OUT(24);
+
+ reset_mdc_addon_daq_bus_0 <= reset_internal or pulse_reset_internal_logic;
+
+ PROC_REG_SETTINGS : process(CLK_100)
+ begin
+ if rising_edge(CLK_100) then
+ motherboard_type_in_i <= REGIO_REGISTERS_OUT(7 downto 4);
+ cal_trigger_register_in_i <= x"000" & REGIO_REGISTERS_OUT(43 downto 40);
+ data_type_select_in_i <= REGIO_REGISTERS_OUT(59 downto 44);
+ cms_select_in_i <= REGIO_REGISTERS_OUT(63 downto 60);
+ end if;
+ end process;
+ THE_CMS_SYNC : signal_sync
+ generic map(
+ DEPTH => 2,
+ WIDTH => 1
+ )
+ port map(
+ RESET => reset_internal,
+ D_IN(0) => COM_STOP_P,
+ CLK0 => CLK_100,
+ CLK1 => CLK_100,
+ D_OUT(0) => timing_trigger_in
+ );
- PULSE_TIMING_TRIGGER : edge_to_pulse
+ PULSE_TIMING_TRIGGER : edge_to_pulse
port map (
CLOCK => CLK_100,
ENABLE_CLK_IN => '1',
SIGNAL_IN => timing_trigger_in,
- PULSE_OUT => pulse_timing_trigger);
+ PULSE_OUT => pulse_timing_trigger
+ );
- PULSE_TRIGGER : edge_to_pulse
- port map (
- CLOCK => CLK_100,
- ENABLE_CLK_IN => '1',
- SIGNAL_IN => REGIO_COMMON_CTRL_REG_OUT(16),
- PULSE_OUT => pulse_pseudo_timing_trigger);
+ proc_gen_cms : process(CLK_100)
+ begin
+ if rising_edge(CLK_100) then
+ if reset_internal = '1' then
+ cms_counter <= x"0";
+ cms_output <= '0';
+ elsif cms_counter = x"0" then
+ if pulse_pseudo_timing_trigger = '1' then
+ cms_counter <= x"1";
+ cms_output <= '1';
+ end if;
+ elsif cms_counter = x"5" then
+ cms_output <= '0';
+ cms_counter <= x"0";
+ else
+ cms_counter <= cms_counter + to_unsigned(1,4);
+ end if;
+ end if;
+ end process;
- PULSE_RESET_LOGIC : edge_to_pulse
- port map (
- CLOCK => CLK_100,
- ENABLE_CLK_IN => '1',
- SIGNAL_IN => REGIO_COMMON_CTRL_REG_OUT(0),
- PULSE_OUT => pulse_reset_internal_logic);
+ J2_P <= cms_output;
- reset_mdc_addon_daq_bus_0 <= reset_internal or pulse_reset_internal_logic;
- PULSE_BEGRUN_TRIGGER : edge_to_pulse
- port map (
- CLOCK => CLK_100,
- ENABLE_CLK_IN => '1',
- SIGNAL_IN => REGIO_COMMON_CTRL_REG_OUT(24),
- PULSE_OUT => pulse_begin_run_trigger_i);
- test_pseudo_signal_i <= (pulse_pseudo_timing_trigger and LVL1_TRG_RELEASE_IN)
- when (debug_trigger_distributor_i(3 downto 0) = x"1") else '0';
+-------------------------------------------------------------------------------
+-- trigger and readout logic
+-------------------------------------------------------------------------------
+
+ GEN_READOUT_LOGIC : if INCLUDE_READOUT = c_YES generate
THE_TRIG_DISTR : trigger_distributor
port map (
---------------------------------------------------------------------
-- FEE Readout
---------------------------------------------------------------------
- THE_MDC_OEP_READOUT : mdc_addon_daq_bus_0
- --generic map (bus_number => bus_number)
- port map (
- CLK => CLK_100,
- RESET => reset_mdc_addon_daq_bus_0,--reset_internal,
- A_ADS_0 => '0',
- A_ADS_1 => '0',
- A_ADS_2 => '0',
- A_ACK => TACK,
- A_CMS => a_cms_i, --CMS,
- A_RDM => RDYI,--out to MB
- A_GDE => GDE,
- A_RDO => TRDYO,--in
- A_RESERV => TRSV,
- A_DRA => open,
- A_DRB_1 => open,
- A_DRB_2 => open,
- A_DRE => open,
- A_ENB_1 => open,
- A_ENB_2 => open,
- A_ENR_1 => open,
- A_ENR_2 => open,
- A_FET_ENABLE => open,
- A_REN => open,
- A_MOD => MODD,
- A_RES => RES,
- A_TOK => TOK,
- A_WRM => WRM,
- TOKEN_TO_MUX_OUT => token_to_mux_out_i,
- TRIGGER_TYPE_IN => init_all_buses_i,
- LA => open,
- D => open,
- A_RDO_OUT => open,
- ROC1_WRITTEN_OUT => roc1_written_i,
- DATA_TYPE_SELECT_IN => data_type_select_in_i,
- DIRECTION_DATA_LINE_OUT => direction_data_line_out_i,
- MOTHERBOARD_TYPE_IN => motherboard_type_in_i,
-
- ACKNOWLEDGE_TRB_INTERFACE_IN => x"1",
- INIT_TRB_INTERFACE_OUT => open,
- DATA_OUT => open,
- READ_FIFO_IN => '0',
- DEBUG_REGISTER_TRB_INTERFACE => (others => '0'),
-
- RAM_ADDRESS_IN => thresh_mem_addr,-- (others => '0'), --8 to 0
- RAM_DATA_IN => thresh_mem_data,--15 to 0
- RAM_DATA_OUT => thresh_mem_data_out,
- RAM_READ_ENABLE_IN => '0',
- RAM_WRITE_ENABLE_IN => thresh_mem_write,
-
- A_ADD_CONFIGURATION_OUT => a_add_configuration_i,
- A_DST_CONFIGURATION_OUT => a_dst_configuration_i,
- A_AOD_CONFIGURATION_OUT => a_aod_configuration_i,
-
- A_ADD_DATA_IN => a_add_data_i,
- A_DST_DATA_IN => a_dst_data_i,
- A_AOD_DATA_IN => a_aod_data_i,
-
- DEBUG_REGISTER_0_BUS_0 => test_debug_i,
- DEBUG_REGISTER_1_BUS_0 => open,
- DEBUG_REGISTER_2_BUS_0 => open,
- DEBUG_REGISTER_3_BUS_0 => open,
- DEBUG_REGISTER_4_BUS_0 => open,
- DEBUG_REGISTER_5_BUS_0 => open,
- DEBUG_REGISTER_6_BUS_0 => open,
- DEBUG_REGISTER_7_BUS_0 => open,
-
- LVL1_TRG_TYPE_IN => LVL1_TRG_TYPE_OUT,
- LVL1_TRG_RECEIVED_IN => open,-- LVL1_TRG_RECEIVED_OUT,
- LVL1_TRG_NUMBER_IN => LVL1_TRG_NUMBER_OUT,
- LVL1_TRG_CODE_IN => LVL1_TRG_CODE_OUT,
- LVL1_TRG_INFORMATION_IN => LVL1_TRG_INFORMATION_OUT,
- LVL1_ERROR_PATTERN_OUT => LVL1_ERROR_PATTERN_IN,
- LVL1_TRG_RELEASE_OUT => LVL1_TRG_RELEASE_IN,
-
- --Data Port
- IPU_NUMBER_IN => IPU_NUMBER_OUT,
- IPU_INFORMATION_IN => IPU_INFORMATION_OUT,
- --start strobe
- IPU_START_READOUT_IN => IPU_START_READOUT_OUT,
- --detector data, equipped with DHDR
- IPU_DATA_OUT => IPU_DATA_IN,
- IPU_DATAREADY_OUT => IPU_DATAREADY_IN,
- --no more data, end transfer, send TRM
- IPU_READOUT_FINISHED_OUT => IPU_READOUT_FINISHED_IN,
- --will be low every second cycle due to 32bit -> 16bit conversion
- IPU_LENGTH_OUT => IPU_LENGTH_IN,
- IPU_ERROR_PATTERN_OUT => IPU_ERROR_PATTERN_IN,
- IPU_READ_IN => IPU_READ_OUT
- );
+ THE_MDC_OEP_READOUT : mdc_addon_daq_bus_0
+ --generic map (bus_number => bus_number)
+ port map (
+ CLK => CLK_100,
+ RESET => reset_mdc_addon_daq_bus_0,--reset_internal,
+ A_ADS_0 => '0',
+ A_ADS_1 => '0',
+ A_ADS_2 => '0',
+ A_ACK => TACK,
+ A_CMS => a_cms_i, --CMS,
+ A_RDM => RDYI,--out to MB
+ A_GDE => GDE,
+ A_RDO => TRDYO,--in
+ A_RESERV => TRSV,
+ A_DRA => open,
+ A_DRB_1 => open,
+ A_DRB_2 => open,
+ A_DRE => open,
+ A_ENB_1 => open,
+ A_ENB_2 => open,
+ A_ENR_1 => open,
+ A_ENR_2 => open,
+ A_FET_ENABLE => open,
+ A_REN => open,
+ A_MOD => MODD,
+ A_RES => RES,
+ A_TOK => TOK,
+ A_WRM => WRM,
+ TOKEN_TO_MUX_OUT => token_to_mux_out_i,
+ TRIGGER_TYPE_IN => init_all_buses_i,
+ LA => open,
+ D => open,
+ A_RDO_OUT => open,
+ ROC1_WRITTEN_OUT => roc1_written_i,
+ DATA_TYPE_SELECT_IN => data_type_select_in_i,
+ DIRECTION_DATA_LINE_OUT => direction_data_line_out_i,
+ MOTHERBOARD_TYPE_IN => motherboard_type_in_i,
+
+ ACKNOWLEDGE_TRB_INTERFACE_IN => x"1",
+ INIT_TRB_INTERFACE_OUT => open,
+ DATA_OUT => open,
+ READ_FIFO_IN => '0',
+ DEBUG_REGISTER_TRB_INTERFACE => (others => '0'),
+
+ RAM_ADDRESS_IN => thresh_mem_addr,-- (others => '0'), --8 to 0
+ RAM_DATA_IN => thresh_mem_data,--15 to 0
+ RAM_DATA_OUT => thresh_mem_data_out,
+ RAM_READ_ENABLE_IN => '0',
+ RAM_WRITE_ENABLE_IN => thresh_mem_write,
+
+ A_ADD_CONFIGURATION_OUT => a_add_configuration_i,
+ A_DST_CONFIGURATION_OUT => a_dst_configuration_i,
+ A_AOD_CONFIGURATION_OUT => a_aod_configuration_i,
+
+ A_ADD_DATA_IN => a_add_data_i,
+ A_DST_DATA_IN => a_dst_data_i,
+ A_AOD_DATA_IN => a_aod_data_i,
+
+ DEBUG_REGISTER_0_BUS_0 => test_debug_i,
+ DEBUG_REGISTER_1_BUS_0 => open,
+ DEBUG_REGISTER_2_BUS_0 => open,
+ DEBUG_REGISTER_3_BUS_0 => open,
+ DEBUG_REGISTER_4_BUS_0 => open,
+ DEBUG_REGISTER_5_BUS_0 => open,
+ DEBUG_REGISTER_6_BUS_0 => open,
+ DEBUG_REGISTER_7_BUS_0 => open,
+
+ LVL1_TRG_TYPE_IN => LVL1_TRG_TYPE_OUT,
+ LVL1_TRG_RECEIVED_IN => LVL1_TRG_RECEIVED_OUT,
+ LVL1_TRG_NUMBER_IN => LVL1_TRG_NUMBER_OUT,
+ LVL1_TRG_CODE_IN => LVL1_TRG_CODE_OUT,
+ LVL1_TRG_INFORMATION_IN => LVL1_TRG_INFORMATION_OUT,
+ LVL1_ERROR_PATTERN_OUT => LVL1_ERROR_PATTERN_IN,
+ LVL1_TRG_RELEASE_OUT => LVL1_TRG_RELEASE_IN,
+ LVL1_INT_TRG_NUMBER_OUT => LVL1_INT_TRG_NUMBER_OUT,
+
+ --Data Port
+ IPU_NUMBER_IN => IPU_NUMBER_OUT,
+ IPU_INFORMATION_IN => IPU_INFORMATION_OUT,
+ --start strobe
+ IPU_START_READOUT_IN => IPU_START_READOUT_OUT,
+ --detector data, equipped with DHDR
+ IPU_DATA_OUT => IPU_DATA_IN,
+ IPU_DATAREADY_OUT => IPU_DATAREADY_IN,
+ --no more data, end transfer, send TRM
+ IPU_READOUT_FINISHED_OUT => IPU_READOUT_FINISHED_IN,
+ --will be low every second cycle due to 32bit -> 16bit conversion
+ IPU_LENGTH_OUT => IPU_LENGTH_IN,
+ IPU_ERROR_PATTERN_OUT => IPU_ERROR_PATTERN_IN,
+ IPU_READ_IN => IPU_READ_OUT
+ );
-------------------------------------------------------------------------------
-- DATA MULTIPLEXER for INOUT DST, AOD,TAD
end if;
end if;
end process;
+ end generate;
+
+
-------------------------------------------------------------------------------
-- pin not used input for fpga
---------------------------------------------------------------------
-- LED
---------------------------------------------------------------------
--- D(1) <= not MED_STAT_DEBUG(1);
--- D(2) <= not MED_STAT_OP(9);
--- D(3) <= not MED_STAT_DEBUG(7);
--- D(4) <= not MED_STAT_DEBUG(8);
-
--- D(1) <= IPU_START_READOUT_OUT;
--- D(2) <= IPU_DATAREADY_IN; --to trbnet
--- D(3) <= IPU_READOUT_FINISHED_IN;
--- D(4) <= IPU_READ_OUT; --to fee readout
-
- process(CLK_100, pulse_pseudo_timing_trigger, counter_led,
- reset_internal)
- begin
- if rising_edge(CLK_100) then
- if (reset_internal = '1') then
- counter_led <= (others => '0');
- elsif (pulse_pseudo_timing_trigger = '1') then
- counter_led <= counter_led + "1";
- elsif (counter_led = x"00004E20") then
- counter_led <= (others => '0');
- else
- counter_led <= counter_led;
- end if;
- end if;
- end process;
-
--- D <= "1010" when (counter_led < x"00002710") else "0101";
+-- TAD(0) <= CLK;
+-- TAD(8 downto 1) <= LVL1_INT_TRG_NUMBER_OUT(1 downto 0) & LVL1_TRG_RELEASE_IN & LVL1_TRG_RECEIVED_OUT & LVL1_TRG_NUMBER_OUT(3 downto 0);
---------------------------------------------------------------------
-- List of debugging signals
jspc29 / mdcoep.git / commitdiff