base folder update

diff --git a/base/cbmtof.lpf b/base/cbmtof.lpf
index 9434a9143e0728d3f1c99daa77385c220c32d490..277f3937a9e869e55d2bf1a0105857e09acf9a2d 100644 (file)
--- a/base/cbmtof.lpf
+++ b/base/cbmtof.lpf
@@ -11,6 +11,8 @@ SYSCONFIG MCCLK_FREQ = 20;
 
 FREQUENCY PORT CLK_OSC 200 MHz;
 FREQUENCY PORT CLK_EXT 200 MHz;
+FREQUENCY NET "clk_200_i" 200.000000 MHz ;
+FREQUENCY NET "clk_100_i_c" 100.000000 MHz ;
 #FREQUENCY PORT CLK_CM_* 125 MHz;
 
 #MULTICYCLE FROM CLKNET "clk_100_i_c" TO CLKNET "CLK_OSC_c" 2 X ;

diff --git a/base/trb3_components_1-7-x.vhd b/base/trb3_components_1-7-x.vhd
index 17da2482e2efb1707cbf1d60d3c7863c67de18a0..b552f78b3372a0810dc81ca012c660ccd1d72a26 100644 (file)
--- a/base/trb3_components_1-7-x.vhd
+++ b/base/trb3_components_1-7-x.vhd
@@ -76,8 +76,7 @@ package trb3_components is
       Reset       : in  std_logic;
       Q           : out std_logic_vector(35 downto 0);
       Empty       : out std_logic;
-      Full        : out std_logic;
-      AlmostEmpty : out std_logic);
+      Full        : out std_logic);
   end component;
 
   component FIFO_36x32_OutReg is
@@ -101,8 +100,7 @@ package trb3_components is
       Reset       : in  std_logic;
       Q           : out std_logic_vector(35 downto 0);
       Empty       : out std_logic;
-      Full        : out std_logic;
-      AlmostEmpty : out std_logic);
+      Full        : out std_logic);
   end component;  
 
   component FIFO_DC_36x128_OutReg is

diff --git a/base/trb3_periph_padiwa.lpf b/base/trb3_periph_padiwa.lpf
index 5b276cd0daf0c3f09a2f197b0c92db1953c36d2d..212e83bd908738b581bfc4af0b82b56e32c0154e 100644 (file)
--- a/base/trb3_periph_padiwa.lpf
+++ b/base/trb3_periph_padiwa.lpf
@@ -194,33 +194,6 @@ IOBUF GROUP "INP_group" IO_TYPE=LVDS25 DIFFRESISTOR=100;
 # LOCATE COMP  "DQUL_34"   SITE "L5";     #"DQUL_34"   DQUL2_8   #70
 # LOCATE COMP  "DQUL_35"   SITE "L6";     #"DQUL_35"   DQUL2_9   #72
 
-LOCATE COMP  "OUT_SDO_1"    SITE "K3"; 
-LOCATE COMP  "OUT_SDO_2"    SITE "F2"; 
-LOCATE COMP  "OUT_SDO_3"    SITE "AA24"; 
-LOCATE COMP  "OUT_SDO_4"    SITE "C3"; 
-
-LOCATE COMP  "OUT_SCK_1"    SITE "J4"; 
-LOCATE COMP  "OUT_SCK_2"    SITE "D4"; 
-LOCATE COMP  "OUT_SCK_3"    SITE "U24"; 
-LOCATE COMP  "OUT_SCK_4"    SITE "L5"; 
-
-LOCATE COMP  "IN_SDI_1"     SITE "C2"; 
-LOCATE COMP  "IN_SDI_2"     SITE "H5"; 
-LOCATE COMP  "IN_SDI_3"     SITE "AD26"; 
-LOCATE COMP  "IN_SDI_4"     SITE "G5"; 
-
-LOCATE COMP  "OUT_CS_1"     SITE "D1"; 
-LOCATE COMP  "OUT_CS_2"     SITE "H6"; 
-LOCATE COMP  "OUT_CS_3"     SITE "U23"; 
-LOCATE COMP  "OUT_CS_4"     SITE "K8"; 
-
-
-DEFINE PORT GROUP "IN_group" "IN_*" ;
-IOBUF GROUP "IN_group" IO_TYPE=LVDS25 DIFFRESISTOR=100;
-
-DEFINE PORT GROUP "OUT_group" "OUT_*" ;
-IOBUF GROUP "OUT_group" IO_TYPE=LVDS25;
-
 #################################################################
 # Additional Lines to AddOn
 #################################################################
@@ -249,15 +222,43 @@ IOBUF GROUP "FLASH_group" IO_TYPE=LVCMOS25 PULLMODE=NONE;
 LOCATE COMP  "PROGRAMN"   SITE "B11";
 IOBUF  PORT "PROGRAMN" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8  ;
 
-LOCATE COMP  "DAC_SDI"   SITE "G6";   #"DQUL_7"   DQSUL0_C  #88   #IN_L_SDIb
-LOCATE COMP  "DAC_SCK"   SITE "E4";   #"DQUL_3"   DQUL0_3   #80   #OUT_L_SDOb
-LOCATE COMP  "DAC_CS_0"  SITE "C3";   #"DQUL_4"   DQUL0_4   #82   #OUT_L_SCK
-LOCATE COMP  "DAC_CS_1"  SITE "D3";   #"DQUL_5"   DQUL0_5   #84   #OUT_L_SCKb
-LOCATE COMP  "DAC_CS_2"  SITE "H6";   #"DQUL_10"  DQUL0_8   #94   #OUT_L_CS
-LOCATE COMP  "DAC_CS_3"  SITE "J6";   #"DQUL_11"  DQUL0_9   #96   #OUT_L_CSb
 
-DEFINE PORT GROUP "DAC_group" "DAC*" ;
-IOBUF GROUP "DAC_group" IO_TYPE=LVCMOS33 PULLMODE=NONE;
+LOCATE COMP  "OUT_SDO_1"    SITE "K3"; 
+LOCATE COMP  "OUT_SDO_2"    SITE "F2"; 
+LOCATE COMP  "OUT_SDO_3"    SITE "AA24"; 
+LOCATE COMP  "OUT_SDO_4"    SITE "C3"; 
+
+LOCATE COMP  "OUT_SCK_1"    SITE "J4"; 
+LOCATE COMP  "OUT_SCK_2"    SITE "D4"; 
+LOCATE COMP  "OUT_SCK_3"    SITE "U24"; 
+LOCATE COMP  "OUT_SCK_4"    SITE "L5"; 
+
+LOCATE COMP  "IN_SDI_1"     SITE "C2"; 
+LOCATE COMP  "IN_SDI_2"     SITE "H5"; 
+LOCATE COMP  "IN_SDI_3"     SITE "AD26"; 
+LOCATE COMP  "IN_SDI_4"     SITE "G5"; 
+
+LOCATE COMP  "OUT_CS_1"     SITE "D1"; 
+LOCATE COMP  "OUT_CS_2"     SITE "H6"; 
+LOCATE COMP  "OUT_CS_3"     SITE "U23"; 
+LOCATE COMP  "OUT_CS_4"     SITE "K8"; 
+
+
+DEFINE PORT GROUP "IN_group" "IN_*" ;
+IOBUF GROUP "IN_group" IO_TYPE=LVDS25 DIFFRESISTOR=100;
+
+DEFINE PORT GROUP "OUT_group" "OUT_*" ;
+IOBUF GROUP "OUT_group" IO_TYPE=LVDS25;
+
+#LOCATE COMP  "DAC_SDI"   SITE "G6";   #"DQUL_7"   DQSUL0_C  #88   #IN_L_SDIb
+#LOCATE COMP  "DAC_SCK"   SITE "E4";   #"DQUL_3"   DQUL0_3   #80   #OUT_L_SDOb
+#LOCATE COMP  "DAC_CS_0"  SITE "C3";   #"DQUL_4"   DQUL0_4   #82   #OUT_L_SCK
+#LOCATE COMP  "DAC_CS_1"  SITE "D3";   #"DQUL_5"   DQUL0_5   #84   #OUT_L_SCKb
+#LOCATE COMP  "DAC_CS_2"  SITE "H6";   #"DQUL_10"  DQUL0_8   #94   #OUT_L_CS
+#LOCATE COMP  "DAC_CS_3"  SITE "J6";   #"DQUL_11"  DQUL0_9   #96   #OUT_L_CSb
+#
+#DEFINE PORT GROUP "DAC_group" "DAC*" ;
+#IOBUF GROUP "DAC_group" IO_TYPE=LVCMOS33 PULLMODE=NONE;
 
 
 #################################################################