CTRL_LOCKED: in STD_LOGIC_VECTOR (15 downto 0);
STAT_BUFFER: out STD_LOGIC_VECTOR (31 downto 0)
);
-END trb_net_ibuf;
+end trb_net_ibuf;
architecture trb_net_ibuf_arch of trb_net_ibuf is
-- Status and control port
STAT_BUFFER: out STD_LOGIC
);
- END component;
+ end component;
signal fifo_data_in : std_logic_vector(50 downto 0);
signal fifo_data_out : std_logic_vector(50 downto 0);
if MED_DATAREADY_IN = '1' and reg_read_out= '1' then
if MED_DATA_IN(TYPE_POSITION) = TYPE_ACK then
-- BUGBUG: this causes trouble if the IBUF is full
- got_ack_internal <= '1';
+ got_ack_internal <= '1';
if MED_DATA_IN(F1_POSITION) = F1_CHECK_ACK then
next_rec_buffer_size_out <= MED_DATA_IN(BUFFER_SIZE_POSITION);
end if;
-- elsif fifo_full = '0' and is_locked = '0' then
- elsif fifo_full = '0' then -- still ACKs may come even when locked
+ elsif fifo_full = '0' then -- still ACKs may come even when locked
fifo_write <= '1';
next_read_out <= '1';
elsif fifo_full = '1' then
INT_PACKET_NR_IN: in STD_LOGIC_VECTOR (1 downto 0);
INT_READ_OUT: out STD_LOGIC; -- offered word is read
INT_ERROR_IN: in STD_LOGIC_VECTOR (2 downto 0); -- Status bits
-
+
-- Media direction port
-- in this case for the cable => 32 lines in total
MED_DATA_OUT: out STD_LOGIC_VECTOR (12 downto 0); -- Data word
-- for the direction to
-- internal world
FIFO_TO_APL_DEPTH : integer := 3; -- direction to application
- FIFO_TERM_BUFFER_DEPTH : integer := 0 -- fifo for auto-answering of
+ FIFO_TERM_BUFFER_DEPTH : integer := 1 -- fifo for auto-answering of
-- the master path, if set to 0
-- no buffer is used at all
);
next_fifo_write_enable_in <= '0';
next_fifo_data_in <= (others => '0');
next_APL_SEND_OUT <= '0';
- buf_STAT_TRIGGER_READER(3 downto 1) <= (others => '0');
- buf_STAT_TRIGGER_READER(2) <= APL_DATAREADY_IN;
- if APL_TYP_IN = TYPE_TRM then
- buf_STAT_TRIGGER_READER(1) <= '1';
- end if;
if APL_TYP_IN = TYPE_TRM and APL_DATAREADY_IN = '1' and buf_APL_READ_OUT = '1' then
- buf_STAT_TRIGGER_READER(3) <= '1';
next_fifo_data_in(7 downto 0) <= APL_SEQNR_IN;
next_fifo_data_in(39 downto 8)<= timecounter;
next_fifo_write_enable_in <= '1';
end if;
end process;
-buf_STAT_TRIGGER_READER(4) <= buf_APL_SEND_OUT;
-buf_STAT_TRIGGER_READER(5) <= next_APL_SEND_OUT;
+buf_STAT_TRIGGER_READER(1) <= fifo_write_enable_in;
+buf_STAT_TRIGGER_READER(2) <= fifo_read;
STAT_TRIGGER_READER <= buf_STAT_TRIGGER_READER;
begin
next_trigger_num_is_read <= trigger_num_is_read;
next_trigger_time_is_read <= trigger_time_is_read;
- next_fifo_read <= '0';
+ fifo_read <= '0';
next_TRB_TRIGGER_READ_ERROR <= '0';
if trigger_num_is_read = '1' and trigger_time_is_read = '1' then
next_trigger_num_is_read <= '0';
next_trigger_time_is_read <= '0';
- fifo_read <= '1';
+ next_fifo_read <= '1';
next_TRB_TRIGGER_READ_ERROR <= buf_TRB_TRIGGER_READ_ERROR;
end if;
end process;
+
process(CLK)
begin
if rising_edge(CLK) then