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\title{Noise performance of CMOS Monolithic Active Pixel Sensors manufactured in a 0.18$\upmu$m CMOS process\thanks{This work has been supported by BMBF (05P12RFFC7), HIC for FAIR and GSI.}}
%\affil[mun]{Forschungsneutronenquelle Heinz-Maier-Leibnitz (FRM II), Technical University Munich, Lichtenbergstr. 1,
%85747 Garching, Germany}
\maketitle
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%\section{Introduction}
-\textbf{In 2013, we performed a comprehensive study of sensors, produced in an \mbox{0.18 $\upmu \rm m$} CMOS process and examined in detail their noise performance.\newline}
-So far CMOS active pixel sensors (MAPS) matched the requirements of CBM in terms of spatial resolution and material budget. During several years, their radiation tolerance has been adapted to the needs of this experiment. Since recently, a dedicated imaging process with $0.18~\rm \upmu m$ feature size became available for particle detectors. The radiation tolerance of this CMOS process was explored and it could be demonstrated that this process provides the radiation tolerance required for CBM at SIS-100. However, the exploratory study found that this new sensors have a quite substantial high noise. In 2013, the origin of this noise was studied to understand the effect and to provide strategies to suppress the noise and improve the performance.\newline
-To explore the noise issue, three different prototypes named MIMOSA-32, MIMOSA-32ter and MIMOSA-34 were designed and tested in laboratory. Each flavor is composed of arrays of 32 different pixels with various parameters, which were put to study selected pixel parameters in a systematic way.\newline
-The aim of the presented study is to optimize the transistor dimensions to improve the noise performance. Therefore the matrices MIMOSA-32ter-P2, MIMOSA-32ter-P6, MIMOSA-32ter-P5 and MIMOSA-34-P17 were chosen. In the following, the matrices are named Pixel A-D accordingly (table \ref{tab:Mi32-1-f-noise-table}). As a reference, the matrix MIMOSA-18AHR-A2, produced in an \mbox{0.35 $\upmu \rm m$} CMOS process is supplemented (Pixel R).\newline
-The pixels A-D in the $0.18 \mum$-process have a higher noise in comparison to the reference pixel R in the $0.35 \mum$-process. In particular the 99\%-noise, which represents the noise value that $>99\%$ of the pixel have a lower noise, is doubled. \newline
-According to table \ref{tab:Mi32-1-f-noise-table} A-C, decreasing the width of the source follower transistor from $1.5\mum$ to $0.5\mum$, the gain improves by $10\%$ and the noise increases slightly by $8\%$. The noise increase is in particular large for the 99\% noise, which is increased by 54\%. Therefore a smaller transistor surface is not beneficial for the noise performance. The origin of this effect was identified as an 1/f-noise or Random Telegraph Signal (RTS) as it was already described in \cite{RTS0.18,RTS0.182}. This holds also for the gate of the reset transistor, which could be enlarged in \mbox{Pixel D}. After this modification, the median noise was reduced from \mbox{$19.8~\rm e$} \mbox{(Pixel A)} to \mbox{$16.2~\rm e$} \mbox{(Pixel D)}. Note that, while enlarging the transistor size reduces the RTS, cooling seems not to show a positive impact. This is in contrast to our observations on RTS-noise originating from the pixel \mbox{diodes \cite{PaperRTS}}.\newline
-We conclude that the lower feature size of the $0.18 \mum$-process under study cannot be fully exploited to reduce the capacitive noise of the pixels. This is as the smaller transistors show an RTS-1/f noise, which dominates the capacitive noise. Knowing this effect, it should be possible to reduce the noise of the above presented sensors by means of optimizing the layout of the few relevant transistors.\newline
-This work is part of a proceeding paper to the IWORID conference 2013 in Paris, which was sent to editorial office in December 2013.\newline
+\textbf{Modern $0.18\mum$ CMOS-processes provide numerous features, which may allow for decisive progresses in the read-out speed and the radiation tolerance of the CMOS Monolithic Active Pixel Sensors (MAPS) to be used in the Micro-Vertex-Detector of CBM. Together with the PICSEL group of IPHC Strasbourg, we aim to exploit those features by migrating the successful architecture of our sensors toward this novel technology. This work reports about our findings on the first prototypes manufactured with the new technology.}
-\bibliographystyle{plain}
-\bibliography{Lit}
+So far, MAPS match the requirements of CBM in terms of spatial resolution, light material budget and tolerance to non-ionizing radiation. Migrating them from the previously used $0.35 \mum$ CMOS process to a novel $0.18\mum$ process was done to exploit the known higher tolerance of deep sub-micron processes to ionizing radiation. Moreover, the novel process allows for a first time to use also PMOS transistors in the pixel. This creates the potential to discriminate the signal inside the pixels instead of transporting it to the end of the columns, which would turn into a substantial acceleration of the read-out.
+
+%During several years, their radiation tolerance has been adapted to the needs of this experiment. Since recently, a dedicated imaging process with $0.18~\rm \upmu m$ feature size became available for particle detectors. The radiation tolerance of this CMOS process was explored and it could be demonstrated that this process provides the radiation tolerance required for CBM at SIS-100. However, the exploratory study found that this new sensors have a quite substantial high noise. In 2013, the origin of this noise was studied to understand the effect and to provide strategies to suppress the noise and improve the performance.\newline
+Three prototypes named MIMOSA-32, MIMOSA-32ter and MIMOSA-34 were designed and tested in order to discover the novel technology. Various parameters of the pixels were varied in a systematic way in order to find an optimum. During our tests, we found that the average noise of the novel pixels exceed the noise of elder pixels manufactured in the $0.35 \mum$-process by about a factor of two. Moreover, we observed a correlation between the noise and the surface of the gate of the transistor serving as input stage of the on-pixel pre-amplifier. This is shown in Table \ref{tab:Mi32-1-f-noise-table}, which displays the noise as a function of the width of the gate of this transistor. The length of the gate of the pixels manufactured in $0.18\mum$-CMOS (pixel A-D) was $0.2\mum$. In the reference pixel (pixel R), which was manufactured in $0.35\mum$-CMOS, an enclosed transistor layout turning into an effective width of several$\mum$ was used and the gate length was $0.35\mum$.
+
+Initially, we expected the noise to shrink with a decreasing surface of this gate as the capacity of the input node is reduced and therefore the gain of the signal is increased. In contrast to this expectation, we observed the noise to increase with shrinking gate. Moreover, we observed a strong increase in the number of hot pixels. This is shown in the most right column (Noise 99\%) of Table \ref{tab:Mi32-1-f-noise-table}. Here, we assumed that 1\% of all pixels can be masked and that the common threshold of the pixels of the chip should be set to discriminate the noise of the most noisy active pixel. The noise of this pixel is shown.
-\begin{table}
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-\hbox{ }
-\hbox{ }
-\hbox{ }
+tested in laboratory. Each flavor is composed of arrays of 32 different pixels with various parameters, which were put to study selected pixel parameters in a systematic way.\newline
+The aim of the presented study is to optimize the transistor dimensions to improve the noise performance. Therefore the matrices MIMOSA-32ter-P2, MIMOSA-32ter-P6, MIMOSA-32ter-P5 and MIMOSA-34-P17 were chosen. In the following, the matrices are named Pixel A-D accordingly (table \ref{tab:Mi32-1-f-noise-table}). As a reference, the matrix MIMOSA-18AHR-A2, produced in an \mbox{0.35 $\upmu \rm m$} CMOS process is supplemented (Pixel R).\newline
+The pixels A-D in the $0.18 \mum$-process have a higher noise in comparison to the reference pixel R in the $0.35 \mum$-process. In particular the 99\%-noise, which represents the noise value that $>99\%$ of the pixel have a lower noise, is doubled. \newline
+
+\begin{table}[t]
\centering
\begin{tabular}{|c|c|ccc|}
\label{tab:Mi32-1-f-noise-table}
\end{table}
+According to table \ref{tab:Mi32-1-f-noise-table} A-C, decreasing the width of the source follower transistor from $1.5\mum$ to $0.5\mum$, the gain improves by $10\%$ and the noise increases slightly by $8\%$. The noise increase is in particular large for the 99\% noise, which is increased by 54\%. Therefore a smaller transistor surface is not beneficial for the noise performance. The origin of this effect was identified as an 1/f-noise or Random Telegraph Signal (RTS) as it was already described in \cite{RTS0.18,RTS0.182}. This holds also for the gate of the reset transistor, which could be enlarged in \mbox{Pixel D}. After this modification, the median noise was reduced from \mbox{$19.8~\rm e$} \mbox{(Pixel A)} to \mbox{$16.2~\rm e$} \mbox{(Pixel D)}. Note that, while enlarging the transistor size reduces the RTS, cooling seems not to show a positive impact. This is in contrast to our observations on RTS-noise originating from the pixel \mbox{diodes \cite{PaperRTS}}.\newline
+We conclude that the lower feature size of the $0.18 \mum$-process under study cannot be fully exploited to reduce the capacitive noise of the pixels. This is as the smaller transistors show an RTS-1/f noise, which dominates the capacitive noise. Knowing this effect, it should be possible to reduce the noise of the above presented sensors by means of optimizing the layout of the few relevant transistors.\newline
+This work is part of a proceeding paper to the IWORID conference 2013 in Paris, which was sent to editorial office in December 2013.\newline
+
+\bibliographystyle{plain}
+\bibliography{Lit}
+
+
+
+
\end{document}
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