signal fifo_full_serdes_i : std_logic_vector(c_links - 1 downto 0);
signal fifo_data_serdes_i : std_logic_vector(c_mupixhitsize*c_links - 1 downto 0);
+ signal reset_reg : std_logic := '0';
+
begin -- Behavioral
-------------------------------------------------------------------------------
-- Port Maps
-------------------------------------------------------------------------------
+ register_reset: process (clk) is
+ begin -- process register_reset
+ if rising_edge(clk) then -- rising clock edge
+ reset_reg <= reset;
+ end if;
+ end process register_reset;
+
THE_BUS_HANDLER : trb_net16_regio_bus_handler
generic map(
PORT_NUMBER => NUM_PORTS,
)
port map(
CLK => CLK,
- RESET => RESET,
+ RESET => reset_reg,
DAT_ADDR_IN => REGIO_ADDR_IN,
DAT_DATA_IN => REGIO_DATA_IN,
port map(
clk_in => clk,
fast_clk_in => fast_clk,
- reset => reset,
+ reset => reset_reg,
ctrl_dout => ctrl_dout,
spi_dout_adc => spi_dout_adc,
spi_dout_dac => spi_dout_dac,
)
port map(
clk => clk,
- reset => reset,
+ reset => reset_reg,
mupixslctrl => mupixslctrl_i,
ctrl_dout => ctrl_dout_sync,
SLV_READ_IN => slv_read(1),
boardcontrol_1 : entity work.MupixBoardDAC
port map(
clk => clk,
- reset => reset,
+ reset => reset_reg,
spi_dout_dac => spi_dout_dac_sync,
dac4_dout => dac4_dout_sync,
spi_dout_adc => spi_dout_adc_sync,
)
port map(
clk => clk,
- rst => reset,
+ rst => reset_reg,
fifo_empty => mux_fifo_empty,
fifo_full => mux_fifo_full,
fifo_datain => mux_fifo_data,
triggerhandler1 : entity work.TriggerHandler
port map(
CLK_IN => clk,
- RESET_IN => reset,
+ RESET_IN => reset_reg,
TIMING_TRIGGER_IN => TIMING_TRG_IN,
LVL1_TRG_DATA_VALID_IN => LVL1_TRG_DATA_VALID_IN,
LVL1_VALID_TIMING_TRG_IN => LVL1_VALID_TIMING_TRG_IN,
)
port map(
clk => clk,
- reset => reset,
+ reset => reset_reg,
serdes_data => fifo_data_serdes_i,
serdes_fifo_full => fifo_full_serdes_i,
serdes_fifo_empty => fifo_empty_serdes_i,
port map(
sysclk => clk,
dataclk => data_clk,
- rst => reset,
- clear => reset,
+ rst => reset_reg,
+ clear => reset_reg,
mupix_data => mupix_data,
fifo_rden => fifo_rden_serdes_i,
fifo_empty => fifo_empty_serdes_i,
signal words_i : std_logic_vector(4 downto 0) := "00100";
signal slowdown_i : std_logic_vector(15 downto 0) := x"FF0A";
+ signal reset_reg : std_logic := '0';
+
begin -- architecture rtl
+ register_reset: process (trbclk) is
+ begin -- process register_reset
+ if rising_edge(trbclk) then -- rising clock edge
+ reset_reg <= reset;
+ end if;
+ end process register_reset;
+
mupix_sim_pll_1 : entity work.mupix_sim_pll
port map (
CLK => sendclk,
MupixStateMachine_1 : entity work.MupixStateMachine
port map (
clk => data_clk_i,
- reset => reset,
+ reset => reset_reg,
words => words_i,
slowdown => slowdown_i,
wr_en => fifo_wren_i,
RdClock => sim_clk_i,
WrEn => fifo_wren_i,
RdEn => fifo_rden_i,
- Reset => reset,
- RPReset => reset,
+ Reset => reset_reg,
+ RPReset => reset_reg,
Q => fifo_data_out,
Empty => fifo_empty_i,
Full => open);
DataOutput_1 : entity work.DataOutput
port map (
clk => sim_clk_i,
- reset => reset,
+ reset => reset_reg,
datain => fifo_data_out,
empty => fifo_empty_i,
rden => fifo_rden_i,
data_output_pipe : process (sim_clk_i) is
begin -- process data_output_pipe
if rising_edge(sim_clk_i) then -- rising clock edge
- if reset = '1' then -- synchronous reset (active high)
+ if reset_reg = '1' then -- synchronous reset (active high)
data_out_reg <= (others => '0');
else
data_out_reg <= data_out_i;
jspc29 / trb3.git / commitdiff