use work.trb_net_std.all;
entity Cal_Limits_v2 is
- generic (
- cal_Limit_gen : unsigned(19 downto 0) := "00000000000100000000";--"00000000000100000000";
- locBufDepth : integer := 7
- );
- port (
- CLK : in std_logic;
- cal_Limit_reg : in unsigned(19 downto 0);
- DIN : in std_logic_vector(31 downto 0);
- DIN_ready : in std_logic;
- DIN_type : in std_logic_vector( 3 downto 0);
- min_curr_in : in std_logic_vector( 9 downto 0);
- max_curr_in : in std_logic_vector( 9 downto 0);
- min_next_in : in std_logic_vector( 9 downto 0);
- max_next_in : in std_logic_vector( 9 downto 0);
- FPGA : in std_logic_vector( 3 downto 0);
- chnl : in std_logic_vector( 6 downto 0);
- Do_Cal_in : in std_logic;
- chnl_cnt_in : in unsigned(19 downto 0);
- BUS_Flash_value : in std_logic_vector(27 downto 0);
- Flash_flag : in std_logic;
- write_curr : out std_logic;
- write_next : out std_logic;
- min_next : out std_logic_vector( 9 downto 0);
- max_next : out std_logic_vector( 9 downto 0);
- min_curr : out std_logic_vector( 9 downto 0);
- max_curr : out std_logic_vector( 9 downto 0);
- min_out : out std_logic_vector( 9 downto 0);
- max_out : out std_logic_vector( 9 downto 0);
- Delta : out std_logic_vector( 9 downto 0);
- FPGA_out : out std_logic_vector( 3 downto 0);
- chnl_out : out std_logic_vector( 6 downto 0);
- FPGA_out_curr : out std_logic_vector( 3 downto 0);
- chnl_out_curr : out std_logic_vector( 6 downto 0);
- FPGA_out_write : out std_logic_vector( 3 downto 0);
- chnl_out_write : out std_logic_vector( 6 downto 0);
- FPGA_out_write_cnt : out std_logic_vector( 3 downto 0);
- chnl_out_write_cnt : out std_logic_vector( 6 downto 0);
- DOUT : out std_logic_vector(31 downto 0);
- DOUT_ready : out std_logic;
- DOUT_type : out std_logic_vector( 3 downto 0);
- Do_Cal_out : out std_logic;
- chnl_cnt_out : out unsigned (19 downto 0); --:="00000000000000000000";
- write_chnl_cnt : out std_logic;
- cal_Limit_set : out unsigned (19 downto 0);
- Debug_Data_min : out std_logic_vector(31 downto 0);
- Debug_Data_max : out std_logic_vector(31 downto 0)
- );
+ generic (
+ cal_Limit_gen : unsigned(19 downto 0) := "00000000000100000000";--"00000000000100000000";
+ locBufDepth : integer := 7;
+ USE_STAT_BITS : integer range 0 to 1 := c_NO;
+ USE_DATA_WRITE : integer range 0 to 1 := c_NO;
+ USE_DATA_FINISHED : integer range 0 to 1 := c_NO;
+ USE_BUSY_RELEASE : integer range 0 to 1 := c_NO
+ );
+ port (
+ CLK : in std_logic;
+ RESET : in std_logic;
+ stop_Limits : in std_logic;
+ cal_Limit_reg : in unsigned(19 downto 0);
+ DIN : in std_logic_vector(31 downto 0);
+ DIN_ready : in std_logic;
+ DIN_type : in std_logic_vector( 3 downto 0);
+ min_curr_in : in std_logic_vector( 9 downto 0);
+ max_curr_in : in std_logic_vector( 9 downto 0);
+ min_next_in : in std_logic_vector( 9 downto 0);
+ max_next_in : in std_logic_vector( 9 downto 0);
+ FPGA : in std_logic_vector( 3 downto 0);
+ chnl : in std_logic_vector( 6 downto 0);
+ Do_Cal_in : in std_logic;
+ chnl_cnt_in : in unsigned(19 downto 0);
+ BUS_Flash_value : in std_logic_vector(27 downto 0);
+ Flash_flag : in std_logic;
+ DIN_info : in std_logic_vector(( 31*USE_STAT_BITS + USE_DATA_WRITE + USE_DATA_FINISHED + USE_BUSY_RELEASE) downto 0);
+ write_curr : out std_logic;
+ write_next : out std_logic;
+ min_next : out std_logic_vector( 9 downto 0);
+ max_next : out std_logic_vector( 9 downto 0);
+ min_curr : out std_logic_vector( 9 downto 0);
+ max_curr : out std_logic_vector( 9 downto 0);
+ min_out : out std_logic_vector( 9 downto 0);
+ max_out : out std_logic_vector( 9 downto 0);
+ Delta : out std_logic_vector( 9 downto 0);
+ FPGA_out : out std_logic_vector( 3 downto 0);
+ chnl_out : out std_logic_vector( 6 downto 0);
+ FPGA_out_curr : out std_logic_vector( 3 downto 0);
+ chnl_out_curr : out std_logic_vector( 6 downto 0);
+ FPGA_out_write : out std_logic_vector( 3 downto 0);
+ chnl_out_write : out std_logic_vector( 6 downto 0);
+ FPGA_out_write_cnt : out std_logic_vector( 3 downto 0);
+ chnl_out_write_cnt : out std_logic_vector( 6 downto 0);
+ DOUT : out std_logic_vector(31 downto 0);
+ DOUT_ready : out std_logic;
+ DOUT_type : out std_logic_vector( 3 downto 0);
+ Do_Cal_out : out std_logic;
+ chnl_cnt_out : out unsigned (19 downto 0); --:="00000000000000000000";
+ write_chnl_cnt : out std_logic;
+ cal_Limit_set : out unsigned (19 downto 0);
+ Debug_Data_min : out std_logic_vector(31 downto 0);
+ Debug_Data_max : out std_logic_vector(31 downto 0);
+ DOUT_info : out std_logic_vector(( 31*USE_STAT_BITS + USE_DATA_WRITE + USE_DATA_FINISHED + USE_BUSY_RELEASE) downto 0)
+ );
end Cal_Limits_v2;
architecture Behavioral of Cal_Limits_v2 is
- signal Delta_i : std_logic_vector( 9 downto 0) := "0110110100";
- signal cnt_i : unsigned(19 downto 0):="00000000000000000000";
- signal cal_Limit : unsigned(19 downto 0):="00011000011010100000";--"00011000011010100000";
+ signal Delta_i : std_logic_vector( 9 downto 0) := "0110110100";
+ signal cnt_i : unsigned(19 downto 0):="00000000000000000000";
+ signal cal_Limit : unsigned(19 downto 0):="00011000011010100000";--"00011000011010100000";
- type array2D is array (1 downto 0, 0 to 64) of std_logic_vector(19 downto 0); --(FPGA)(channel)
- signal def_value : array2D := (others => ("10000000010000000010","10000000100000000010","10000000110000000010","10000001000000000010",
- "10000001010000000010","10000001100000000010","10000001110000000010","10000010000000000010",
- "10000010010000000010","10000010100000000010","10000010110000000010","10000011000000000010",
- "10000011010000000010","10000011100000000010", others => "11111000010000001111" ));
-
- type bit_2D is array (16 downto 0, 63 downto 0) of std_logic; --(channel)
- signal dflt_i : bit_2D := (others => (others => '1'));
+ type array2D is array (1 downto 0, 0 to 64) of std_logic_vector(19 downto 0); --(FPGA)(channel)
+ signal def_value : array2D := (others => ("10000000010000000010","10000000100000000010","10000000110000000010","10000001000000000010",
+ "10000001010000000010","10000001100000000010","10000001110000000010","10000010000000000010",
+ "10000010010000000010","10000010100000000010","10000010110000000010","10000011000000000010",
+ "10000011010000000010","10000011100000000010", others => "11111000010000001111" ));
+
+ type bit_2D is array (16 downto 0, 63 downto 0) of std_logic; --(channel)
+ signal dflt_i : bit_2D := (others => (others => '1'));
- type tLocalBuffer is array ( (locBufDepth-1) downto 0) of std_logic_vector(31 downto 0); --(Flag [31])(reserved [30] )(FPGA [29:26])(channel [25:20])(Max [19:10])(Min [9:0])
- signal EBRcntr : tLocalBuffer := (others =>(others => '0'));
- signal EBRbufCurr : tLocalBuffer := (others =>(others => '0'));
- signal EBRbufNext : tLocalBuffer := (others =>(x"3FF00"&b"00" & b"11" & x"FF"));
-
- signal DIN_r : std_logic_vector(31 downto 0);
- signal DIN_ready_r : std_logic;
- signal DIN_type_r : std_logic_vector( 3 downto 0);
- signal min_curr_in_r : std_logic_vector( 9 downto 0);
- signal max_curr_in_r : std_logic_vector( 9 downto 0);
- signal min_next_in_r : std_logic_vector( 9 downto 0):= "1111111111";
- signal max_next_in_r : std_logic_vector( 9 downto 0):= "0000000000";
- signal FPGA_r : std_logic_vector( 3 downto 0):= "0000";
- signal chnl_r : std_logic_vector( 6 downto 0);
- signal Do_Cal_in_r : std_logic;
+ type tLocalBuffer is array ( (locBufDepth-1) downto 0) of std_logic_vector(31 downto 0); --(Flag [31])(reserved [30] )(FPGA [29:26])(channel [25:20])(Max [19:10])(Min [9:0])
+ signal EBRcntr : tLocalBuffer := (others =>(others => '0'));
+ signal EBRbufCurr : tLocalBuffer := (others =>(others => '0'));
+ signal EBRbufNext : tLocalBuffer := (others =>(x"3FF00"&b"00" & b"11" & x"FF"));
+
+ signal DIN_r : std_logic_vector(31 downto 0);
+ signal DIN_ready_r : std_logic;
+ signal DIN_type_r : std_logic_vector( 3 downto 0);
+ signal min_curr_in_r : std_logic_vector( 9 downto 0);
+ signal max_curr_in_r : std_logic_vector( 9 downto 0);
+ signal min_next_in_r : std_logic_vector( 9 downto 0):= "1111111111";
+ signal max_next_in_r : std_logic_vector( 9 downto 0):= "0000000000";
+ signal FPGA_r : std_logic_vector( 3 downto 0):= "0000";
+ signal chnl_r : std_logic_vector( 6 downto 0);
+ signal Do_Cal_in_r : std_logic;
+ signal stop_Limits_r : std_logic;
+ signal DIN_info_r : std_logic_vector(( 31*USE_STAT_BITS + USE_DATA_WRITE + USE_DATA_FINISHED + USE_BUSY_RELEASE) downto 0);
begin
- Limit : process (CLK)
- begin
- if rising_edge(CLK) then
-
- if (cal_Limit_reg <= cal_Limit_gen) then
- cal_Limit <= cal_Limit_gen;
- cal_Limit_set <= cal_Limit_gen;
- else
- cal_Limit <= cal_Limit_reg;
- cal_Limit_set <= cal_Limit_reg;
- end if;
-
- end if;
- end process;
+ Limit : process (CLK)
+ begin
+ if rising_edge(CLK) then
+ if (cal_Limit_reg <= cal_Limit_gen) then
+ cal_Limit <= cal_Limit_gen;
+ cal_Limit_set <= cal_Limit_gen;
+ else
+ cal_Limit <= cal_Limit_reg;
+ cal_Limit_set <= cal_Limit_reg;
+ end if;
+ end if;
+ end process;
- Count : process (CLK)
- variable cnt_v : unsigned (19 downto 0);
- begin
- if rising_edge(CLK) then
- cnt_v := chnl_cnt_in;
+ Count : process (CLK)
+ variable cnt_v : unsigned (19 downto 0);
+ begin
+ if rising_edge(CLK) then
+ if (RESET = '1') then
+ --Reset behaviour
+ else
+ cnt_v := chnl_cnt_in;
- for i in 0 to (locBufDepth-1) loop
- if (EBRcntr(i)(31) = '1') and (EBRcntr(i)(29 downto 26) = FPGA) and (EBRcntr(i)(25 downto 20) = chnl(5 downto 0)) then
- cnt_v := unsigned(EBRcntr(i)(19 downto 0));
- end if;
- end loop;
+ for i in 0 to (locBufDepth-1) loop
+ if (EBRcntr(i)(31) = '1') and (EBRcntr(i)(29 downto 26) = FPGA) and (EBRcntr(i)(25 downto 20) = chnl(5 downto 0)) then
+ cnt_v := unsigned(EBRcntr(i)(19 downto 0));
+ end if;
+ end loop;
- for i in 0 to (locBufDepth-2) loop
- EBRcntr(i) <= EBRcntr(i+1);
- end loop;
-
- if Do_Cal_in = '1' then
- if cnt_v < cal_Limit then
- cnt_v := cnt_v + 1;
- else
- cnt_v := to_unsigned(0,20);
- dflt_i(to_integer(unsigned(FPGA)),to_integer(unsigned(chnl))) <= '0';
- end if;
- write_chnl_cnt <= '1';
- chnl_cnt_out <= cnt_v;
- cnt_i <= cnt_v;
- EBRcntr(locBufDepth-1) <= "10" & FPGA & chnl(5 downto 0) & std_logic_vector(cnt_v);
- else
- write_chnl_cnt <= '0';
- chnl_cnt_out <= x"00000";
- EBRcntr(locBufDepth-1) <= x"00000000";
- end if;
-
- --sync following processes with cnt_i
- fpga_r <= FPGA;
- chnl_r <= chnl;
- DIN_r <= DIN;
- DIN_ready_r <= DIN_ready;
- DIN_type_r <= DIN_type;
- min_curr_in_r <= min_curr_in;
- max_curr_in_r <= max_curr_in;
- min_next_in_r <= min_next_in;
- max_next_in_r <= max_next_in;
- Do_Cal_in_r <= Do_Cal_in;
- end if;
- end process;
+ for i in 0 to (locBufDepth-2) loop
+ EBRcntr(i) <= EBRcntr(i+1);
+ end loop;
+
+ if ((Do_Cal_in = '1') and (stop_Limits = '0')) then
+ if cnt_v < cal_Limit then
+ cnt_v := cnt_v + 1;
+ else
+ cnt_v := to_unsigned(0,20);
+ dflt_i(to_integer(unsigned(FPGA)),to_integer(unsigned(chnl))) <= '0';
+ end if;
+ write_chnl_cnt <= '1';
+ chnl_cnt_out <= cnt_v;
+ cnt_i <= cnt_v;
+ EBRcntr(locBufDepth-1) <= "10" & FPGA & chnl(5 downto 0) & std_logic_vector(cnt_v);
+ else
+ write_chnl_cnt <= '0';
+ chnl_cnt_out <= x"00000";
+ EBRcntr(locBufDepth-1) <= x"00000000";
+ end if;
+
+ end if;--reset|no calibration
+
+ --sync following processes with cnt_i
+ fpga_r <= FPGA;
+ chnl_r <= chnl;
+ DIN_r <= DIN;
+ DIN_ready_r <= DIN_ready;
+ DIN_type_r <= DIN_type;
+ min_curr_in_r <= min_curr_in;
+ max_curr_in_r <= max_curr_in;
+ min_next_in_r <= min_next_in;
+ max_next_in_r <= max_next_in;
+ Do_Cal_in_r <= Do_Cal_in;
+ stop_Limits_r <= stop_Limits;
+ DIN_info_r <= DIN_info;
+
+ end if;
+ end process;
- THE_Mem : process(CLK)
- variable EBRCurr_Min_v : std_logic_vector(9 downto 0):= "1111111111";
- variable EBRCurr_Max_v : std_logic_vector(9 downto 0):= "0000000000";
- variable EBRNext_Min_v : std_logic_vector(9 downto 0):= "1111111111";
- variable EBRNext_Max_v : std_logic_vector(9 downto 0):= "0000000000";
- begin
- if rising_edge(CLK) then
- --------- Current Values -----------------------------
- EBRCurr_Min_v := min_curr_in_r;
- EBRCurr_Max_v := max_curr_in_r;
+ THE_Mem : process(CLK)
+ variable EBRCurr_Min_v : std_logic_vector(9 downto 0):= "1111111111";
+ variable EBRCurr_Max_v : std_logic_vector(9 downto 0):= "0000000000";
+ variable EBRNext_Min_v : std_logic_vector(9 downto 0):= "1111111111";
+ variable EBRNext_Max_v : std_logic_vector(9 downto 0):= "0000000000";
+ begin
+ if rising_edge(CLK) then
+ if (RESET = '1') then
+ --Reset behaviour
+ else
+ --------- Current Values -----------------------------
+ EBRCurr_Min_v := min_curr_in_r;
+ EBRCurr_Max_v := max_curr_in_r;
- for i in 0 to (locBufDepth-1) loop
- if (EBRbufCurr(i)(31) = '1') and (EBRbufCurr(i)(29 downto 26) = FPGA_r) and (EBRbufCurr(i)(25 downto 20) = chnl_r(5 downto 0)) then
- EBRCurr_Min_v := EBRbufCurr(i)( 9 downto 0);
- EBRCurr_Max_v := EBRbufCurr(i)(19 downto 10);
- end if;
- end loop;
+ for i in 0 to (locBufDepth-1) loop
+ if (EBRbufCurr(i)(31) = '1') and (EBRbufCurr(i)(29 downto 26) = FPGA_r) and (EBRbufCurr(i)(25 downto 20) = chnl_r(5 downto 0)) then
+ EBRCurr_Min_v := EBRbufCurr(i)( 9 downto 0);
+ EBRCurr_Max_v := EBRbufCurr(i)(19 downto 10);
+ end if;
+ end loop;
- for i in 0 to (locBufDepth-2) loop
- EBRbufCurr(i) <= EBRbufCurr(i+1);
- end loop;
-
- --------- Next Values -----------------------------
- EBRNext_Min_v := min_next_in_r;
- EBRNext_Max_v := max_next_in_r;
-
- for i in 0 to (locBufDepth-1) loop
- if (EBRbufNext(i)(31) = '1') and (EBRbufNext(i)(29 downto 26) = FPGA_r) and (EBRbufNext(i)(25 downto 20) = chnl_r(5 downto 0)) then
- EBRNext_Min_v := EBRbufNext(i)( 9 downto 0);
- EBRNext_Max_v := EBRbufNext(i)(19 downto 10);
- end if;
- end loop;
+ for i in 0 to (locBufDepth-2) loop
+ EBRbufCurr(i) <= EBRbufCurr(i+1);
+ end loop;
+
+ --------- Next Values -----------------------------
+ EBRNext_Min_v := min_next_in_r;
+ EBRNext_Max_v := max_next_in_r;
+
+ for i in 0 to (locBufDepth-1) loop
+ if (EBRbufNext(i)(31) = '1') and (EBRbufNext(i)(29 downto 26) = FPGA_r) and (EBRbufNext(i)(25 downto 20) = chnl_r(5 downto 0)) then
+ EBRNext_Min_v := EBRbufNext(i)( 9 downto 0);
+ EBRNext_Max_v := EBRbufNext(i)(19 downto 10);
+ end if;
+ end loop;
- for i in 0 to (locBufDepth-2) loop
- EBRbufNext(i) <= EBRbufNext(i+1);
- end loop;
+ for i in 0 to (locBufDepth-2) loop
+ EBRbufNext(i) <= EBRbufNext(i+1);
+ end loop;
- --------------------------------------------------------------
- -------------------------- CURRENT -------------------------
- --------------------------------------------------------------
- if dflt_i(to_integer(unsigned(FPGA_r)),to_integer(unsigned(chnl_r))) = '0' then
- if Do_Cal_in_r = '1' then
- if cnt_i /= to_unsigned(0,20) then
- min_out <= EBRCurr_Min_v;
- max_out <= EBRCurr_Max_v;
- if (unsigned(EBRCurr_Min_v) < unsigned(EBRCurr_Max_v)) then
- Delta_i <= std_logic_vector(unsigned(EBRCurr_Max_v) - unsigned(EBRCurr_Min_v));
- else
- Delta_i <= "0110110100";
- end if;
- min_curr <= EBRCurr_Min_v;
- max_curr <= EBRCurr_Max_v;
- write_curr <= '0';
- EBRbufCurr(locBufDepth-1) <= "10" & FPGA_r & chnl_r(5 downto 0) & EBRCurr_Max_v & EBRCurr_Min_v;
- else
- min_out <= EBRNext_Min_v;
- max_out <= EBRNext_Max_v;
- min_curr <= EBRNext_Min_v;
- max_curr <= EBRNext_Max_v;
- if (unsigned(EBRNext_Min_v) < unsigned(EBRNext_Max_v)) then
- Delta_i <= std_logic_vector(unsigned(EBRNext_Max_v) - unsigned(EBRNext_Min_v));
- else
- Delta_i <= "0110110100";
- end if;
- write_curr <= '1';
- EBRbufCurr(locBufDepth-1) <= "10" & FPGA_r & chnl_r(5 downto 0) & EBRNext_Max_v & EBRNext_Min_v;
- end if;
- else -- no calibr
- write_curr <= '0';
- write_next <= '0';
- --min_out <= "1111111111";
- --max_out <= "0000000000";
- --min_curr <= "1111111111";
- --max_curr <= "0000000000";
- EBRbufNext(locBufDepth-1) <= x"00000000";
- EBRbufCurr(locBufDepth-1) <= x"00000000";
- end if;
- elsif dflt_i(to_integer(unsigned(FPGA_r)),to_integer(unsigned(chnl_r))) = '1' then
- --FLASH
- if Do_Cal_in_r = '1' then
- write_curr <= '1';
- min_out <= def_value(0,to_integer(unsigned(chnl_r)))( 9 downto 0);
- max_out <= def_value(0,to_integer(unsigned(chnl_r)))(19 downto 10);
- min_curr <= def_value(0,to_integer(unsigned(chnl_r)))( 9 downto 0);
- max_curr <= def_value(0,to_integer(unsigned(chnl_r)))(19 downto 10);
- Delta_i <= std_logic_vector(unsigned(def_value(0,to_integer(unsigned(chnl_r)))(19 downto 10)) - unsigned(def_value(0,to_integer(unsigned(chnl_r)))(9 downto 0)));
- EBRbufCurr(locBufDepth-1) <= "10" & FPGA_r & chnl_r(5 downto 0) & def_value(0,to_integer(unsigned(chnl_r)))(19 downto 10) & def_value(0,to_integer(unsigned(chnl_r)))( 9 downto 0);
- else
- write_curr <= '0';
- --min_out <= b"0000000000";
- --max_out <= b"0000000000";
- min_curr <= b"0000000000";
- max_curr <= b"0000000000";
- Delta_i <= b"0000000000";
- EBRbufCurr(locBufDepth-1) <= x"00000000";
- end if;
- else
- write_curr <= '0';
- min_out <= "0000000100";
- max_out <= "1000000000";
- min_curr <= "0000000100";
- max_curr <= "1000000000";
- Delta_i <= "0111111011";--"0111111110";
- if Do_Cal_in_r = '1' then
- EBRbufCurr(locBufDepth-1) <= "10" & FPGA_r & chnl_r(5 downto 0) & "1000000000" & "0000000100";
- else
- EBRbufCurr(locBufDepth-1) <= x"00000000";
- end if;
- end if;--default value
+ --------------------------------------------------------------
+ -------------------------- CURRENT -------------------------
+ --------------------------------------------------------------
+ if dflt_i(to_integer(unsigned(FPGA_r)),to_integer(unsigned(chnl_r))) = '0' then
+ if Do_Cal_in_r = '1' then
+ if cnt_i /= to_unsigned(0,20) then
+ min_out <= EBRCurr_Min_v;
+ max_out <= EBRCurr_Max_v;
+ if (unsigned(EBRCurr_Min_v) < unsigned(EBRCurr_Max_v)) then
+ Delta_i <= std_logic_vector(unsigned(EBRCurr_Max_v) - unsigned(EBRCurr_Min_v));
+ else
+ Delta_i <= "0110110100";
+ end if;
+ min_curr <= EBRCurr_Min_v;
+ max_curr <= EBRCurr_Max_v;
+ write_curr <= '0';
+ EBRbufCurr(locBufDepth-1) <= "10" & FPGA_r & chnl_r(5 downto 0) & EBRCurr_Max_v & EBRCurr_Min_v;
+ else
+ min_out <= EBRNext_Min_v;
+ max_out <= EBRNext_Max_v;
+ min_curr <= EBRNext_Min_v;
+ max_curr <= EBRNext_Max_v;
+ if (unsigned(EBRNext_Min_v) < unsigned(EBRNext_Max_v)) then
+ Delta_i <= std_logic_vector(unsigned(EBRNext_Max_v) - unsigned(EBRNext_Min_v));
+ else
+ Delta_i <= "0110110100";
+ end if;
+ write_curr <= '1';
+ EBRbufCurr(locBufDepth-1) <= "10" & FPGA_r & chnl_r(5 downto 0) & EBRNext_Max_v & EBRNext_Min_v;
+ end if;
+ else -- no calibr
+ write_curr <= '0';
+ write_next <= '0';
+ --min_out <= "1111111111";
+ --max_out <= "0000000000";
+ --min_curr <= "1111111111";
+ --max_curr <= "0000000000";
+ EBRbufNext(locBufDepth-1) <= x"00000000";
+ EBRbufCurr(locBufDepth-1) <= x"00000000";
+ end if;
+ elsif dflt_i(to_integer(unsigned(FPGA_r)),to_integer(unsigned(chnl_r))) = '1' then
+ --FLASH
+ if Do_Cal_in_r = '1' then
+ write_curr <= '1';
+ min_out <= def_value(0,to_integer(unsigned(chnl_r)))( 9 downto 0);
+ max_out <= def_value(0,to_integer(unsigned(chnl_r)))(19 downto 10);
+ min_curr <= def_value(0,to_integer(unsigned(chnl_r)))( 9 downto 0);
+ max_curr <= def_value(0,to_integer(unsigned(chnl_r)))(19 downto 10);
+ Delta_i <= std_logic_vector(unsigned(def_value(0,to_integer(unsigned(chnl_r)))(19 downto 10)) - unsigned(def_value(0,to_integer(unsigned(chnl_r)))(9 downto 0)));
+ EBRbufCurr(locBufDepth-1) <= "10" & FPGA_r & chnl_r(5 downto 0) & def_value(0,to_integer(unsigned(chnl_r)))(19 downto 10) & def_value(0,to_integer(unsigned(chnl_r)))( 9 downto 0);
+ else
+ write_curr <= '0';
+ --min_out <= b"0000000000";
+ --max_out <= b"0000000000";
+ min_curr <= b"0000000000";
+ max_curr <= b"0000000000";
+ Delta_i <= b"0000000000";
+ EBRbufCurr(locBufDepth-1) <= x"00000000";
+ end if;
+ else
+ write_curr <= '0';
+ min_out <= "0000000100";
+ max_out <= "1000000000";
+ min_curr <= "0000000100";
+ max_curr <= "1000000000";
+ Delta_i <= "0111111011";--"0111111110";
+ if Do_Cal_in_r = '1' then
+ EBRbufCurr(locBufDepth-1) <= "10" & FPGA_r & chnl_r(5 downto 0) & "1000000000" & "0000000100";
+ else
+ EBRbufCurr(locBufDepth-1) <= x"00000000";
+ end if;
+ end if;--default value
- --------------------------------------------------------------
- ----------------------------- NEXT -------------------------
- --------------------------------------------------------------
- if Do_Cal_in_r = '1' then
- write_next <= '1';
- if cnt_i /= to_unsigned(0,20) then --next memory
- if unsigned(DIN_r(21 downto 12)) >= unsigned(EBRNext_Max_v) then
- EBRNext_Max_v := DIN_r(21 downto 12);
- Debug_Data_max <= DIN_r;
- if unsigned(DIN_r(21 downto 12)) < unsigned(EBRNext_Min_v) then
- EBRNext_Min_v := DIN_r(21 downto 12);
- Debug_Data_min <= DIN_r;
- end if;
- else
- if unsigned(DIN_r(21 downto 12)) < unsigned(EBRNext_Min_v) then
- EBRNext_Min_v := DIN_r(21 downto 12);
- Debug_Data_min <= DIN_r;
- end if;
- end if;
- else
- EBRNext_Min_v := DIN_r(21 downto 12);--"1111111111";
- EBRNext_Max_v := DIN_r(21 downto 12);--"0000000000";
- end if; --/= 0
- EBRbufNext(locBufDepth-1)<= "10" & FPGA_r & chnl_r(5 downto 0) & EBRNext_Max_v & EBRNext_Min_v;
- min_next <= EBRNext_Min_v;
- max_next <= EBRNext_Max_v;
- else -- no calib
- write_next <= '0';
- min_next <= "1010101010";
- max_next <= "0101010101";
- EBRbufNext(locBufDepth-1) <= (x"3FF00"&b"00" & b"11" & x"FF");
- end if;
-
- end if;--rising_edge
- end process;
+ --------------------------------------------------------------
+ ----------------------------- NEXT -------------------------
+ --------------------------------------------------------------
+ if ((Do_Cal_in_r = '1') and (stop_Limits_r = '0')) then
+ write_next <= '1';
+ if cnt_i /= to_unsigned(0,20) then --next memory
+ if unsigned(DIN_r(21 downto 12)) >= unsigned(EBRNext_Max_v) then
+ EBRNext_Max_v := DIN_r(21 downto 12);
+ Debug_Data_max <= DIN_r;
+ if unsigned(DIN_r(21 downto 12)) < unsigned(EBRNext_Min_v) then
+ EBRNext_Min_v := DIN_r(21 downto 12);
+ Debug_Data_min <= DIN_r;
+ end if;
+ else
+ if unsigned(DIN_r(21 downto 12)) < unsigned(EBRNext_Min_v) then
+ EBRNext_Min_v := DIN_r(21 downto 12);
+ Debug_Data_min <= DIN_r;
+ end if;
+ end if;
+ else
+ EBRNext_Min_v := DIN_r(21 downto 12);--"1111111111";
+ EBRNext_Max_v := DIN_r(21 downto 12);--"0000000000";
+ end if; --/= 0
+ EBRbufNext(locBufDepth-1)<= "10" & FPGA_r & chnl_r(5 downto 0) & EBRNext_Max_v & EBRNext_Min_v;
+ min_next <= EBRNext_Min_v;
+ max_next <= EBRNext_Max_v;
+ else -- no calib
+ write_next <= '0';
+ min_next <= "1010101010";
+ max_next <= "0101010101";
+ EBRbufNext(locBufDepth-1) <= (x"3FF00"&b"00" & b"11" & x"FF");
+ end if;
+ end if; -- reset| Calibration
+ end if;--rising_edge
+ end process;
- proc_Flash_input : process (CLK)
- begin
- if rising_edge(CLK) then
- if Flash_flag = '1' then
- def_value(0,to_integer(unsigned(BUS_Flash_value(27 downto 20))))( 19 downto 0) <= BUS_Flash_value(19 downto 0);
- end if;
- end if;
- end process;
+ proc_Flash_input : process (CLK)
+ begin
+ if rising_edge(CLK) then
+ --if RESET = '1' then
+ --RESET
+ --elsif (stop_Limits_r = '0') then
+ if Flash_flag = '1' then
+ def_value(0,to_integer(unsigned(BUS_Flash_value(27 downto 20))))( 19 downto 0) <= BUS_Flash_value(19 downto 0);
+ end if;
+ --end if;
+ end if;
+ end process;
- --synchronous output
- proc_slope : process (CLK)
- begin
- if rising_edge(CLK) then
- DOUT <= DIN_r;
- DOUT_ready <= DIN_ready_r;
- DOUT_type <= DIN_type_r;
- Do_Cal_out <= Do_Cal_in_r;
- chnl_out_write <= chnl_r;
- FPGA_out_write <= fpga_r;
- FPGA_out <= fpga_r;
- FPGA_out_curr <= fpga_r;
-
- chnl_out <= chnl_r;
- chnl_out_curr <= chnl_r;
- end if;
- end process;
+ --synchronous output
+ proc_slope : process (CLK)
+ begin
+ if rising_edge(CLK) then
+ DOUT <= DIN_r;
+ DOUT_ready <= DIN_ready_r;
+ DOUT_type <= DIN_type_r;
+ DOUT_info <= DIN_info_r;
+ Do_Cal_out <= Do_Cal_in_r;
+ chnl_out_write <= chnl_r;
+ FPGA_out_write <= fpga_r;
+ FPGA_out <= fpga_r;
+ FPGA_out_curr <= fpga_r;
+
+ chnl_out <= chnl_r;
+ chnl_out_curr <= chnl_r;
+ end if;
+ end process;
- chnl_out_write_cnt <= chnl_r;
- FPGA_out_write_cnt <= fpga_r;
- Delta <= Delta_i;
+ chnl_out_write_cnt <= chnl_r;
+ FPGA_out_write_cnt <= fpga_r;
+ Delta <= Delta_i;
end Behavioral;
\ No newline at end of file
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
+library work;
+use work.trb_net_std.all;
entity calc_output is
- Port (
- CLK : in std_logic;
- DIN : in std_logic_vector(31 downto 0);
- DIN_ready : in std_logic;
- DIN_type : in std_logic_vector( 3 downto 0);
- do_cal_in : in std_logic;
- overshoot_in : in std_logic := '0';
- undershoot_in : in std_logic := '0';
- slope : in std_logic_vector(11 downto 0);
- factor : in std_logic_vector( 9 downto 0);
- DOUT : out std_logic_vector(31 downto 0);
- DOUT_ready : out std_logic;
- DOUT_type : out std_logic_vector( 3 downto 0);
- do_cal_out : out std_logic;
- overshoot_out : out std_logic := '0';
- undershoot_out : out std_logic := '0';
- Cal_Data_out : out std_logic_vector(21 downto 0)
- );
+ generic (
+ USE_STAT_BITS : integer range 0 to 1 := c_NO;
+ USE_DATA_WRITE : integer range 0 to 1 := c_NO;
+ USE_DATA_FINISHED : integer range 0 to 1 := c_NO;
+ USE_BUSY_RELEASE : integer range 0 to 1 := c_NO
+ );
+ port (
+ CLK : in std_logic;
+ DIN : in std_logic_vector(31 downto 0);
+ DIN_ready : in std_logic;
+ DIN_type : in std_logic_vector( 3 downto 0);
+ do_cal_in : in std_logic;
+ overshoot_in : in std_logic := '0';
+ undershoot_in : in std_logic := '0';
+ slope : in std_logic_vector(11 downto 0);
+ factor : in std_logic_vector( 9 downto 0);
+ DIN_info : in std_logic_vector(( 31*USE_STAT_BITS + USE_DATA_WRITE + USE_DATA_FINISHED + USE_BUSY_RELEASE) downto 0);
+ DOUT : out std_logic_vector(31 downto 0);
+ DOUT_ready : out std_logic;
+ DOUT_type : out std_logic_vector( 3 downto 0);
+ do_cal_out : out std_logic;
+ overshoot_out : out std_logic := '0';
+ undershoot_out : out std_logic := '0';
+ Cal_Data_out : out std_logic_vector(21 downto 0);
+ DOUT_info : out std_logic_vector(( 31*USE_STAT_BITS + USE_DATA_WRITE + USE_DATA_FINISHED + USE_BUSY_RELEASE) downto 0)
+ );
end calc_output;
architecture Behavioral of calc_output is
-
begin
- cnt : process (CLK,factor,slope)
- begin
- if rising_edge(CLK) then
- Cal_Data_out <= std_logic_vector( (unsigned(factor) * unsigned(slope)) + to_unsigned(512,9));
- DOUT <= DIN;
- DOUT_ready <= DIN_ready;
- DOUT_type <= DIN_type;
- do_cal_out <= do_cal_in;
- overshoot_out <= overshoot_in;
- undershoot_out <= undershoot_in;
- end if;
- end process;
+
+ cnt : process (CLK,factor,slope)
+ begin
+ if rising_edge(CLK) then
+ Cal_Data_out <= std_logic_vector( (unsigned(factor) * unsigned(slope)) + to_unsigned(512,9));
+ DOUT <= DIN;
+ DOUT_ready <= DIN_ready;
+ DOUT_type <= DIN_type;
+ do_cal_out <= do_cal_in;
+ overshoot_out <= overshoot_in;
+ undershoot_out <= undershoot_in;
+ DOUT_info <= DIN_info;
+ end if;
+ end process;
end Behavioral;
-- Engineer: Adrian Weber
--
-- Create Date: 06.01.2017 13:32:05
+-- Update Date: 13.11.2018 09:42:20
-- Module Name: Calibration - Behavioral
-- Project Name: TDC Calibration
-- Target Devices: TrbSc
use work.trb_net_std.all;
entity TDC_Calibration is
- Port (
- CLK : in std_logic;
- RESET : in std_logic;
- DIN : in std_logic_vector(31 downto 0);
- DIN_TYPE : in std_logic_vector( 3 downto 0);
- DIN_READY : in std_logic;
- DIN_STAT : in std_logic_vector(31 downto 0);
- FPGA_in : in std_logic_vector(15 downto 0);
- DOUT : out std_logic_vector(31 downto 0);
- DOUT_TYPE : out std_logic_vector( 3 downto 0);
- DOUT_READY : out std_logic;
- DOUT_STAT : out std_logic_vector(31 downto 0);
- BUS_RX : in CTRLBUS_RX;
- BUS_TX : out CTRLBUS_TX
- );
+ generic (
+ IS_COMBINER : integer range 0 to 1 := c_YES;
+ USE_STAT_BITS : integer range 0 to 1 := c_NO;
+ USE_DATA_WRITE : integer range 0 to 1 := c_NO;
+ USE_DATA_FINISHED : integer range 0 to 1 := c_NO;
+ USE_BUSY_RELEASE : integer range 0 to 1 := c_NO );
+ port (
+ CLK : in std_logic;
+ RESET : in std_logic;
+ DIN : in std_logic_vector(31 downto 0);
+ DIN_TYPE : in std_logic_vector( 3 downto 0);
+ DIN_READY : in std_logic;
+ DIN_STAT : in std_logic_vector((31*IS_COMBINER) downto 0);
+ FPGA_in : in std_logic_vector(15 downto 0);
+ TRIGG_TYPE : in std_logic_vector( 3 downto 0);
+ DOUT : out std_logic_vector(31 downto 0);
+ DOUT_TYPE : out std_logic_vector( 3 downto 0);
+ DOUT_READY : out std_logic;
+ DOUT_STAT : out std_logic_vector((31*IS_COMBINER) downto 0);
+ BUS_RX : in CTRLBUS_RX;
+ BUS_TX : out CTRLBUS_TX;
+ DIN_info : in std_logic_vector(( 31*USE_STAT_BITS + USE_DATA_WRITE + USE_DATA_FINISHED + USE_BUSY_RELEASE) downto 0);
+ DOUT_info : out std_logic_vector(( 31*USE_STAT_BITS + USE_DATA_WRITE + USE_DATA_FINISHED + USE_BUSY_RELEASE) downto 0)
+ );
end TDC_Calibration;
architecture Behavioral of TDC_Calibration is
- signal Dout_int : std_logic_vector(21 downto 0);
- signal DIN_i_Mem : std_logic_vector(31 downto 0) := (others => '0');
- signal DIN_i_Mem_ready : std_logic;
- signal DIN_i_Mem_type : std_logic_vector( 3 downto 0);
- signal DIN_o_Lim : std_logic_vector(31 downto 0) := (others => '0');
- signal DIN_o_Lim_ready : std_logic;
- signal DIN_o_Lim_type : std_logic_vector( 3 downto 0);
- signal min_out_Lim : std_logic_vector( 9 downto 0) := (others => '1');
- signal max_out_Lim : std_logic_vector( 9 downto 0) := (others => '0');
- signal Delta_Lim : std_logic_vector( 9 downto 0) := "0110110100";
- signal min_next_Lim : std_logic_vector( 9 downto 0) := (others => '1');
- signal max_next_Lim : std_logic_vector( 9 downto 0) := (others => '0');
- signal min_curr_Lim : std_logic_vector( 9 downto 0) := (others => '1');
- signal max_curr_Lim : std_logic_vector( 9 downto 0) := (others => '0');
- signal FPGA_Lim : std_logic_vector( 3 downto 0) ;
- signal chnl_Lim : std_logic_vector( 6 downto 0) := (others => '0');
- signal do_cal_LIM : std_logic;
- signal DIN_o_LUT : std_logic_vector(31 downto 0) := (others => '0');
- signal DIN_o_LUT_ready : std_logic;
- signal DIN_o_LUT_type : std_logic_vector( 3 downto 0);
- signal min_out_LUT : std_logic_vector( 9 downto 0) := (others => '0');
- signal max_out_LUT : std_logic_vector( 9 downto 0) := (others => '1');
- signal slope_LUT : std_logic_vector(11 downto 0) := (others => '0');
- signal cal_flag_LUT_out : std_logic := '0';
- signal write_next : std_logic;
- signal min_next : std_logic_vector( 9 downto 0):= "1111111111";
- signal max_next : std_logic_vector( 9 downto 0);
- signal write_curr : std_logic;
- signal min_curr : std_logic_vector( 9 downto 0);
- signal max_curr : std_logic_vector( 9 downto 0);
- signal factor : std_logic_vector( 9 downto 0);
- signal DIN_o_cnt : std_logic_vector(31 downto 0);
- signal DIN_o_cnt_ready : std_logic;
- signal DIN_o_cnt_type : std_logic_vector( 3 downto 0);
- signal FPGA_o_cnt : std_logic_vector( 3 downto 0);
- signal chnl_read_cnt : std_logic_vector( 6 downto 0);
- signal cal_cnt_in : unsigned(19 downto 0);
- signal cal_cnt_out : unsigned(19 downto 0);
- signal DIN_o_cnt_val : std_logic_vector(31 downto 0);
- signal DIN_o_cnt_val_ready : std_logic;
- signal DIN_o_cnt_val_type : std_logic_vector( 3 downto 0);
- signal DIN_MemCurr_data : std_logic_vector(31 downto 0);
- signal DIN_MemCurr_ready : std_logic;
- signal DIN_MemCurr_type : std_logic_vector( 3 downto 0);
- signal Do_Cal_read_cnt : std_logic;
- signal CHNL_out_Memory : std_logic_vector( 6 downto 0);
- signal FPGA_out_Memory : std_logic_vector( 3 downto 0);
- signal Do_Cal_Memory : std_logic;
- signal write_chnl_cnt : std_logic;
- signal chnl_out_write : std_logic_vector( 6 downto 0);
- signal FPGA_out_write : std_logic_vector( 3 downto 0);
- signal BUS_do_Cal : std_logic := '1';
- signal overshoot_LUT : std_logic := '0';
- signal undershoot_LUT : std_logic := '0';
- signal Cal_Limit_reg : unsigned(19 downto 0) := "00011000011010100000";
- signal cal_Limit_set : unsigned(19 downto 0);
- signal Do_cal_CalcOut : std_logic := '0';
- signal DIN_o_CalcOut : std_logic_vector(31 downto 0);
- signal DIN_o_CalcOut_ready : std_logic;
- signal DIN_o_CalcOut_type : std_logic_vector( 3 downto 0);
- signal overshoot_CalcOut : std_logic := '0';
- signal undershoot_CalcOut : std_logic := '0';
- signal Bus_Chnl : std_logic_vector( 6 downto 0);
- signal Bus_FPGA : std_logic_vector( 3 downto 0);
- signal Bus_min : std_logic_vector( 9 downto 0);
- signal Bus_max : std_logic_vector( 9 downto 0);
- signal FPGA_out_curr : std_logic_vector( 3 downto 0);
- signal chnl_out_curr : std_logic_vector( 6 downto 0);
- signal BUS_Flash_value : std_logic_vector(27 downto 0);
- signal Flash_flag : std_logic;
- signal chnl_out_write_cnt : std_logic_vector( 6 downto 0);
- signal FPGA_out_write_cnt : std_logic_vector( 3 downto 0);
-
- signal docal_debug_out : unsigned(31 downto 0);
- signal docal_debug_in : unsigned(31 downto 0);
- signal Debug_Data_min : std_logic_vector(31 downto 0);
- signal Debug_Data_max : std_logic_vector(31 downto 0);
-
- type array_16_16_t is array (0 to 15) of std_logic_vector(15 downto 0);
- signal FPGA_mntr_i : array_16_16_t := (others => (others=> '0'));
- signal FPGA_cnt_mntr : std_logic_vector( 3 downto 0);
- signal FPGA_mntr : std_logic_vector(15 downto 0);
- type MinMax_t is array (0 to 15, 0 to 63) of std_logic_vector(19 downto 0);
- signal MinMax_Monitor : MinMax_t := (others=>(others=>(others=>'0')));
+ signal Dout_int : std_logic_vector(21 downto 0);
+ signal DIN_i_Mem : std_logic_vector(31 downto 0) := (others => '0');
+ signal DIN_i_Mem_ready : std_logic;
+ signal DIN_i_Mem_type : std_logic_vector( 3 downto 0);
+ signal DIN_o_Lim : std_logic_vector(31 downto 0) := (others => '0');
+ signal DIN_o_Lim_ready : std_logic;
+ signal DIN_o_Lim_type : std_logic_vector( 3 downto 0);
+ signal min_out_Lim : std_logic_vector( 9 downto 0) := (others => '1');
+ signal max_out_Lim : std_logic_vector( 9 downto 0) := (others => '0');
+ signal Delta_Lim : std_logic_vector( 9 downto 0) := "0110110100";
+ signal min_next_Lim : std_logic_vector( 9 downto 0) := (others => '1');
+ signal max_next_Lim : std_logic_vector( 9 downto 0) := (others => '0');
+ signal min_curr_Lim : std_logic_vector( 9 downto 0) := (others => '1');
+ signal max_curr_Lim : std_logic_vector( 9 downto 0) := (others => '0');
+ signal FPGA_Lim : std_logic_vector( 3 downto 0) ;
+ signal chnl_Lim : std_logic_vector( 6 downto 0) := (others => '0');
+ signal do_cal_LIM : std_logic;
+ signal DIN_o_LUT : std_logic_vector(31 downto 0) := (others => '0');
+ signal DIN_o_LUT_ready : std_logic;
+ signal DIN_o_LUT_type : std_logic_vector( 3 downto 0);
+ signal min_out_LUT : std_logic_vector( 9 downto 0) := (others => '0');
+ signal max_out_LUT : std_logic_vector( 9 downto 0) := (others => '1');
+ signal slope_LUT : std_logic_vector(11 downto 0) := (others => '0');
+ signal cal_flag_LUT_out : std_logic := '0';
+ signal write_next : std_logic;
+ signal min_next : std_logic_vector( 9 downto 0):= "1111111111";
+ signal max_next : std_logic_vector( 9 downto 0);
+ signal write_curr : std_logic;
+ signal min_curr : std_logic_vector( 9 downto 0);
+ signal max_curr : std_logic_vector( 9 downto 0);
+ signal factor_LUT : std_logic_vector( 9 downto 0);
+ signal DIN_o_cnt : std_logic_vector(31 downto 0);
+ signal DIN_o_cnt_ready : std_logic;
+ signal DIN_o_cnt_type : std_logic_vector( 3 downto 0);
+ signal FPGA_o_cnt : std_logic_vector( 3 downto 0);
+ signal chnl_read_cnt : std_logic_vector( 6 downto 0);
+ signal cal_cnt_in : unsigned(19 downto 0);
+ signal cal_cnt_out : unsigned(19 downto 0);
+ signal DIN_o_cnt_val : std_logic_vector(31 downto 0);
+ signal DIN_o_cnt_val_ready : std_logic;
+ signal DIN_o_cnt_val_type : std_logic_vector( 3 downto 0);
+ signal DIN_MemCurr_data : std_logic_vector(31 downto 0);
+ signal DIN_MemCurr_ready : std_logic;
+ signal DIN_MemCurr_type : std_logic_vector( 3 downto 0);
+ signal Do_Cal_read_cnt : std_logic;
+ signal CHNL_out_Memory : std_logic_vector( 6 downto 0);
+ signal FPGA_out_Memory : std_logic_vector( 3 downto 0);
+ signal Do_Cal_Memory : std_logic;
+ signal write_chnl_cnt : std_logic;
+ signal chnl_out_write : std_logic_vector( 6 downto 0);
+ signal FPGA_out_write : std_logic_vector( 3 downto 0);
+ signal BUS_do_Cal : std_logic := '1';
+ signal overshoot_LUT : std_logic := '0';
+ signal undershoot_LUT : std_logic := '0';
+ signal Cal_Limit_reg : unsigned(19 downto 0) := "00011000011010100000";
+ signal cal_Limit_set : unsigned(19 downto 0);
+ signal Do_cal_CalcOut : std_logic := '0';
+ signal DIN_o_CalcOut : std_logic_vector(31 downto 0);
+ signal DIN_o_CalcOut_ready : std_logic;
+ signal DIN_o_CalcOut_type : std_logic_vector( 3 downto 0);
+ signal overshoot_CalcOut : std_logic := '0';
+ signal undershoot_CalcOut : std_logic := '0';
+ signal Bus_Chnl : std_logic_vector( 6 downto 0);
+ signal Bus_FPGA : std_logic_vector( 3 downto 0);
+ signal Bus_min : std_logic_vector( 9 downto 0);
+ signal Bus_max : std_logic_vector( 9 downto 0);
+ signal FPGA_out_curr : std_logic_vector( 3 downto 0);
+ signal chnl_out_curr : std_logic_vector( 6 downto 0);
+ signal BUS_Flash_value : std_logic_vector(27 downto 0);
+ signal Flash_flag : std_logic;
+ signal chnl_out_write_cnt : std_logic_vector( 6 downto 0);
+ signal FPGA_out_write_cnt : std_logic_vector( 3 downto 0);
+
+ signal docal_debug_out : unsigned(31 downto 0);
+ signal docal_debug_in : unsigned(31 downto 0);
+ signal Debug_Data_min : std_logic_vector(31 downto 0);
+ signal Debug_Data_max : std_logic_vector(31 downto 0);
+
+ type array_16_16_t is array (0 to 15) of std_logic_vector(15 downto 0);
+ signal FPGA_mntr_i : array_16_16_t := (others => (others=> '0'));
+ signal FPGA_cnt_mntr : std_logic_vector( 3 downto 0);
+ signal FPGA_mntr : std_logic_vector(15 downto 0);
+ type MinMax_t is array (0 to 15, 0 to 63) of std_logic_vector(19 downto 0);
+ signal MinMax_Monitor : MinMax_t := (others=>(others=>(others=>'0')));
+ signal BUS_stop_LimitGen : std_logic := '0';
+ signal BUS_Trig_type : std_logic_vector( 3 downto 0):="0000";
+ signal stop_Limits_r : std_logic := '0';
+ signal stp_Lmt_read_cnt : std_logic := '0';
+ signal stp_Lmt_MemCurr : std_logic := '0';
+
+ signal MonitorRam_plcHldr1 : std_logic_vector( 5 downto 0);
+ signal MonitorRam_plcHldr2 : std_logic_vector( 9 downto 0);
+
+ signal Max_Monitoring : std_logic_vector( 9 downto 0):="1010101010";
+ signal Min_Monitoring : std_logic_vector( 9 downto 0):="1010101010";
+
+ signal Monitor_RAM_RE : std_logic := '0';
+ signal Monitor_RAM_AddFPGA : std_logic_vector( 3 downto 0);
+ signal Monitor_RAM_AddChnl : std_logic_vector( 6 downto 0);
+
+ signal Monitor_RAM_ready : std_logic := '0';
+ signal Monitor_RAM_ready_i : std_logic := '0';
+ signal Monitor_RAM_ready_r : std_logic := '0';
+
+ signal DIN_delay : std_logic_vector(31 downto 0);
+ signal DIN_ready_delay : std_logic;
+ signal DIN_type_delay : std_logic_vector( 3 downto 0);
+ signal slope_delay : std_logic_vector(11 downto 0) := (others => '0');
+ signal do_cal_delay : std_logic := '0';
+ signal factor_delay : std_logic_vector( 9 downto 0);
+ signal overshoot_delay : std_logic := '0';
+ signal undershoot_delay : std_logic := '0';
+
+ signal trig_type_in : std_logic_vector( 3 downto 0):= "0000";
+
+ signal DIN_info_rc : std_logic_vector(( 31*USE_STAT_BITS + USE_DATA_WRITE + USE_DATA_FINISHED + USE_BUSY_RELEASE) downto 0) := (others => '0');
+ signal DIN_info_mem : std_logic_vector(( 31*USE_STAT_BITS + USE_DATA_WRITE + USE_DATA_FINISHED + USE_BUSY_RELEASE) downto 0) := (others => '0');
+ signal DIN_info_LUT : std_logic_vector(( 31*USE_STAT_BITS + USE_DATA_WRITE + USE_DATA_FINISHED + USE_BUSY_RELEASE) downto 0) := (others => '0');
+ signal DIN_info_Lim : std_logic_vector(( 31*USE_STAT_BITS + USE_DATA_WRITE + USE_DATA_FINISHED + USE_BUSY_RELEASE) downto 0) := (others => '0');
+ signal DIN_info_delay : std_logic_vector(( 31*USE_STAT_BITS + USE_DATA_WRITE + USE_DATA_FINISHED + USE_BUSY_RELEASE) downto 0) := (others => '0');
+ signal DIN_info_CalcOut : std_logic_vector(( 31*USE_STAT_BITS + USE_DATA_WRITE + USE_DATA_FINISHED + USE_BUSY_RELEASE) downto 0) := (others => '0');
+ signal DIN_info_ready : std_logic_vector(( 31*USE_STAT_BITS + USE_DATA_WRITE + USE_DATA_FINISHED + USE_BUSY_RELEASE) downto 0) := (others => '0');
+
+ component RAM_pseudo_DP_wReg_36x1k is
+ port (
+ WrAddress : in std_logic_vector( 9 downto 0);
+ RdAddress : in std_logic_vector( 9 downto 0);
+ Data : in std_logic_vector(35 downto 0);
+ WE : in std_logic;
+ RdClock : in std_logic;
+ RdClockEn : in std_logic;
+ Reset : in std_logic;
+ WrClock : in std_logic;
+ WrClockEn : in std_logic;
+ Q : out std_logic_vector(35 downto 0)
+ );
+ end component RAM_pseudo_DP_wReg_36x1k;
+
begin
--BUS Handler
- proc_reg : process
- begin
- wait until rising_edge(CLK);
- BUS_TX.ack <= '0';
- BUS_TX.nack <= '0';
- BUS_TX.unknown <= '0';
- Flash_flag <= '0';
+ proc_reg : process
+ begin
+ wait until rising_edge(CLK);
+ BUS_TX.ack <= '0';
+ BUS_TX.nack <= '0';
+ BUS_TX.unknown <= '0';
+ Flash_flag <= '0';
+
+ Monitor_RAM_RE <= '0';
- if BUS_RX.write = '1' then
- BUS_TX.ack <= '1';
- if BUS_RX.addr(11 downto 0) > x"010" and BUS_RX.addr(11 downto 0) < x"0d0" then
- BUS_Flash_value <= std_logic_vector(unsigned(BUS_RX.addr(7 downto 0))-7) & BUS_RX.data(19 downto 10) & BUS_RX.data(9 downto 0);
- Flash_flag <= '1';
- elsif BUS_RX.addr(11 downto 0) >= x"000" and BUS_RX.addr(11 downto 0) < x"010" then --standard debugg
- case BUS_RX.addr(11 downto 0) is
- when x"000" =>
- BUS_do_Cal <= BUS_RX.data(0); -- change between w/ and w/o FPGA based Calibration
- when x"001" =>
- Cal_Limit_reg <= unsigned(BUS_RX.data(19 downto 0)); -- Set Maximum Value for Calibration Counter
- when x"002" =>
- Bus_FPGA <= BUS_RX.data(3 downto 0); -- set channel for Min/Max Output
- when x"003" =>
- Bus_Chnl <= BUS_RX.data(6 downto 0); -- set channel for Min/Max Output
- when others =>
- BUS_TX.ack <= '0';
- BUS_TX.unknown <= '1';
- end case;
- else --monitoring
- BUS_TX.ack <= '0';
- BUS_TX.unknown <= '1';
- end if;
- elsif BUS_RX.read = '1' then
- BUS_TX.ack <= '1';
- if BUS_RX.addr(11 downto 4) = x"00" then
- case BUS_RX.addr(3 downto 0) is
- when x"0" => BUS_TX.data(31 downto 1) <= (others => '0');
- BUS_TX.data( 0) <= BUS_do_Cal;
- when x"1" => BUS_TX.data(31 downto 20) <= (others => '0');
- BUS_TX.data(19 downto 0) <= std_logic_vector(cal_Limit_set);
- when x"2" => BUS_TX.data( 3 downto 0) <= Bus_FPGA;
- BUS_TX.data(31 downto 4) <= (others => '0');
- when x"3" => BUS_TX.data( 6 downto 0) <= Bus_Chnl;
- BUS_TX.data(31 downto 7) <= (others => '0');
- when x"4" => BUS_TX.data(31 downto 10) <= (others => '0');
- BUS_TX.data( 9 downto 0) <= Bus_min;
- when x"5" => BUS_TX.data(31 downto 10) <= (others => '0');
- BUS_TX.data( 9 downto 0) <= Bus_max;
- when x"6" => BUS_TX.data <= std_logic_vector(docal_debug_in);
- when x"7" => BUS_TX.data <= std_logic_vector(docal_debug_out);
- when x"8" => BUS_TX.data(11 downto 8) <= FPGA_Lim;
- BUS_TX.data(7) <= '0';
- BUS_TX.data( 6 downto 0) <= chnl_Lim;
- BUS_TX.data(31 downto 12) <= (others => '0');
- when x"9" => BUS_TX.data(31 downto 20) <= (others => '0');
- BUS_TX.data(19 downto 0) <= std_logic_vector(cal_cnt_in);
- when x"A" => BUS_TX.data <= Debug_Data_min;
- when x"B" => BUS_TX.data <= Debug_Data_max;
- when x"C" => BUS_TX.data(31 downto 20) <= (others => '0');
- BUS_TX.data(19 downto 0) <= MinMax_Monitor(0,16);
- when x"D" => BUS_TX.data(31 downto 20) <= (others => '0');
- BUS_TX.data(19 downto 0) <= MinMax_Monitor(0,17);
- when x"E" => BUS_TX.data(31 downto 20) <= (others => '0');
- BUS_TX.data(19 downto 0) <= MinMax_Monitor(0,18);
- when x"F" => BUS_TX.data(31 downto 20) <= (others => '0');
- BUS_TX.data(19 downto 0) <= MinMax_Monitor(0,19);
- when others => BUS_TX.ack <= '0';
- BUS_TX.unknown <= '1';
- end case;
- elsif BUS_RX.addr(11 downto 4) = x"02" then
- BUS_TX.data(31 downto 16) <= x"0000";
- BUS_TX.data(15 downto 0) <= FPGA_mntr_i(to_integer(unsigned(BUS_RX.addr(3 downto 0))));
- elsif BUS_RX.addr(11 downto 4) = x"03" then --ch 0
- BUS_TX.data(31 downto 20) <= (others => '0');
- BUS_TX.data(19 downto 0) <= MinMax_Monitor(to_integer(unsigned(BUS_RX.addr(3 downto 0))),0);
- elsif (BUS_RX.addr(11 downto 4) > x"03") and (BUS_RX.addr(11 downto 4) < x"20") then
- BUS_TX.data(31 downto 20) <= (others => '0');
- case BUS_RX.addr(4 downto 0) is
- when "00000" => BUS_TX.data(19 downto 0) <= MinMax_Monitor(to_integer(unsigned(BUS_RX.addr(11 downto 5)) - 2), 1);
- when "00001" => BUS_TX.data(19 downto 0) <= MinMax_Monitor(to_integer(unsigned(BUS_RX.addr(11 downto 5)) - 2), 2);
- when "00010" => BUS_TX.data(19 downto 0) <= MinMax_Monitor(to_integer(unsigned(BUS_RX.addr(11 downto 5)) - 2), 3);
- when "00011" => BUS_TX.data(19 downto 0) <= MinMax_Monitor(to_integer(unsigned(BUS_RX.addr(11 downto 5)) - 2), 4);
- when "00100" => BUS_TX.data(19 downto 0) <= MinMax_Monitor(to_integer(unsigned(BUS_RX.addr(11 downto 5)) - 2), 5);
- when "00101" => BUS_TX.data(19 downto 0) <= MinMax_Monitor(to_integer(unsigned(BUS_RX.addr(11 downto 5)) - 2), 6);
- when "00110" => BUS_TX.data(19 downto 0) <= MinMax_Monitor(to_integer(unsigned(BUS_RX.addr(11 downto 5)) - 2), 7);
- when "00111" => BUS_TX.data(19 downto 0) <= MinMax_Monitor(to_integer(unsigned(BUS_RX.addr(11 downto 5)) - 2), 8);
- when "01000" => BUS_TX.data(19 downto 0) <= MinMax_Monitor(to_integer(unsigned(BUS_RX.addr(11 downto 5)) - 2), 9);
- when "01001" => BUS_TX.data(19 downto 0) <= MinMax_Monitor(to_integer(unsigned(BUS_RX.addr(11 downto 5)) - 2),10);
- when "01010" => BUS_TX.data(19 downto 0) <= MinMax_Monitor(to_integer(unsigned(BUS_RX.addr(11 downto 5)) - 2),11);
- when "01011" => BUS_TX.data(19 downto 0) <= MinMax_Monitor(to_integer(unsigned(BUS_RX.addr(11 downto 5)) - 2),12);
- when "01100" => BUS_TX.data(19 downto 0) <= MinMax_Monitor(to_integer(unsigned(BUS_RX.addr(11 downto 5)) - 2),13);
- when "01101" => BUS_TX.data(19 downto 0) <= MinMax_Monitor(to_integer(unsigned(BUS_RX.addr(11 downto 5)) - 2),14);
- when "01110" => BUS_TX.data(19 downto 0) <= MinMax_Monitor(to_integer(unsigned(BUS_RX.addr(11 downto 5)) - 2),15);
- when "01111" => BUS_TX.data(19 downto 0) <= MinMax_Monitor(to_integer(unsigned(BUS_RX.addr(11 downto 5)) - 2),16);
- when "10000" => BUS_TX.data(19 downto 0) <= MinMax_Monitor(to_integer(unsigned(BUS_RX.addr(11 downto 5)) - 2),17);
- when "10001" => BUS_TX.data(19 downto 0) <= MinMax_Monitor(to_integer(unsigned(BUS_RX.addr(11 downto 5)) - 2),18);
- when "10010" => BUS_TX.data(19 downto 0) <= MinMax_Monitor(to_integer(unsigned(BUS_RX.addr(11 downto 5)) - 2),19);
- when "10011" => BUS_TX.data(19 downto 0) <= MinMax_Monitor(to_integer(unsigned(BUS_RX.addr(11 downto 5)) - 2),20);
- when "10100" => BUS_TX.data(19 downto 0) <= MinMax_Monitor(to_integer(unsigned(BUS_RX.addr(11 downto 5)) - 2),21);
- when "10101" => BUS_TX.data(19 downto 0) <= MinMax_Monitor(to_integer(unsigned(BUS_RX.addr(11 downto 5)) - 2),22);
- when "10110" => BUS_TX.data(19 downto 0) <= MinMax_Monitor(to_integer(unsigned(BUS_RX.addr(11 downto 5)) - 2),23);
- when "10111" => BUS_TX.data(19 downto 0) <= MinMax_Monitor(to_integer(unsigned(BUS_RX.addr(11 downto 5)) - 2),24);
- when "11000" => BUS_TX.data(19 downto 0) <= MinMax_Monitor(to_integer(unsigned(BUS_RX.addr(11 downto 5)) - 2),25);
- when "11001" => BUS_TX.data(19 downto 0) <= MinMax_Monitor(to_integer(unsigned(BUS_RX.addr(11 downto 5)) - 2),26);
- when "11010" => BUS_TX.data(19 downto 0) <= MinMax_Monitor(to_integer(unsigned(BUS_RX.addr(11 downto 5)) - 2),27);
- when "11011" => BUS_TX.data(19 downto 0) <= MinMax_Monitor(to_integer(unsigned(BUS_RX.addr(11 downto 5)) - 2),28);
- when "11100" => BUS_TX.data(19 downto 0) <= MinMax_Monitor(to_integer(unsigned(BUS_RX.addr(11 downto 5)) - 2),29);
- when "11101" => BUS_TX.data(19 downto 0) <= MinMax_Monitor(to_integer(unsigned(BUS_RX.addr(11 downto 5)) - 2),30);
- when "11110" => BUS_TX.data(19 downto 0) <= MinMax_Monitor(to_integer(unsigned(BUS_RX.addr(11 downto 5)) - 2),31);
- when "11111" => BUS_TX.data(19 downto 0) <= MinMax_Monitor(to_integer(unsigned(BUS_RX.addr(11 downto 5)) - 2),32);
+ if BUS_RX.write = '1' then
+ BUS_TX.ack <= '1';
+ if BUS_RX.addr(11 downto 0) > x"010" and BUS_RX.addr(11 downto 0) < x"0d0" then
+ BUS_Flash_value <= std_logic_vector(unsigned(BUS_RX.addr(7 downto 0))-7) & BUS_RX.data(19 downto 10) & BUS_RX.data(9 downto 0);
+ Flash_flag <= '1';
+ elsif BUS_RX.addr(11 downto 0) >= x"000" and BUS_RX.addr(11 downto 0) < x"010" then --standard debugg
+ case BUS_RX.addr(11 downto 0) is
+ when x"000" =>
+ BUS_Trig_type <= BUS_RX.data(11 downto 8);
+ BUS_do_Cal <= BUS_RX.data(0); -- change between w/ and w/o FPGA based Calibration
+ BUS_stop_LimitGen <= BUS_RX.data(4);
+ when x"001" =>
+ Cal_Limit_reg <= unsigned(BUS_RX.data(19 downto 0)); -- Set Maximum Value for Calibration Counter
+ when x"002" =>
+ Bus_FPGA <= BUS_RX.data(3 downto 0); -- set channel for Min/Max Output
+ when x"003" =>
+ Bus_Chnl <= BUS_RX.data(6 downto 0); -- set channel for Min/Max Output
+ when others =>
+ BUS_TX.ack <= '0';
+ BUS_TX.unknown <= '1';
end case;
- else
- BUS_TX.ack <= '0';
- BUS_TX.unknown <= '1';
- end if;
- end if;
- end process;
-
- THE_MONITOR_FPGA_ID : process
- begin
- wait until rising_edge(CLK);
- FPGA_mntr_i(to_integer(unsigned(FPGA_cnt_mntr))) <= FPGA_mntr;
- end process;
-
-
- read_cntr : entity work.read_cnt
- port map(
- CLK => CLK,
- RESET => RESET,
- chnl => chnl_read_cnt,
- FPGA_out => FPGA_o_cnt,
- FPGA_in => FPGA_in,
- DIN => DIN_i_Mem,
- DIN_ready => DIN_i_Mem_ready,
- DIN_type => DIN_i_Mem_type,
- DOUT => DIN_o_cnt,
- DOUT_ready => DIN_o_cnt_ready,
- DOUT_type => DIN_o_cnt_type,
- Do_Cal => Do_Cal_read_cnt,
- FPGA_cnt_mntr => FPGA_cnt_mntr,
- FPGA_mntr => FPGA_mntr
- );
+ else --monitoring
+ BUS_TX.ack <= '0';
+ BUS_TX.unknown <= '1';
+ end if;
+ elsif BUS_RX.read = '1' then
+ BUS_TX.ack <= '1';
+ if BUS_RX.addr(11 downto 4) = x"00" then
+ case BUS_RX.addr(3 downto 0) is
+ when x"0" => BUS_TX.data(31 downto 12) <= (others => '0');
+ BUS_TX.data(11 downto 8) <= BUS_Trig_type;
+ BUS_TX.data( 7 downto 5) <= (others => '0');
+ BUS_TX.data( 4) <= BUS_stop_LimitGen;
+ BUS_TX.data( 3 downto 1) <= (others => '0');
+ BUS_TX.data( 0) <= BUS_do_Cal;
+ when x"1" => BUS_TX.data(31 downto 20) <= (others => '0');
+ BUS_TX.data(19 downto 0) <= std_logic_vector(cal_Limit_set);
+ when x"2" => BUS_TX.data( 3 downto 0) <= Bus_FPGA;
+ BUS_TX.data(31 downto 4) <= (others => '0');
+ when x"3" => BUS_TX.data( 6 downto 0) <= Bus_Chnl;
+ BUS_TX.data(31 downto 7) <= (others => '0');
+ when x"4" => BUS_TX.data(31 downto 10) <= (others => '0');
+ BUS_TX.data( 9 downto 0) <= Bus_min;
+ when x"5" => BUS_TX.data(31 downto 10) <= (others => '0');
+ BUS_TX.data( 9 downto 0) <= Bus_max;
+ when x"6" => BUS_TX.data <= std_logic_vector(docal_debug_in);
+ when x"7" => BUS_TX.data <= std_logic_vector(docal_debug_out);
+ when x"8" => BUS_TX.data(11 downto 8) <= FPGA_Lim;
+ BUS_TX.data(7) <= '0';
+ BUS_TX.data( 6 downto 0) <= chnl_Lim;
+ BUS_TX.data(31 downto 12) <= (others => '0');
+ when x"9" => BUS_TX.data(31 downto 20) <= (others => '0');
+ BUS_TX.data(19 downto 0) <= std_logic_vector(cal_cnt_in);
+ when x"A" => BUS_TX.data <= Debug_Data_min;
+ when x"B" => BUS_TX.data <= Debug_Data_max;
+ when x"C" => BUS_TX.data(31 downto 20) <= (others => '0');
+ BUS_TX.data(19 downto 0) <= Max_Monitoring & Min_Monitoring;--MinMax_Monitor(0,16);
+ when x"D" => BUS_TX.data(31 downto 20) <= (others => '0');
+ BUS_TX.data(19 downto 0) <= MinMax_Monitor(0,17);
+ when x"E" => BUS_TX.data(31 downto 20) <= (others => '0');
+ BUS_TX.data(19 downto 0) <= MinMax_Monitor(0,18);
+ when x"F" => BUS_TX.data(31 downto 20) <= (others => '0');
+ BUS_TX.data(19 downto 0) <= MinMax_Monitor(0,19);
+ when others => BUS_TX.ack <= '0';
+ BUS_TX.unknown <= '1';
+ end case;
+ elsif BUS_RX.addr(11 downto 4) = x"02" then
+ BUS_TX.data(31 downto 16) <= x"0000";
+ BUS_TX.data(15 downto 0) <= FPGA_mntr_i(to_integer(unsigned(BUS_RX.addr(3 downto 0))));
+ elsif BUS_RX.addr(11 downto 4) = x"03" then --ch 0
+ BUS_TX.ack <= '0';
+ Monitor_RAM_AddChnl <= "0000000";
+ Monitor_RAM_AddFPGA <= std_logic_vector(unsigned(BUS_RX.addr(3 downto 0)));
+ Monitor_RAM_RE <= '1';
+ elsif (BUS_RX.addr(11 downto 4) > x"03") and (BUS_RX.addr(11 downto 4) < x"20") then
+ BUS_TX.ack <= '0';
+ Monitor_RAM_AddChnl <= std_logic_vector(unsigned("00" & BUS_RX.addr(4 downto 0))+1);
+ Monitor_RAM_AddFPGA <= std_logic_vector(unsigned(BUS_RX.addr(8 downto 5)) - 2);
+ Monitor_RAM_RE <= '1';
+ else
+ BUS_TX.ack <= '0';
+ BUS_TX.unknown <= '1';
+ end if;
+ elsif (Monitor_RAM_ready = '1') then
+ BUS_TX.data(31 downto 20) <= (others => '0');
+ BUS_TX.data(19 downto 0) <= Max_Monitoring & Min_Monitoring;
+ BUS_TX.ack <= '1';
+ end if;
+ end process;
+
+ THE_MONITOR_FPGA_ID : process
+ begin
+ wait until rising_edge(CLK);
+ FPGA_mntr_i(to_integer(unsigned(FPGA_cnt_mntr))) <= FPGA_mntr;
+ end process;
+
+
+ THE_MONITOR_RAM : RAM_pseudo_DP_wReg_36x1k
+ port map (
+ WrAddress(9 downto 6) => FPGA_out_curr,
+ WrAddress(5 downto 0) => chnl_out_curr(5 downto 0),
+ RdAddress(9 downto 6) => Monitor_RAM_AddFPGA,
+ RdAddress(5 downto 0) => Monitor_RAM_AddChnl(5 downto 0),
+ Data( 9 downto 0) => min_curr_Lim,
+ Data(15 downto 10) => (others => '0'),
+ Data(25 downto 16) => max_curr_Lim,
+ Data(35 downto 26) => (others => '0'),
+ WE => write_curr,
+ RdClock => CLK,
+ RdClockEn => '1',--Monitor_RAM_RE,
+ Reset => RESET,
+ WrClock => CLK,
+ WrClockEn => '1',
+ Q(35 downto 26) => MonitorRam_plcHldr2,
+ Q(25 downto 16) => Max_Monitoring,
+ Q(15 downto 10) => MonitorRam_plcHldr1,
+ Q( 9 downto 0) => Min_Monitoring
+ );
+
+ Monitor_RAM_ready_r <= Monitor_RAM_RE when rising_edge(CLK);
+ Monitor_RAM_ready <= Monitor_RAM_ready_r when rising_edge(CLK);
+
+
+
+-- read_no_COMBINER : if IS_COMBINER = c_NO generate
+--
+-- THE_TRIG_TYP : process begin
+-- wait until rising_edge(CLK);
+--
+-- if DIN(31 downto 29) = "001" then
+-- trig_type_in <= DIN(27 downto 24);
+-- end if;
+-- end process;
+--
+-- read_cntr : entity work.read_cnt
+-- port map(
+-- CLK => CLK,
+-- RESET => RESET,
+-- BUS_stp_Lmt => BUS_stop_LimitGen,
+-- BUS_Trig_type => BUS_Trig_type,
+-- chnl => chnl_read_cnt,
+-- FPGA_out => FPGA_o_cnt,
+-- FPGA_in => FPGA_in,
+-- Trigger_type => trig_type_in,
+-- DIN => DIN_i_Mem,
+-- DIN_ready => DIN_i_Mem_ready,
+-- DIN_type => x"4",
+-- DOUT => DIN_o_cnt,
+-- DOUT_ready => DIN_o_cnt_ready,
+-- DOUT_type => DIN_o_cnt_type,
+-- Do_Cal => Do_Cal_read_cnt,
+-- FPGA_cnt_mntr => FPGA_cnt_mntr,
+-- FPGA_mntr => FPGA_mntr,
+-- stop_Limit => stp_Lmt_read_cnt
+-- );
+-- end generate read_no_COMBINER;
+--
+-- read_COMBINER : if IS_COMBINER = c_YES generate
+
+ read_cntr : entity work.read_cnt
+ generic map (
+ USE_STAT_BITS => USE_STAT_BITS,
+ USE_DATA_WRITE => USE_DATA_WRITE,
+ USE_DATA_FINISHED => USE_DATA_FINISHED,
+ USE_BUSY_RELEASE => USE_BUSY_RELEASE
+ )
+ port map(
+ CLK => CLK,
+ RESET => RESET,
+ BUS_stp_Lmt => BUS_stop_LimitGen,
+ BUS_Trig_type => BUS_Trig_type,
+ chnl => chnl_read_cnt,
+ FPGA_out => FPGA_o_cnt,
+ FPGA_in => FPGA_in,
+ Trigger_type => TRIGG_TYPE,
+ DIN => DIN_i_Mem,
+ DIN_ready => DIN_i_Mem_ready,
+ DIN_type => DIN_i_Mem_type,
+ DOUT => DIN_o_cnt,
+ DOUT_ready => DIN_o_cnt_ready,
+ DOUT_type => DIN_o_cnt_type,
+ Do_Cal => Do_Cal_read_cnt,
+ FPGA_cnt_mntr => FPGA_cnt_mntr,
+ FPGA_mntr => FPGA_mntr,
+ stop_Limit => stp_Lmt_read_cnt,
+ DIN_info => DIN_info_ready,
+ DOUT_info => DIN_info_rc
+ );
+-- end generate read_COMBINER;
- ent_cnt_val : entity work.cnt_val
- port map(
- CLK => CLK,
- RESET => RESET,
- write => write_chnl_cnt,
- FPGA_read => FPGA_o_cnt,
- chnl_read => chnl_read_cnt,
- FPGA_write => FPGA_out_write_cnt,
- chnl_write => chnl_out_write_cnt,
- cal_cnt => cal_cnt_in,
- cal_cnt_out => cal_cnt_out,
- DIN => DIN_o_cnt,
- DIN_ready => DIN_o_cnt_ready,
- DIN_type => DIN_o_cnt_type--,
- --DOUT => DIN_o_cnt_val,
- --DOUT_ready => DIN_o_cnt_val_ready,
- --DOUT_type => DIN_o_cnt_val_type--,
--- FPGA_out => open,
--- CHNL_out => open
- );
+ ent_cnt_val : entity work.cnt_val
+ port map(
+ CLK => CLK,
+ RESET => RESET,
+ write => write_chnl_cnt,
+ FPGA_read => FPGA_o_cnt,
+ chnl_read => chnl_read_cnt,
+ FPGA_write => FPGA_out_write_cnt,
+ chnl_write => chnl_out_write_cnt,
+ cal_cnt => cal_cnt_in,
+ cal_cnt_out => cal_cnt_out,
+ DIN => DIN_o_cnt,
+ DIN_ready => DIN_o_cnt_ready,
+ DIN_type => DIN_o_cnt_type
+ );
+
+ Mem_next : entity work.Memory
+ port map(
+ CLK => CLK,
+ RESET => RESET,
+ write => write_next,
+ FPGA_read => FPGA_o_cnt,
+ chnl_read => chnl_read_cnt,
+ FPGA_write => FPGA_out_write,
+ chnl_write => chnl_out_write,
+ min => min_next_Lim,
+ max => max_next_Lim,
+ min_out => min_next,
+ max_out => max_next,
+ DIN => DIN_o_cnt,
+ DIN_ready => DIN_o_cnt_ready,
+ DIN_type => DIN_o_cnt_type
+ );
- Mem_next : entity work.Memory
- port map(
- CLK => CLK,
- RESET => RESET,
- write => write_next,
- FPGA_read => FPGA_o_cnt,
- chnl_read => chnl_read_cnt,
- FPGA_write => FPGA_out_write,
- chnl_write => chnl_out_write,
- min => min_next_Lim,
- max => max_next_Lim,
- min_out => min_next,
- max_out => max_next,
- DIN => DIN_o_cnt,
- DIN_ready => DIN_o_cnt_ready,
- DIN_type => DIN_o_cnt_type
- );
+ Mem_curr : entity work.Memory_curr
+ generic map (
+ USE_STAT_BITS => USE_STAT_BITS,
+ USE_DATA_WRITE => USE_DATA_WRITE,
+ USE_DATA_FINISHED => USE_DATA_FINISHED,
+ USE_BUSY_RELEASE => USE_BUSY_RELEASE
+ )
+ port map(
+ CLK => CLK,
+ RESET => RESET,
+ stp_Lmt_in => stp_Lmt_read_cnt,
+ write => write_curr,
+ FPGA_read => FPGA_o_cnt,
+ chnl_read => chnl_read_cnt,
+ FPGA_write => FPGA_out_curr,
+ chnl_write => chnl_out_curr,
+ min => min_curr_Lim,
+ max => max_curr_Lim,
+ min_out => min_curr,
+ max_out => max_curr,
+ Do_Cal_in => Do_Cal_read_cnt,
+ DIN => DIN_o_cnt,
+ DIN_ready => DIN_o_cnt_ready,
+ DIN_type => DIN_o_cnt_type,
+ DOUT => DIN_MemCurr_data,
+ DOUT_ready => DIN_MemCurr_ready,
+ DOUT_type => DIN_MemCurr_type,
+ FPGA_out => FPGA_out_Memory,
+ CHNL_out => CHNL_out_Memory,
+ Do_Cal_out => Do_Cal_Memory,
+ stp_Lmt_out => stp_Lmt_MemCurr,
+ DIN_info => DIN_info_rc,
+ DOUT_info => DIN_info_mem
+ );
+
+
+ Cal_Limits : entity work.Cal_Limits_v2
+ generic map(
+ cal_Limit_gen => "00000010011100010000", -- 10k
+ USE_STAT_BITS => USE_STAT_BITS,
+ USE_DATA_WRITE => USE_DATA_WRITE,
+ USE_DATA_FINISHED => USE_DATA_FINISHED,
+ USE_BUSY_RELEASE => USE_BUSY_RELEASE
+ )
+ port map(
+ CLK => CLK,
+ RESET => RESET,
+ stop_Limits => stp_Lmt_MemCurr,
+ cal_Limit_reg => Cal_Limit_reg,
+ DIN => DIN_MemCurr_data,
+ DIN_ready => DIN_MemCurr_ready,
+ DIN_type => DIN_MemCurr_type,
+ min_curr_in => min_curr,
+ max_curr_in => max_curr,
+ min_next_in => min_next,
+ max_next_in => max_next,
+ FPGA => FPGA_out_Memory,
+ chnl => CHNL_out_Memory,
+ Do_Cal_in => Do_Cal_Memory,
+ chnl_cnt_in => cal_cnt_out,
+ BUS_Flash_value => BUS_Flash_value,
+ Flash_flag => Flash_flag,
+ write_curr => write_curr,
+ write_next => write_next,
+ min_next => min_next_Lim,
+ max_next => max_next_Lim,
+ min_curr => min_curr_Lim,
+ max_curr => max_curr_Lim,
+ min_out => min_out_Lim,
+ max_out => max_out_Lim,
+ Delta => Delta_Lim,
+ FPGA_out => FPGA_Lim,
+ chnl_out => chnl_Lim,
+ FPGA_out_curr => FPGA_out_curr,
+ chnl_out_curr => chnl_out_curr,
+ FPGA_out_write => FPGA_out_write,
+ chnl_out_write => chnl_out_write,
+ FPGA_out_write_cnt => FPGA_out_write_cnt,
+ chnl_out_write_cnt => chnl_out_write_cnt,
+ DOUT => DIN_o_Lim,
+ DOUT_ready => DIN_o_Lim_ready,
+ DOUT_type => DIN_o_Lim_type,
+ Do_Cal_out => do_cal_LIM,
+ chnl_cnt_out => cal_cnt_in,
+ write_chnl_cnt => write_chnl_cnt,
+ cal_Limit_set => cal_Limit_set,
+ Debug_Data_min => Debug_Data_min,
+ Debug_Data_max => Debug_Data_max,
+ DIN_info => DIN_info_mem,
+ DOUT_info => DIN_info_Lim
+ );
- Mem_curr : entity work.Memory_curr
- port map(
- CLK => CLK,
- RESET => RESET,
- write => write_curr,
- FPGA_read => FPGA_o_cnt,
- chnl_read => chnl_read_cnt,
- FPGA_write => FPGA_out_curr,
- chnl_write => chnl_out_curr,
- min => min_curr_Lim,
- max => max_curr_Lim,
- min_out => min_curr,
- max_out => max_curr,
- Do_Cal_in => Do_Cal_read_cnt,
- DIN => DIN_o_cnt,
- DIN_ready => DIN_o_cnt_ready,
- DIN_type => DIN_o_cnt_type,
- DOUT => DIN_MemCurr_data,
- DOUT_ready => DIN_MemCurr_ready,
- DOUT_type => DIN_MemCurr_type,
- FPGA_out => FPGA_out_Memory,
- CHNL_out => CHNL_out_Memory,
- Do_Cal_out => Do_Cal_Memory
- );
-
-
- Cal_Limits : entity work.Cal_Limits_v2
- generic map(
- cal_Limit_gen => "00000010011100010000" -- 10k
- )
- port map(
- CLK => CLK,
- cal_Limit_reg => Cal_Limit_reg,
- DIN => DIN_MemCurr_data,
- DIN_ready => DIN_MemCurr_ready,
- DIN_type => DIN_MemCurr_type,
- min_curr_in => min_curr,
- max_curr_in => max_curr,
- min_next_in => min_next,
- max_next_in => max_next,
- FPGA => FPGA_out_Memory,
- chnl => CHNL_out_Memory,
- Do_Cal_in => Do_Cal_Memory,
- chnl_cnt_in => cal_cnt_out,
- BUS_Flash_value => BUS_Flash_value,
- Flash_flag => Flash_flag,
- write_curr => write_curr,
- write_next => write_next,
- min_next => min_next_Lim,
- max_next => max_next_Lim,
- min_curr => min_curr_Lim,
- max_curr => max_curr_Lim,
- min_out => min_out_Lim,
- max_out => max_out_Lim,
- Delta => Delta_Lim,
- FPGA_out => FPGA_Lim,
- chnl_out => chnl_Lim,
- FPGA_out_curr => FPGA_out_curr,
- chnl_out_curr => chnl_out_curr,
- FPGA_out_write => FPGA_out_write,
- chnl_out_write => chnl_out_write,
- FPGA_out_write_cnt => FPGA_out_write_cnt,
- chnl_out_write_cnt => chnl_out_write_cnt,
- DOUT => DIN_o_Lim,
- DOUT_ready => DIN_o_Lim_ready,
- DOUT_type => DIN_o_Lim_type,
- Do_Cal_out => do_cal_LIM,
- chnl_cnt_out => cal_cnt_in,
- write_chnl_cnt => write_chnl_cnt,
- cal_Limit_set => cal_Limit_set,
- Debug_Data_min => Debug_Data_min,
- Debug_Data_max => Debug_Data_max
- );
+ LUTs : entity work.LUT
+ generic map (
+ USE_STAT_BITS => USE_STAT_BITS,
+ USE_DATA_WRITE => USE_DATA_WRITE,
+ USE_DATA_FINISHED => USE_DATA_FINISHED,
+ USE_BUSY_RELEASE => USE_BUSY_RELEASE
+ )
+ port map(
+ CLK => CLK,
+ DIN => DIN_o_Lim,
+ DIN_ready => DIN_o_Lim_ready,
+ DIN_type => DIN_o_Lim_type,
+ Delta => Delta_Lim,
+ min_in => min_out_Lim,
+ max_in => max_out_Lim,
+ do_cal_in => do_cal_LIM,
+ min_out => min_out_LUT,
+ max_out => max_out_LUT,
+ DOUT => DIN_o_LUT,
+ DOUT_ready => DIN_o_LUT_ready,
+ DOUT_type => DIN_o_LUT_type,
+ slope => slope_LUT,
+ do_cal_out => cal_flag_LUT_out,
+ factor => factor_LUT,
+ overshoot => overshoot_LUT,
+ undershoot => undershoot_LUT,
+ DIN_info => DIN_info_Lim,
+ DOUT_info => DIN_info_LUT
+ );
+
+ DELAY_SLOPE: process begin
+ wait until rising_edge(CLK);
- LUTs : entity work.LUT
- port map(
- CLK => CLK,
- DIN => DIN_o_Lim,
- DIN_ready => DIN_o_Lim_ready,
- DIN_type => DIN_o_Lim_type,
- Delta => Delta_Lim,
- min_in => min_out_Lim,
- max_in => max_out_Lim,
- do_cal_in => do_cal_LIM,
- min_out => min_out_LUT,
- max_out => max_out_LUT,
- DOUT => DIN_o_LUT,
- DOUT_ready => DIN_o_LUT_ready,
- DOUT_type => DIN_o_LUT_type,
- slope => slope_LUT,
- do_cal_out => cal_flag_LUT_out,
- factor => factor,
- overshoot => overshoot_LUT,
- undershoot => undershoot_LUT
- );
+ DIN_delay <= DIN_o_LUT;
+ DIN_ready_delay <= DIN_o_LUT_ready;
+ DIN_type_delay <= DIN_o_LUT_type;
+ slope_delay <= slope_LUT;
+ do_cal_delay <= cal_flag_LUT_out;
+ factor_delay <= factor_LUT;
+ overshoot_delay <= overshoot_LUT;
+ undershoot_delay <= undershoot_LUT;
+ DIN_info_delay <= DIN_info_LUT;
+ end process;
- Calc_Output : entity work.calc_output
- port map(
- CLK => CLK,
- DIN => DIN_o_LUT,
- DIN_ready => DIN_o_LUT_ready,
- DIN_type => DIN_o_LUT_type,
- do_cal_in => cal_flag_LUT_out,
- overshoot_in => overshoot_LUT,
- undershoot_in => undershoot_LUT,
- slope => slope_LUT,
- factor => factor,
- DOUT => DIN_o_CalcOut,
- DOUT_ready => DIN_o_CalcOut_ready,
- DOUT_type => DIN_o_CalcOut_type,
- do_cal_out => Do_cal_CalcOut,
- overshoot_out => overshoot_CalcOut,
- undershoot_out => undershoot_CalcOut,
- Cal_Data_out => Dout_int
- );
+ Calc_Output : entity work.calc_output
+ generic map (
+ USE_STAT_BITS => USE_STAT_BITS,
+ USE_DATA_WRITE => USE_DATA_WRITE,
+ USE_DATA_FINISHED => USE_DATA_FINISHED,
+ USE_BUSY_RELEASE => USE_BUSY_RELEASE
+ )
+ port map(
+ CLK => CLK,
+ DIN => DIN_delay,
+ DIN_ready => DIN_ready_delay,
+ DIN_type => DIN_type_delay,
+ do_cal_in => do_cal_delay,
+ overshoot_in => overshoot_delay,
+ undershoot_in => undershoot_delay,
+ slope => slope_delay,
+ factor => factor_delay,
+ DOUT => DIN_o_CalcOut,
+ DOUT_ready => DIN_o_CalcOut_ready,
+ DOUT_type => DIN_o_CalcOut_type,
+ do_cal_out => Do_cal_CalcOut,
+ overshoot_out => overshoot_CalcOut,
+ undershoot_out => undershoot_CalcOut,
+ Cal_Data_out => Dout_int,
+ DIN_info => DIN_info_delay,
+ DOUT_info => DIN_info_CalcOut
+ );
THE_Enable : process
- begin
- wait until rising_edge(CLK);
- if DIN_READY = '1' then
- DIN_i_Mem <= DIN;
- DIN_i_Mem_type <= DIN_TYPE;
- end if;
- DIN_i_Mem_ready <= DIN_READY;
- end process;
-
+ begin
+ wait until rising_edge(CLK);
+ if DIN_READY = '1' then
+ DIN_i_Mem <= DIN;
+ DIN_i_Mem_type <= DIN_TYPE;
+ DIN_info_ready <= DIN_info;
+ end if;
+ DIN_i_Mem_ready <= DIN_READY;
+
+ end process;
- fine_out : process (CLK)
- begin
- if rising_edge(CLK) then
+
+ fine_out : process (CLK)
+ begin
+ if rising_edge(CLK) then
- if ((Do_cal_CalcOut = '1') and (BUS_do_Cal = '1')) then
- DOUT(31 downto 22) <= DIN_o_CalcOut(31 downto 22);
- DOUT(11 downto 0) <= DIN_o_CalcOut(11 downto 0);
- if ((overshoot_CalcOut = '0') and (undershoot_CalcOut = '0')) then
- DOUT(21 downto 12) <= Dout_int(19 downto 10);
- elsif (undershoot_CalcOut = '1') and (overshoot_CalcOut = '0') then
- DOUT(21 downto 12) <= "1111110010"; --1010
- elsif (undershoot_CalcOut = '0') and (overshoot_CalcOut = '1') then
- DOUT(21 downto 12) <= "1111110111"; --1015
- else
- DOUT(21 downto 12) <= "1111111100"; --1020
- end if;
- else
- DOUT <= DIN_o_CalcOut;
- end if;
+ if ((Do_cal_CalcOut = '1') and (BUS_do_Cal = '1')) then
+ DOUT(31 downto 22) <= DIN_o_CalcOut(31 downto 22);
+ DOUT(11 downto 0) <= DIN_o_CalcOut(11 downto 0);
+ if ((overshoot_CalcOut = '0') and (undershoot_CalcOut = '0')) then
+ DOUT(21 downto 12) <= Dout_int(19 downto 10);
+ elsif (undershoot_CalcOut = '1') and (overshoot_CalcOut = '0') then
+ DOUT(21 downto 12) <= "1111110010"; --1010
+ elsif (undershoot_CalcOut = '0') and (overshoot_CalcOut = '1') then
+ DOUT(21 downto 12) <= "1111110111"; --1015
+ else
+ DOUT(21 downto 12) <= "1111111100"; --1020
+ end if;
+ else
+ DOUT <= DIN_o_CalcOut;
+ end if;
- DOUT_READY <= DIN_o_CalcOut_ready;
- DOUT_TYPE <= DIN_o_CalcOut_type;
- end if;
- end process;
+ DOUT_READY <= DIN_o_CalcOut_ready;
+ DOUT_TYPE <= DIN_o_CalcOut_type;
+ DOUT_info <= DIN_info_CalcOut;
+ end if;
+ end process;
+
+
+ debug : process (CLK)
+ begin
+ if rising_edge(CLK) then
+ if (unsigned(Bus_Chnl) = unsigned(chnl_Lim)) and (unsigned(Bus_FPGA) = unsigned(FPGA_Lim)) then
+ Bus_min <= min_out_Lim;
+ Bus_max <= max_out_Lim;
+ end if;
+
+ if do_cal_LIM = '1' then
+ docal_debug_out <= docal_debug_out + 1;
+ end if;
+ if Do_Cal_Memory = '1' then
+ docal_debug_in <= docal_debug_in + 1;
+ end if;
+ end if;
+ end process;
+
+ Calib_monitor : process (CLK)
+ begin
+ if rising_edge(CLK) then
+ if do_cal_LIM = '1' then
+ MinMax_Monitor(to_integer(unsigned(FPGA_Lim)),to_integer(unsigned(chnl_Lim(5 downto 0))))( 9 downto 0) <= min_out_Lim;
+ MinMax_Monitor(to_integer(unsigned(FPGA_Lim)),to_integer(unsigned(chnl_Lim(5 downto 0))))(19 downto 10) <= max_out_Lim;
+ end if;
+ end if;
+ end process;
- debug : process (CLK)
- begin
- if rising_edge(CLK) then
- if (unsigned(Bus_Chnl) = unsigned(chnl_Lim)) and (unsigned(Bus_FPGA) = unsigned(FPGA_Lim)) then
- Bus_min <= min_out_Lim;
- Bus_max <= max_out_Lim;
- end if;
-
- if do_cal_LIM = '1' then
- docal_debug_out <= docal_debug_out + 1;
- end if;
- if Do_Cal_Memory = '1' then
- docal_debug_in <= docal_debug_in + 1;
- end if;
- end if;
- end process;
-
- Calib_monitor : process (CLK)
- begin
- if rising_edge(CLK) then
- if do_cal_LIM = '1' then
- MinMax_Monitor(to_integer(unsigned(FPGA_Lim)),to_integer(unsigned(chnl_Lim(5 downto 0))))( 9 downto 0) <= min_out_Lim;
- MinMax_Monitor(to_integer(unsigned(FPGA_Lim)),to_integer(unsigned(chnl_Lim(5 downto 0))))(19 downto 10) <= max_out_Lim;
- end if;
- end if;
- end process;
-
-
- TX_statusbits : process (CLK)
- begin
- if rising_edge(CLK) then
- if (DIN_READY = '1') then
- DOUT_STAT <= DIN_STAT; --ToDO: better handling
- end if;
- end if;
- end process;
+ TX_stat : if IS_COMBINER = c_YES generate
+ TX_statusbits : process (CLK)
+ begin
+ if rising_edge(CLK) then
+ if (DIN_READY = '1') then
+ DOUT_STAT <= DIN_STAT;
+ end if;
+ end if;
+ end process;
+ end generate TX_stat;
end Behavioral;
use work.trb_net_std.all;
entity LUT is
- port (
- CLK : in std_logic;
- DIN : in std_logic_vector(31 downto 0);
- DIN_ready : in std_logic;
- DIN_type : in std_logic_vector( 3 downto 0);
- Delta : in std_logic_vector( 9 downto 0):="0110110100";
- min_in : in std_logic_vector( 9 downto 0);
- max_in : in std_logic_vector( 9 downto 0);
- do_cal_in : in std_logic;
- min_out : out std_logic_vector( 9 downto 0);
- max_out : out std_logic_vector( 9 downto 0);
- DOUT : out std_logic_vector(31 downto 0);
- DOUT_ready : out std_logic;
- DOUT_type : out std_logic_vector( 3 downto 0);
- slope : out std_logic_vector(11 downto 0);
- do_cal_out : out std_logic;
- factor : out std_logic_vector( 9 downto 0);
- overshoot : out std_logic := '0';
- undershoot : out std_logic := '0'
- );
+ generic (
+ USE_STAT_BITS : integer range 0 to 1 := c_NO;
+ USE_DATA_WRITE : integer range 0 to 1 := c_NO;
+ USE_DATA_FINISHED : integer range 0 to 1 := c_NO;
+ USE_BUSY_RELEASE : integer range 0 to 1 := c_NO );
+ port (
+ CLK : in std_logic;
+ DIN : in std_logic_vector(31 downto 0);
+ DIN_ready : in std_logic;
+ DIN_type : in std_logic_vector( 3 downto 0);
+ Delta : in std_logic_vector( 9 downto 0):="0110110100";
+ min_in : in std_logic_vector( 9 downto 0);
+ max_in : in std_logic_vector( 9 downto 0);
+ do_cal_in : in std_logic;
+ DIN_info : in std_logic_vector(( 31*USE_STAT_BITS + USE_DATA_WRITE + USE_DATA_FINISHED + USE_BUSY_RELEASE) downto 0);
+ min_out : out std_logic_vector( 9 downto 0);
+ max_out : out std_logic_vector( 9 downto 0);
+ DOUT : out std_logic_vector(31 downto 0);
+ DOUT_ready : out std_logic;
+ DOUT_type : out std_logic_vector( 3 downto 0);
+ slope : out std_logic_vector(11 downto 0);
+ do_cal_out : out std_logic;
+ factor : out std_logic_vector( 9 downto 0);
+ overshoot : out std_logic := '0';
+ undershoot : out std_logic := '0';
+ DOUT_info : out std_logic_vector(( 31*USE_STAT_BITS + USE_DATA_WRITE + USE_DATA_FINISHED + USE_BUSY_RELEASE) downto 0)
+ );
end entity;
architecture lut of LUT is
- subtype lutin is std_logic_vector (11 downto 0);
- subtype lutout is std_logic_vector (11 downto 0);
- type lut is array (natural range 436 to 563) of lutout;
+ subtype lutin is std_logic_vector (11 downto 0);
+ subtype lutout is std_logic_vector (11 downto 0);
+ type lut is array (natural range 436 to 563) of lutout;
- constant LUTslope: lut := (
- "100100101101", "100100100111", "100100100010", "100100011101",
- "100100010111", "100100010010", "100100001101", "100100001000",
- "100100000010", "100011111101", "100011111000", "100011110011",
- "100011101110", "100011101001", "100011100100", "100011011111",
- "100011011001", "100011010100", "100011010000", "100011001011",
- "100011000110", "100011000001", "100010111100", "100010110111",
- "100010110010", "100010101101", "100010101000", "100010100100",
- "100010011111", "100010011010", "100010010101", "100010010001",
- "100010001100", "100010000111", "100010000011", "100001111110",
- "100001111001", "100001110101", "100001110000", "100001101100",
- "100001100111", "100001100011", "100001011110", "100001011010",
- "100001010101", "100001010001", "100001001100", "100001001000",
- "100001000100", "100000111111", "100000111011", "100000110111",
- "100000110010", "100000101110", "100000101010", "100000100110",
- "100000100001", "100000011101", "100000011001", "100000010101",
- "100000010001", "100000001100", "100000001000", "100000000100",
- "100000000000", "011111111100", "011111111000", "011111110100",
- "011111110000", "011111101100", "011111101000", "011111100100",
- "011111100000", "011111011100", "011111011000", "011111010100",
- "011111010000", "011111001100", "011111001000", "011111000100",
- "011111000000", "011110111101", "011110111001", "011110110101",
- "011110110001", "011110101101", "011110101010", "011110100110",
- "011110100010", "011110011110", "011110011011", "011110010111",
- "011110010011", "011110010000", "011110001100", "011110001000",
- "011110000101", "011110000001", "011101111110", "011101111010",
- "011101110110", "011101110011", "011101101111", "011101101100",
- "011101101000", "011101100101", "011101100001", "011101011110",
- "011101011010", "011101010111", "011101010011", "011101010000",
- "011101001101", "011101001001", "011101000110", "011101000010",
- "011100111111", "011100111100", "011100111000", "011100110101",
- "011100110010", "011100101110", "011100101011", "011100101000",
- "011100100101", "011100100001", "011100011110", "011100011011"
- );
+ constant LUTslope: lut := (
+ "100100101101", "100100100111", "100100100010", "100100011101",
+ "100100010111", "100100010010", "100100001101", "100100001000",
+ "100100000010", "100011111101", "100011111000", "100011110011",
+ "100011101110", "100011101001", "100011100100", "100011011111",
+ "100011011001", "100011010100", "100011010000", "100011001011",
+ "100011000110", "100011000001", "100010111100", "100010110111",
+ "100010110010", "100010101101", "100010101000", "100010100100",
+ "100010011111", "100010011010", "100010010101", "100010010001",
+ "100010001100", "100010000111", "100010000011", "100001111110",
+ "100001111001", "100001110101", "100001110000", "100001101100",
+ "100001100111", "100001100011", "100001011110", "100001011010",
+ "100001010101", "100001010001", "100001001100", "100001001000",
+ "100001000100", "100000111111", "100000111011", "100000110111",
+ "100000110010", "100000101110", "100000101010", "100000100110",
+ "100000100001", "100000011101", "100000011001", "100000010101",
+ "100000010001", "100000001100", "100000001000", "100000000100",
+ "100000000000", "011111111100", "011111111000", "011111110100",
+ "011111110000", "011111101100", "011111101000", "011111100100",
+ "011111100000", "011111011100", "011111011000", "011111010100",
+ "011111010000", "011111001100", "011111001000", "011111000100",
+ "011111000000", "011110111101", "011110111001", "011110110101",
+ "011110110001", "011110101101", "011110101010", "011110100110",
+ "011110100010", "011110011110", "011110011011", "011110010111",
+ "011110010011", "011110010000", "011110001100", "011110001000",
+ "011110000101", "011110000001", "011101111110", "011101111010",
+ "011101110110", "011101110011", "011101101111", "011101101100",
+ "011101101000", "011101100101", "011101100001", "011101011110",
+ "011101011010", "011101010111", "011101010011", "011101010000",
+ "011101001101", "011101001001", "011101000110", "011101000010",
+ "011100111111", "011100111100", "011100111000", "011100110101",
+ "011100110010", "011100101110", "011100101011", "011100101000",
+ "011100100101", "011100100001", "011100011110", "011100011011"
+ );
- signal do_cal_out_i : std_logic := '0';
+ signal do_cal_out_i : std_logic := '0';
begin
-
- proc_slope : process (CLK)
- begin
- if rising_edge(CLK) then
- if do_cal_in = '1' then
- slope <= LUTslope( TO_INTEGER ( unsigned(Delta)));
- end if;
- min_out <= min_in;
- max_out <= max_in;
- do_cal_out_i <= do_cal_in;
- end if;
- end process;
+ proc_slope : process (CLK)
+ begin
+ if rising_edge(CLK) then
+ if do_cal_in = '1' then
+ slope <= LUTslope( TO_INTEGER ( unsigned(Delta)));
+ end if;
+ min_out <= min_in;
+ max_out <= max_in;
+ do_cal_out_i <= do_cal_in;
+ end if;
+ end process;
- proc_factor : process (CLK)
- begin
- if rising_edge(CLK) then
- --keep values in definition area of linear part
- if (unsigned(DIN(21 downto 12)) < unsigned(min_in) ) then
- factor <= (others => '0');
- undershoot <= '1'; -- value is out of calibration range
- overshoot <= '0';
- elsif (unsigned(DIN(21 downto 12)) > unsigned(max_in) ) then
- factor <= (others => '0');
- overshoot <= '1'; -- value is out of calibration range
- undershoot <= '0';
- else
- factor <= std_logic_vector(unsigned(DIN(21 downto 12)) - unsigned(min_in));
- undershoot <= '0';
- overshoot <= '0';
- end if;
+ proc_factor : process (CLK)
+ begin
+ if rising_edge(CLK) then
+ --keep values in definition area of linear part
+ if (unsigned(DIN(21 downto 12)) < unsigned(min_in) ) then
+ factor <= (others => '0');
+ undershoot <= '1'; -- value is out of calibration range
+ overshoot <= '0';
+ elsif (unsigned(DIN(21 downto 12)) > unsigned(max_in) ) then
+ factor <= (others => '0');
+ overshoot <= '1'; -- value is out of calibration range
+ undershoot <= '0';
+ else
+ factor <= std_logic_vector(unsigned(DIN(21 downto 12)) - unsigned(min_in));
+ undershoot <= '0';
+ overshoot <= '0';
+ end if;
- DOUT <= DIN;
- DOUT_ready <= DIN_ready;
- DOUT_type <= DIN_type;
- end if;
- end process;
+ DOUT <= DIN;
+ DOUT_ready <= DIN_ready;
+ DOUT_type <= DIN_type;
+ DOUT_info <= DIN_info;
+ end if;
+ end process;
- do_cal_out <= do_cal_out_i;
+ do_cal_out <= do_cal_out_i;
end architecture;
\ No newline at end of file
use IEEE.NUMERIC_STD.ALL;
entity Memory is
- Port (
- CLK : in std_logic;
- RESET : in std_logic;
- write : in std_logic;
- FPGA_read : in std_logic_vector( 3 downto 0);
- chnl_read : in std_logic_vector( 6 downto 0);
- FPGA_write : in std_logic_vector( 3 downto 0);
- chnl_write : in std_logic_vector( 6 downto 0);
- Min : in std_logic_vector( 9 downto 0);
- Max : in std_logic_vector( 9 downto 0);
- DIN : in std_logic_vector(31 downto 0);
- DIN_ready : in std_logic;
- DIN_type : in std_logic_vector( 3 downto 0);
- Min_out : out std_logic_vector( 9 downto 0):= "1111111111";
- Max_out : out std_logic_vector( 9 downto 0):= "0000000000"
- );
+ Port (
+ CLK : in std_logic;
+ RESET : in std_logic;
+ write : in std_logic;
+ FPGA_read : in std_logic_vector( 3 downto 0);
+ chnl_read : in std_logic_vector( 6 downto 0);
+ FPGA_write : in std_logic_vector( 3 downto 0);
+ chnl_write : in std_logic_vector( 6 downto 0);
+ Min : in std_logic_vector( 9 downto 0);
+ Max : in std_logic_vector( 9 downto 0);
+ DIN : in std_logic_vector(31 downto 0);
+ DIN_ready : in std_logic;
+ DIN_type : in std_logic_vector( 3 downto 0);
+ Min_out : out std_logic_vector( 9 downto 0):= "1111111111";
+ Max_out : out std_logic_vector( 9 downto 0):= "0000000000"
+ );
end Memory;
architecture Behavioral of Memory is
- signal Max_EBR_out : std_logic_vector(9 downto 0) := "0000000000";
- signal Min_EBR_out : std_logic_vector(9 downto 0) := "1111111111";
- signal Q_col, Q_col_r : std_logic_vector(20 downto 0) :='0' & x"003FF";
- signal Q_i1 : std_logic_vector(5 downto 0);
- signal Q_i2 : std_logic_vector(9 downto 0);
+ signal Max_EBR_out : std_logic_vector( 9 downto 0) := "0000000000";
+ signal Min_EBR_out : std_logic_vector( 9 downto 0) := "1111111111";
+ signal Q_col, Q_col_r : std_logic_vector(20 downto 0) :='0' & x"003FF";
+ signal Q_i1 : std_logic_vector( 5 downto 0);
+ signal Q_i2 : std_logic_vector( 9 downto 0);
- component RAM_pseudo_DP_wReg_36x1k is
- port (
- WrAddress : in std_logic_vector(9 downto 0);
- RdAddress : in std_logic_vector(9 downto 0);
- Data : in std_logic_vector(35 downto 0);
- WE : in std_logic;
- RdClock : in std_logic;
- RdClockEn : in std_logic;
- Reset : in std_logic;
- WrClock : in std_logic;
- WrClockEn : in std_logic;
- Q : out std_logic_vector(35 downto 0)
- );
- end component RAM_pseudo_DP_wReg_36x1k;
+ component RAM_pseudo_DP_wReg_36x1k is
+ port (
+ WrAddress : in std_logic_vector( 9 downto 0);
+ RdAddress : in std_logic_vector( 9 downto 0);
+ Data : in std_logic_vector(35 downto 0);
+ WE : in std_logic;
+ RdClock : in std_logic;
+ RdClockEn : in std_logic;
+ Reset : in std_logic;
+ WrClock : in std_logic;
+ WrClockEn : in std_logic;
+ Q : out std_logic_vector(35 downto 0)
+ );
+ end component RAM_pseudo_DP_wReg_36x1k;
begin
THE_EBR_curr : RAM_pseudo_DP_wReg_36x1k
port map (
- WrAddress(9 downto 6) => FPGA_write,
- WrAddress(5 downto 0) => chnl_write(5 downto 0),
- RdAddress(9 downto 6) => FPGA_read,
- RdAddress(5 downto 0) => chnl_read(5 downto 0),
- Data( 9 downto 0) => Min,
- Data(15 downto 10) => (others => '0'),
- Data(25 downto 16) => Max,
- Data(35 downto 26) => (others => '0'),
- WE => write,
- RdClock => CLK,
- RdClockEn => '1',
- Reset => RESET,
- WrClock => CLK,
- WrClockEn => '1',
- Q(35 downto 26) => Q_i2,
- Q(25 downto 16) => Max_EBR_out,
- Q(15 downto 10) => Q_i1,
- Q( 9 downto 0) => Min_EBR_out
- );
+ WrAddress(9 downto 6) => FPGA_write,
+ WrAddress(5 downto 0) => chnl_write(5 downto 0),
+ RdAddress(9 downto 6) => FPGA_read,
+ RdAddress(5 downto 0) => chnl_read(5 downto 0),
+ Data( 9 downto 0) => Min,
+ Data(15 downto 10) => (others => '0'),
+ Data(25 downto 16) => Max,
+ Data(35 downto 26) => (others => '0'),
+ WE => write,
+ RdClock => CLK,
+ RdClockEn => '1',
+ Reset => RESET,
+ WrClock => CLK,
+ WrClockEn => '1',
+ Q(35 downto 26) => Q_i2,
+ Q(25 downto 16) => Max_EBR_out,
+ Q(15 downto 10) => Q_i1,
+ Q( 9 downto 0) => Min_EBR_out
+ );
-
- RW_handler : process (CLK)
- begin
- if rising_edge(CLK) then
- -- handle read/write on same Address;
- -- delay of collision Output to sync with "normal" Q.
- if (write = '1') and (FPGA_write = FPGA_read) and (chnl_write = chnl_read) then
+
+ RW_handler : process (CLK)
+ begin
+ if rising_edge(CLK) then
+ -- handle read/write on same Address;
+ -- delay of collision Output to sync with "normal" Q.
+ if (write = '1') and (FPGA_write = FPGA_read) and (chnl_write = chnl_read) then
Q_col(20) <= '1';
Q_col(19 downto 10) <= Max;
Q_col( 9 downto 0) <= Min;
else
Q_col <= '0' & x"003FF";
- end if;
- -- selection between Q from collison or normal one
- if (Q_col_r(20) = '1') then
- Min_out <= Q_col_r( 9 downto 0);
- Max_out <= Q_col_r(19 downto 10);
- else
- if Min_EBR_out = "0000000000" then
- Min_out <= "1111111111";
- else
- Min_out <= Min_EBR_out;
- end if;
+ end if;
+ -- selection between Q from collison or normal one
+ if (Q_col_r(20) = '1') then
+ Min_out <= Q_col_r( 9 downto 0);
+ Max_out <= Q_col_r(19 downto 10);
+ else
+ if Min_EBR_out = "0000000000" then
+ Min_out <= "1111111111";
+ else
+ Min_out <= Min_EBR_out;
+ end if;
Max_out <= Max_EBR_out;
- end if;
- Q_col_r <= Q_col;
- end if;
- end process;
+ end if;
+ Q_col_r <= Q_col;
+ end if;
+ end process;
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
+library work;
+use work.trb_net_std.all;
entity Memory_curr is
- port (
- CLK : in std_logic;
- RESET : in std_logic;
- write : in std_logic;
- FPGA_read : in std_logic_vector( 3 downto 0);
- chnl_read : in std_logic_vector( 6 downto 0);
- FPGA_write : in std_logic_vector( 3 downto 0);
- chnl_write : in std_logic_vector( 6 downto 0);
- Min : in std_logic_vector( 9 downto 0);
- Max : in std_logic_vector( 9 downto 0);
- Do_Cal_in : in std_logic;
- DIN : in std_logic_vector(31 downto 0);
- DIN_ready : in std_logic;
- DIN_type : in std_logic_vector( 3 downto 0);
- Min_out : out std_logic_vector( 9 downto 0):= "1111111111";
- Max_out : out std_logic_vector( 9 downto 0):= "0000000000";
- DOUT : out std_logic_vector(31 downto 0);
- DOUT_ready : out std_logic;
- DOUT_type : out std_logic_vector( 3 downto 0);
- FPGA_out : out std_logic_vector( 3 downto 0);
- CHNL_out : out std_logic_vector( 6 downto 0);
- Do_Cal_out : out std_logic
- );
+ generic (
+ USE_STAT_BITS : integer range 0 to 1 := c_NO;
+ USE_DATA_WRITE : integer range 0 to 1 := c_NO;
+ USE_DATA_FINISHED : integer range 0 to 1 := c_NO;
+ USE_BUSY_RELEASE : integer range 0 to 1 := c_NO );
+ port (
+ CLK : in std_logic;
+ RESET : in std_logic;
+ stp_Lmt_in : in std_logic;
+ write : in std_logic;
+ FPGA_read : in std_logic_vector( 3 downto 0);
+ chnl_read : in std_logic_vector( 6 downto 0);
+ FPGA_write : in std_logic_vector( 3 downto 0);
+ chnl_write : in std_logic_vector( 6 downto 0);
+ Min : in std_logic_vector( 9 downto 0);
+ Max : in std_logic_vector( 9 downto 0);
+ Do_Cal_in : in std_logic;
+ DIN : in std_logic_vector(31 downto 0);
+ DIN_ready : in std_logic;
+ DIN_type : in std_logic_vector( 3 downto 0);
+ DIN_info : in std_logic_vector(( 31*USE_STAT_BITS + USE_DATA_WRITE + USE_DATA_FINISHED + USE_BUSY_RELEASE) downto 0);
+ Min_out : out std_logic_vector( 9 downto 0):= "1111111111";
+ Max_out : out std_logic_vector( 9 downto 0):= "0000000000";
+ DOUT : out std_logic_vector(31 downto 0);
+ DOUT_ready : out std_logic;
+ DOUT_type : out std_logic_vector( 3 downto 0);
+ FPGA_out : out std_logic_vector( 3 downto 0);
+ CHNL_out : out std_logic_vector( 6 downto 0);
+ Do_Cal_out : out std_logic;
+ stp_Lmt_out : out std_logic;
+ DOUT_info : out std_logic_vector(( 31*USE_STAT_BITS + USE_DATA_WRITE + USE_DATA_FINISHED + USE_BUSY_RELEASE) downto 0)
+ );
end Memory_curr;
architecture Behavioral of Memory_curr is
- signal Max_EBR_out : std_logic_vector(9 downto 0);
- signal Min_EBR_out : std_logic_vector(9 downto 0);
- signal Q_col, Q_col_r : std_logic_vector(20 downto 0) :='0' & x"00000";
- signal chnl_r, chnl_2r : std_logic_vector( 6 downto 0);
- signal fpga_r, fpga_2r : std_logic_vector( 3 downto 0);
- signal DIN_r, DIN_2r : std_logic_vector(31 downto 0);
- signal DIN_ready_r, DIN_ready_2r : std_logic;
- signal DIN_type_r, DIN_type_2r : std_logic_vector( 3 downto 0);
- signal Do_Cal_in_r, Do_Cal_in_2r : std_logic;
- signal Q_i1 : std_logic_vector(5 downto 0);
- signal Q_i2 : std_logic_vector(9 downto 0);
-
- component RAM_pseudo_DP_wReg_36x1k is
- port (
- WrAddress : in std_logic_vector(9 downto 0);
- RdAddress : in std_logic_vector(9 downto 0);
- Data : in std_logic_vector(35 downto 0);
- WE : in std_logic;
- RdClock : in std_logic;
- RdClockEn : in std_logic;
- Reset : in std_logic;
- WrClock : in std_logic;
- WrClockEn : in std_logic;
- Q : out std_logic_vector(35 downto 0)
- );
- end component RAM_pseudo_DP_wReg_36x1k;
+ signal Max_EBR_out : std_logic_vector( 9 downto 0);
+ signal Min_EBR_out : std_logic_vector( 9 downto 0);
+ signal Q_col, Q_col_r : std_logic_vector(20 downto 0) :='0' & x"00000";
+ signal chnl_r, chnl_2r : std_logic_vector( 6 downto 0);
+ signal fpga_r, fpga_2r : std_logic_vector( 3 downto 0);
+ signal DIN_r, DIN_2r : std_logic_vector(31 downto 0);
+ signal DIN_ready_r, DIN_ready_2r : std_logic;
+ signal DIN_type_r, DIN_type_2r : std_logic_vector( 3 downto 0);
+ signal Do_Cal_in_r, Do_Cal_in_2r : std_logic;
+ signal Q_i1 : std_logic_vector( 5 downto 0);
+ signal Q_i2 : std_logic_vector( 9 downto 0);
+ signal stop_Lim_r, stop_Lim_2r : std_logic;
+ signal DIN_info_r, DIN_info_2r : std_logic_vector(( 31*USE_STAT_BITS + USE_DATA_WRITE + USE_DATA_FINISHED + USE_BUSY_RELEASE) downto 0) := (others => '0');
+
+ component RAM_pseudo_DP_wReg_36x1k is
+ port (
+ WrAddress : in std_logic_vector( 9 downto 0);
+ RdAddress : in std_logic_vector( 9 downto 0);
+ Data : in std_logic_vector(35 downto 0);
+ WE : in std_logic;
+ RdClock : in std_logic;
+ RdClockEn : in std_logic;
+ Reset : in std_logic;
+ WrClock : in std_logic;
+ WrClockEn : in std_logic;
+ Q : out std_logic_vector(35 downto 0)
+ );
+ end component RAM_pseudo_DP_wReg_36x1k;
begin
THE_EBR_curr : RAM_pseudo_DP_wReg_36x1k
port map (
- WrAddress(9 downto 6) => FPGA_write,
- WrAddress(5 downto 0) => chnl_write(5 downto 0),
- RdAddress(9 downto 6) => FPGA_read,
- RdAddress(5 downto 0) => chnl_read(5 downto 0),
- Data( 9 downto 0) => Min,
- Data(15 downto 10) => (others => '0'),
- Data(25 downto 16) => Max,
- Data(35 downto 26) => (others => '0'),
- WE => write,
- RdClock => CLK,
- RdClockEn => '1',
- Reset => RESET,
- WrClock => CLK,
- WrClockEn => '1',
- Q(35 downto 26) => Q_i2,
- Q(25 downto 16) => Max_EBR_out,
- Q(15 downto 10) => Q_i1,
- Q( 9 downto 0) => Min_EBR_out
- );
+ WrAddress(9 downto 6) => FPGA_write,
+ WrAddress(5 downto 0) => chnl_write(5 downto 0),
+ RdAddress(9 downto 6) => FPGA_read,
+ RdAddress(5 downto 0) => chnl_read(5 downto 0),
+ Data( 9 downto 0) => Min,
+ Data(15 downto 10) => (others => '0'),
+ Data(25 downto 16) => Max,
+ Data(35 downto 26) => (others => '0'),
+ WE => write,
+ RdClock => CLK,
+ RdClockEn => '1',
+ Reset => RESET,
+ WrClock => CLK,
+ WrClockEn => '1',
+ Q(35 downto 26) => Q_i2,
+ Q(25 downto 16) => Max_EBR_out,
+ Q(15 downto 10) => Q_i1,
+ Q( 9 downto 0) => Min_EBR_out
+ );
-
- mem : process (CLK)
- begin
- if rising_edge(CLK) then
- -- handle read/write on same Address;
- -- delay of collision Output to sync with "normal" Q.
- if (write = '1') and (FPGA_write = FPGA_read) and (chnl_write = chnl_read) then
+
+ mem : process (CLK)
+ begin
+ if rising_edge(CLK) then
+ -- handle read/write on same Address;
+ -- delay of collision Output to sync with "normal" Q.
+ if (write = '1') and (FPGA_write = FPGA_read) and (chnl_write = chnl_read) then
Q_col(20) <= '1';
Q_col(19 downto 10) <= Max;
Q_col( 9 downto 0) <= Min;
else
Q_col <= '0' & x"00000";
- end if;
- -- selection between Q from collison or normal one
- if (Q_col_r(20) = '1') then
- Min_out <= Q_col_r( 9 downto 0);
- Max_out <= Q_col_r(19 downto 10);
- else
+ end if;
+ -- selection between Q from collison or normal one
+ if (Q_col_r(20) = '1') then
+ Min_out <= Q_col_r( 9 downto 0);
+ Max_out <= Q_col_r(19 downto 10);
+ else
Min_out <= Min_EBR_out;
Max_out <= Max_EBR_out;
- end if;
- Q_col_r <= Q_col;
- -- Delay to sync with EBR output
- DIN_r <= DIN;
- DIN_2r <= DIN_r;
- DOUT <= DIN_2r;
+ end if;
+ Q_col_r <= Q_col;
+ -- Delay to sync with EBR output
+ DIN_r <= DIN;
+ DIN_2r <= DIN_r;
+ DOUT <= DIN_2r;
- DIN_ready_r <= DIN_ready;
- DIN_ready_2r <= DIN_ready_r;
- DOUT_ready <= DIN_ready_2r;
+ DIN_ready_r <= DIN_ready;
+ DIN_ready_2r <= DIN_ready_r;
+ DOUT_ready <= DIN_ready_2r;
- DIN_type_r <= DIN_type;
- DIN_type_2r <= DIN_type_r;
- DOUT_type <= DIN_type_2r;
+ DIN_type_r <= DIN_type;
+ DIN_type_2r <= DIN_type_r;
+ DOUT_type <= DIN_type_2r;
+
+ DIN_info_r <= DIN_info;
+ DIN_info_2r <= DIN_info_r;
+ DOUT_info <= DIN_info_2r;
- fpga_r <= FPGA_read;
- fpga_2r <= fpga_r;
- FPGA_out <= fpga_2r;
+ fpga_r <= FPGA_read;
+ fpga_2r <= fpga_r;
+ FPGA_out <= fpga_2r;
- chnl_r <= chnl_read;
- chnl_2r <= chnl_r;
- CHNL_out <= chnl_2r;
+ chnl_r <= chnl_read;
+ chnl_2r <= chnl_r;
+ CHNL_out <= chnl_2r;
- Do_Cal_in_r <= Do_Cal_in;
- Do_Cal_in_2r <= Do_Cal_in_r;
- Do_Cal_out <= Do_Cal_in_2r;
- end if;
- end process;
+ Do_Cal_in_r <= Do_Cal_in;
+ Do_Cal_in_2r <= Do_Cal_in_r;
+ Do_Cal_out <= Do_Cal_in_2r;
+
+ stop_Lim_r <= stp_Lmt_in;
+ stop_Lim_2r <= stop_Lim_r;
+ stp_Lmt_out <= stop_Lim_2r;
+ end if;
+ end process;
end Behavioral;
use IEEE.NUMERIC_STD.ALL;
entity cnt_val is
- Port (
- CLK : in std_logic;
- RESET : in std_logic;
- write : in std_logic;
- FPGA_read : in std_logic_vector( 3 downto 0);
- chnl_read : in std_logic_vector( 6 downto 0);
- FPGA_write : in std_logic_vector( 3 downto 0);
- chnl_write : in std_logic_vector( 6 downto 0);
- cal_cnt : in unsigned(19 downto 0);
- DIN : in std_logic_vector(31 downto 0);
- DIN_ready : in std_logic;
- DIN_type : in std_logic_vector( 3 downto 0);
- cal_cnt_out : out unsigned(19 downto 0)--;
- --DOUT : out std_logic_vector(31 downto 0);
- --DOUT_ready : out std_logic;
- -- DOUT_type : out std_logic_vector( 3 downto 0)--;
--- FPGA_out : out std_logic_vector( 3 downto 0);
--- CHNL_out : out std_logic_vector( 6 downto 0)
- );
+ Port (
+ CLK : in std_logic;
+ RESET : in std_logic;
+ write : in std_logic;
+ FPGA_read : in std_logic_vector( 3 downto 0);
+ chnl_read : in std_logic_vector( 6 downto 0);
+ FPGA_write : in std_logic_vector( 3 downto 0);
+ chnl_write : in std_logic_vector( 6 downto 0);
+ cal_cnt : in unsigned(19 downto 0);
+ DIN : in std_logic_vector(31 downto 0);
+ DIN_ready : in std_logic;
+ DIN_type : in std_logic_vector( 3 downto 0);
+ cal_cnt_out : out unsigned(19 downto 0)--;
+ --DOUT : out std_logic_vector(31 downto 0);
+ --DOUT_ready : out std_logic;
+ --DOUT_type : out std_logic_vector( 3 downto 0)--;
+ --FPGA_out : out std_logic_vector( 3 downto 0);
+ --CHNL_out : out std_logic_vector( 6 downto 0)
+ );
end cnt_val;
architecture Behavioral of cnt_val is
- signal cal_cnt_i : std_logic_vector(19 downto 0) :=x"00000";
- signal Q_col, Q_col_r : std_logic_vector(20 downto 0) :='0' & x"00000";
--- signal chnl_r, chnl_2r : std_logic_vector( 6 downto 0);
--- signal fpga_r, fpga_2r : std_logic_vector( 3 downto 0);
- signal Q_i1 : std_logic_vector(15 downto 0);
+ signal cal_cnt_i : std_logic_vector(19 downto 0) :=x"00000";
+ signal Q_col, Q_col_r : std_logic_vector(20 downto 0) :='0' & x"00000";
+ signal Q_i1 : std_logic_vector(15 downto 0);
- component RAM_pseudo_DP_wReg_36x1k is
- port (
- WrAddress : in std_logic_vector(9 downto 0);
- RdAddress : in std_logic_vector(9 downto 0);
- Data : in std_logic_vector(35 downto 0);
- WE : in std_logic;
- RdClock : in std_logic;
- RdClockEn : in std_logic;
- Reset : in std_logic;
- WrClock : in std_logic;
- WrClockEn : in std_logic;
- Q : out std_logic_vector(35 downto 0)
- );
- end component RAM_pseudo_DP_wReg_36x1k;
+ component RAM_pseudo_DP_wReg_36x1k is
+ port (
+ WrAddress : in std_logic_vector(9 downto 0);
+ RdAddress : in std_logic_vector(9 downto 0);
+ Data : in std_logic_vector(35 downto 0);
+ WE : in std_logic;
+ RdClock : in std_logic;
+ RdClockEn : in std_logic;
+ Reset : in std_logic;
+ WrClock : in std_logic;
+ WrClockEn : in std_logic;
+ Q : out std_logic_vector(35 downto 0)
+ );
+ end component RAM_pseudo_DP_wReg_36x1k;
begin
THE_EBR_curr : RAM_pseudo_DP_wReg_36x1k
port map (
- WrAddress(9 downto 6) => FPGA_write,
- WrAddress(5 downto 0) => chnl_write(5 downto 0),
- RdAddress(9 downto 6) => FPGA_read,
- RdAddress(5 downto 0) => chnl_read(5 downto 0),
- Data(19 downto 0) => std_logic_vector(cal_cnt),
- Data(35 downto 20) => (others => '0'),
- WE => write,
- RdClock => CLK,
- RdClockEn => '1',
- Reset => RESET,
- WrClock => CLK,
- WrClockEn => '1',
- Q(35 downto 20) => Q_i1, --F**king modelsim wants it like this
- Q(19 downto 0) => cal_cnt_i
- );
+ WrAddress(9 downto 6) => FPGA_write,
+ WrAddress(5 downto 0) => chnl_write(5 downto 0),
+ RdAddress(9 downto 6) => FPGA_read,
+ RdAddress(5 downto 0) => chnl_read(5 downto 0),
+ Data(19 downto 0) => std_logic_vector(cal_cnt),
+ Data(35 downto 20) => (others => '0'),
+ WE => write,
+ RdClock => CLK,
+ RdClockEn => '1',
+ Reset => RESET,
+ WrClock => CLK,
+ WrClockEn => '1',
+ Q(35 downto 20) => Q_i1, --F**king modelsim wants it like this
+ Q(19 downto 0) => cal_cnt_i
+ );
- mem : process (CLK)
- begin
- if rising_edge(CLK) then
- -- handle read/write on same Address;
- -- delay of collision Output to sync with "normal" Q.
- if (write = '1') and (FPGA_write = FPGA_read) and (chnl_write = chnl_read) then
+ mem : process (CLK)
+ begin
+ if rising_edge(CLK) then
+ -- handle read/write on same Address;
+ -- delay of collision Output to sync with "normal" Q.
+ if (write = '1') and (FPGA_write = FPGA_read) and (chnl_write = chnl_read) then
Q_col(20) <= '1';
Q_col(19 downto 0) <= std_logic_vector(cal_cnt);
else
Q_col <= '0' & x"00000";
- end if;
- -- selection between Q from collison or normal one
- if (Q_col_r(20) = '1') then
- cal_cnt_out <= unsigned(Q_col_r(19 downto 0));
- else
- cal_cnt_out <= unsigned(cal_cnt_i);
- end if;
- Q_col_r <= Q_col;
- --delays to snyc with EBR
- --DOUT <= DIN;
- --DOUT_ready <= DIN_ready;
- --DOUT_type <= DIN_type;
--- fpga_r <= FPGA_read;
--- fpga_2r <= fpga_r;
--- FPGA_out <= fpga_2r;
--- chnl_r <= chnl_read;
--- chnl_2r <= chnl_r;
--- CHNL_out <= chnl_2r;
- end if;
- end process;
+ end if;
+ -- selection between Q from collison or normal one
+ if (Q_col_r(20) = '1') then
+ cal_cnt_out <= unsigned(Q_col_r(19 downto 0));
+ else
+ cal_cnt_out <= unsigned(cal_cnt_i);
+ end if;
+ Q_col_r <= Q_col;
+ end if;
+ end process;
end Behavioral;
use work.trb_net_std.all;
entity compare_old is
- Port (
- CLK : in std_logic;
- DIN : in std_logic_vector(31 downto 0);
- DIN_ready : in std_logic;
- DIN_type : in std_logic_vector( 3 downto 0);
- FPGA_in : in std_Logic_vector( 3 downto 0);
- CHNL_in : in std_logic_vector( 6 downto 0);
- Do_Cal_in : in std_Logic;
- CHNL_out : out std_logic_vector( 6 downto 0);
- FPGA_out : out std_logic_vector( 3 downto 0);
- DOUT : out std_logic_vector(31 downto 0);
- DOUT_ready : out std_logic;
- DOUT_type : out std_logic_vector( 3 downto 0);
- Do_Cal_out : out std_logic;
- read : out std_logic
- );
+ Port (
+ CLK : in std_logic;
+ DIN : in std_logic_vector(31 downto 0);
+ DIN_ready : in std_logic;
+ DIN_type : in std_logic_vector( 3 downto 0);
+ FPGA_in : in std_Logic_vector( 3 downto 0);
+ CHNL_in : in std_logic_vector( 6 downto 0);
+ Do_Cal_in : in std_Logic;
+ CHNL_out : out std_logic_vector( 6 downto 0);
+ FPGA_out : out std_logic_vector( 3 downto 0);
+ DOUT : out std_logic_vector(31 downto 0);
+ DOUT_ready : out std_logic;
+ DOUT_type : out std_logic_vector( 3 downto 0);
+ Do_Cal_out : out std_logic;
+ read : out std_logic
+ );
end compare_old;
architecture Behavioral of compare_old is
- signal FPGA_i : std_logic_vector( 3 downto 0):="0001";
- signal CHNL_i : std_logic_vector( 6 downto 0);
+ signal FPGA_i : std_logic_vector( 3 downto 0):="0001";
+ signal CHNL_i : std_logic_vector( 6 downto 0);
begin
- rd_cnt : process(CLK)
- begin
- if rising_edge(CLK) then
- if (Do_Cal_in = '1') then
- if (FPGA_in = FPGA_i) and (CHNL_in = CHNL_i) then -- same channel and fpga as before, no need to reread
- read <= '0';
- FPGA_out <= FPGA_i;
- CHNL_out <= CHNL_i;
- else -- different fpga/channel -> read again!
- read <= '1';
- FPGA_i <= FPGA_in;
- CHNL_i <= CHNL_in;
- FPGA_out <= FPGA_in;
- CHNL_out <= CHNL_in;
- end if;
- else
- read <= '0';
- end if;
- --loop through entity
- DOUT <= DIN;
- DOUT_ready <= DIN_ready;
- DOUT_type <= DIN_type;
- Do_Cal_out <= Do_Cal_in;
- end if;
- end process;
+ rd_cnt : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if (Do_Cal_in = '1') then
+ if (FPGA_in = FPGA_i) and (CHNL_in = CHNL_i) then -- same channel and fpga as before, no need to reread
+ read <= '0';
+ FPGA_out <= FPGA_i;
+ CHNL_out <= CHNL_i;
+ else -- different fpga/channel -> read again!
+ read <= '1';
+ FPGA_i <= FPGA_in;
+ CHNL_i <= CHNL_in;
+ FPGA_out <= FPGA_in;
+ CHNL_out <= CHNL_in;
+ end if;
+ else
+ read <= '0';
+ end if;
+ --loop through entity
+ DOUT <= DIN;
+ DOUT_ready <= DIN_ready;
+ DOUT_type <= DIN_type;
+ Do_Cal_out <= Do_Cal_in;
+ end if;
+ end process;
end Behavioral;
use work.trb_net_std.all;
entity read_cnt is
- Port (
- CLK : in std_logic;
- RESET : in std_logic;
- DIN : in std_logic_vector(31 downto 0);
- DIN_ready : in std_logic;
- DIN_type : in std_logic_vector( 3 downto 0);
- FPGA_in : in std_logic_vector(15 downto 0);
- chnl : out std_logic_vector( 6 downto 0);
- FPGA_out : out std_logic_vector( 3 downto 0);
- DOUT : out std_logic_vector(31 downto 0);
- DOUT_ready : out std_logic;
- DOUT_type : out std_logic_vector( 3 downto 0);
- Do_Cal : out std_logic;
- FPGA_cnt_mntr : out std_logic_vector( 3 downto 0);
- FPGA_mntr : out std_logic_vector(15 downto 0)
- );
+ generic (
+ USE_STAT_BITS : integer range 0 to 1 := c_NO;
+ USE_DATA_WRITE : integer range 0 to 1 := c_NO;
+ USE_DATA_FINISHED : integer range 0 to 1 := c_NO;
+ USE_BUSY_RELEASE : integer range 0 to 1 := c_NO );
+ port (
+ CLK : in std_logic;
+ RESET : in std_logic;
+ BUS_stp_Lmt : in std_logic;
+ BUS_Trig_type : in std_logic_vector( 3 downto 0);
+ DIN : in std_logic_vector(31 downto 0);
+ DIN_ready : in std_logic;
+ DIN_type : in std_logic_vector( 3 downto 0);
+ FPGA_in : in std_logic_vector(15 downto 0);
+ Trigger_type : in std_logic_vector( 3 downto 0);
+ DIN_info : in std_logic_vector(( 31*USE_STAT_BITS + USE_DATA_WRITE + USE_DATA_FINISHED + USE_BUSY_RELEASE) downto 0);
+ chnl : out std_logic_vector( 6 downto 0);
+ FPGA_out : out std_logic_vector( 3 downto 0);
+ DOUT : out std_logic_vector(31 downto 0);
+ DOUT_ready : out std_logic;
+ DOUT_type : out std_logic_vector( 3 downto 0);
+ Do_Cal : out std_logic;
+ FPGA_cnt_mntr : out std_logic_vector( 3 downto 0);
+ FPGA_mntr : out std_logic_vector(15 downto 0);
+ stop_Limit : out std_logic;
+ DOUT_info : out std_logic_vector(( 31*USE_STAT_BITS + USE_DATA_WRITE + USE_DATA_FINISHED + USE_BUSY_RELEASE) downto 0)
+ );
end read_cnt;
architecture Behavioral of read_cnt is
- type t_Fpga is array (0 to 15) of std_logic_vector(15 downto 0);
- signal FPGA_num : t_Fpga := (others => (others => '0'));
- signal cnt : integer range 0 to 15 := 0;
- signal FPGA_i : integer range 0 to 15 := 0;
- --signal save : std_logic_vector(11 downto 0);
+ type t_Fpga is array (0 to 15) of std_logic_vector(15 downto 0);
+ signal FPGA_num : t_Fpga := (others => (others => '0'));
+ signal cnt : integer range 0 to 15 := 0;
+ signal FPGA_i : integer range 0 to 15 := 0;
+ signal trig_type : std_logic_vector(3 downto 0);
begin
-
- rd_cnt : process(CLK)
- begin
- if rising_edge(CLK) then
- if (DIN(31) = '1') and (DIN_type = x"4") and (DIN_ready = '1') then
- chnl <= DIN(28 downto 22);
- FPGA_out <= std_logic_vector(to_unsigned(FPGA_i,4));
- if DIN(21 downto 12) /= "1111111111" and FPGA_in(15 downto 12) = x"1" then --3FF --toDO: without 15 downto 12
- Do_Cal <= '1';
- else
- Do_Cal <= '0';
- end if;
- else
- --FPGA_i <= 0;
- Do_Cal <= '0';
- end if;
- DOUT <= DIN;
- DOUT_ready <= DIN_ready;
- DOUT_type <= DIN_type;
- end if;
- end process;
+
+ rd_cnt : process(CLK)
+ begin
+ --ToDO:
+ -- * Find Triger=0xD (or what is set?)
+ -- * Only do Limits with Trig D // or dedicated trigger
+ -- * deactivate complete limit generation
+
+ if rising_edge(CLK) then
+ stop_Limit <= '1';
+ if (DIN(31) = '1') and (DIN_type = x"4") and (DIN_ready = '1') then -- real TDC_Data
+ --Trigger_type
+ chnl <= DIN(28 downto 22);
+ FPGA_out <= std_logic_vector(to_unsigned(FPGA_i,4));
+ if DIN(21 downto 12) /= "1111111111" then
+ Do_Cal <= '1';
+ if ((Trigger_type = BUS_Trig_type ) or (BUS_Trig_type = "0000")) then
+ stop_Limit <= BUS_stp_Lmt;
+ end if;
+ else
+ Do_Cal <= '0';
+ end if;
+ else
+ Do_Cal <= '0';
+ end if;
+ DOUT <= DIN;
+ DOUT_ready <= DIN_ready;
+ DOUT_type <= DIN_type;
+ DOUT_info <= DIN_info;
+ end if;
+ end process;
- THE_FPGA_num : process(CLK)
- variable position : std_logic_vector( 3 downto 0);
- variable save : std_logic_vector(11 downto 0) := X"000";
- begin
+ THE_FPGA_num : process(CLK)
+ variable position : std_logic_vector( 3 downto 0);
+ variable save : std_logic_vector(11 downto 0) := X"000";
+ begin
position := x"f";
if rising_edge(CLK) then
if RESET = '1' then
cnt <= 0;
else
- if DIN_ready = '1' then
- for i in 0 to 11 loop
- if FPGA_in = FPGA_num(i) then
- save(i) := '1';
- else
- save(i) := '0';
- end if;
- end loop;
-
- if save(11 downto 4) = x"00" then
- if save(3 downto 0) = x"0" then
- FPGA_i <= cnt;
- FPGA_num(cnt) <= FPGA_in;
- cnt <= cnt + 1;
- elsif save(0) = '1' then
- FPGA_i <= 0;
- elsif save(1) = '1' then
- FPGA_i <= 1;
- elsif save(2) = '1' then
- FPGA_i <= 2;
- elsif save(3) = '1' then
- FPGA_i <= 3;
- else
- --ERROR
- end if;
- elsif save(11 downto 8) = x"0" and save(3 downto 0) = x"0" then
- if save(4) = '1' then
- FPGA_i <= 4;
- elsif save(5) = '1' then
- FPGA_i <= 5;
- elsif save(6) = '1' then
- FPGA_i <= 6;
- elsif save(7) = '1' then
- FPGA_i <= 7;
- else
- --ERROR
- end if;
- elsif save(7 downto 0) = x"00" then
- if save(8) = '1' then
- FPGA_i <= 8;
- elsif save(9) = '1' then
- FPGA_i <= 9;
- elsif save(10) = '1' then
- FPGA_i <= 10;
- elsif save(11) = '1' then
- FPGA_i <= 11;
- else
- --ERROR
- end if;
- else
- --ERROR
- end if;
- end if;
+ if DIN_ready = '1' then
+ for i in 0 to 11 loop
+ if FPGA_in = FPGA_num(i) then
+ save(i) := '1';
+ else
+ save(i) := '0';
+ end if;
+ end loop;
+
+ if save(11 downto 4) = x"00" then
+ if save(3 downto 0) = x"0" then
+ FPGA_i <= cnt;
+ FPGA_num(cnt) <= FPGA_in;
+ cnt <= cnt + 1;
+ elsif save(0) = '1' then
+ FPGA_i <= 0;
+ elsif save(1) = '1' then
+ FPGA_i <= 1;
+ elsif save(2) = '1' then
+ FPGA_i <= 2;
+ elsif save(3) = '1' then
+ FPGA_i <= 3;
+ else
+ --ERROR
+ end if;
+ elsif save(11 downto 8) = x"0" and save(3 downto 0) = x"0" then
+ if save(4) = '1' then
+ FPGA_i <= 4;
+ elsif save(5) = '1' then
+ FPGA_i <= 5;
+ elsif save(6) = '1' then
+ FPGA_i <= 6;
+ elsif save(7) = '1' then
+ FPGA_i <= 7;
+ else
+ --ERROR
+ end if;
+ elsif save(7 downto 0) = x"00" then
+ if save(8) = '1' then
+ FPGA_i <= 8;
+ elsif save(9) = '1' then
+ FPGA_i <= 9;
+ elsif save(10) = '1' then
+ FPGA_i <= 10;
+ elsif save(11) = '1' then
+ FPGA_i <= 11;
+ else
+ --ERROR
+ end if;
+ else
+ --ERROR
+ end if;
+ end if;
end if;
- FPGA_mntr <= FPGA_num(FPGA_i);
- FPGA_cnt_mntr <= std_logic_vector(to_unsigned(FPGA_i,4));
+ FPGA_mntr <= FPGA_num(FPGA_i);
+ FPGA_cnt_mntr <= std_logic_vector(to_unsigned(FPGA_i,4));
end if;
- end process;
-
+ end process;
+
end Behavioral;
\ No newline at end of file
signal int2med : int2med_array_t(0 to INTERFACE_NUM-1);
signal med_stat_debug : std_logic_vector (1*64-1 downto 0);
- signal ctrlbus_rx, bustools_rx, bustc_rx, bus_master_out, handlerbus_rx, busdebug_rx, bustdccal_rx : CTRLBUS_RX;
- signal ctrlbus_tx, bustools_tx, bustc_tx, bus_master_in , busdebug_tx ,bustdccal_tx : CTRLBUS_TX;
+ signal ctrlbus_rx, bustools_rx, bustc_rx, bus_master_out, handlerbus_rx, busdebug_rx, bustdccal_rx : CTRLBUS_RX;
+ signal ctrlbus_tx, bustools_tx, bustc_tx, bus_master_in , busdebug_tx ,bustdccal_tx : CTRLBUS_TX;
signal bussci_tx : ctrlbus_tx_array_t(0 to 3);
signal bussci_rx : ctrlbus_rx_array_t(0 to 3);
signal back_slave_ready_i : std_logic_vector(12 downto 1);
signal master_ready_override_i : std_logic_vector(12 downto 1);
- signal fee_data : std_logic_vector(15 downto 0);
- signal fee_dataready : std_logic;
- signal fee_busy : std_logic;
- signal fee_read : std_logic;
- signal fee_status_bits : std_logic_vector(31 downto 0);
+ signal fee_data : std_logic_vector(15 downto 0);
+ signal fee_dataready : std_logic;
+ signal fee_busy : std_logic;
+ signal fee_read : std_logic;
+ signal fee_status_bits : std_logic_vector(31 downto 0);
- signal fee_packer_cnt : std_logic_vector(16 downto 0) := (others => '0');
- signal fee_packer_data : std_logic_vector(31 downto 0);
- signal fee_packer_dataready : std_logic;
+ signal fee_packer_cnt : std_logic_vector(16 downto 0) := (others => '0');
+ signal fee_packer_data : std_logic_vector(31 downto 0);
+ signal fee_packer_dataready : std_logic;
- signal cts_start_readout : std_logic;
- signal Data_stream : std_logic_vector(31 downto 0);
- signal packer_cnt_HL : std_logic := '0';
- signal fee_length : std_logic_vector(15 downto 0);
+ signal cts_start_readout : std_logic;
+ signal Data_stream : std_logic_vector(31 downto 0);
+ signal packer_cnt_HL : std_logic := '0';
+ signal fee_length : std_logic_vector(15 downto 0);
signal fee_packer_data_finished : std_logic;
signal fee_packer_statusBits : std_logic_vector(31 downto 0);
signal pckr_RX_state : pckr_RX_state_type;
signal pckr_TX_state : pckr_TX_state_type;
- signal EvInf_data : std_logic_vector(31 downto 0);
- signal EvStatBits : std_logic_vector(31 downto 0);
- signal pckr_Data : std_logic_vector(31 downto 0);
- signal pckr_Data_ready : std_logic;
- signal pckr_Data_Length_Ev : std_logic_vector(15 downto 0);
- signal pckr_Data_Source : std_logic_vector(15 downto 0);
- signal sse_fee_addr : std_logic_vector(15 downto 0);
- signal pckr_Data_type : std_logic_vector( 3 downto 0);
+ signal EvInf_data : std_logic_vector(31 downto 0);
+ signal EvStatBits : std_logic_vector(31 downto 0);
+ signal pckr_Data : std_logic_vector(31 downto 0);
+ signal pckr_Data_ready : std_logic;
+ signal pckr_Data_Length_Ev : std_logic_vector(15 downto 0);
+ signal pckr_Data_Source : std_logic_vector(15 downto 0);
+ signal sse_fee_addr : std_logic_vector(15 downto 0);
+ signal pckr_Data_type : std_logic_vector( 3 downto 0);
- signal cts_data : std_logic_vector(31 downto 0) := x"F0F1F2F3";
- signal cts_length : std_logic_vector(15 downto 0);
- signal cts_read : std_logic;
- signal cts_dataready : std_logic := '0';
- signal cts_finished : std_logic;
+ signal cts_data : std_logic_vector(31 downto 0) := x"F0F1F2F3";
+ signal cts_length : std_logic_vector(15 downto 0);
+ signal cts_read : std_logic;
+ signal cts_dataready : std_logic := '0';
+ signal cts_finished : std_logic;
- signal pckr_fifo_full : std_logic;
- signal pckr_fifo_empty : std_logic;
- signal fifo_rdEn : std_logic;
+ signal pckr_fifo_full : std_logic;
+ signal pckr_fifo_empty : std_logic;
+ signal fifo_rdEn : std_logic;
signal fifo_rdEn_r, fifo_rdEn_2r, fifo_rdEn_3r : std_logic;
- signal fifo_data_out : std_logic_vector(35 downto 0);
+ signal fifo_data_out : std_logic_vector(35 downto 0);
- signal FSM_state_RX : std_logic_vector(31 downto 0);
- signal FSM_state_TX : std_logic_vector(31 downto 0);
- signal WCNT_i : std_logic_vector(15 downto 0);
+ signal FSM_state_RX : std_logic_vector(31 downto 0);
+ signal FSM_state_TX : std_logic_vector(31 downto 0);
+ signal WCNT_i : std_logic_vector(15 downto 0);
- signal DEBUG_fifo_rdEn : unsigned(31 downto 0);
- signal DEBUG_cts_read : unsigned(31 downto 0);
- signal DEBUG_enable_fifo_rdEn : std_logic;
- signal DEBUG_cts_dataready : std_logic := '0';
- signal DEBUG_EvtLength : unsigned(15 downto 0);
+ signal DEBUG_fifo_rdEn : unsigned(31 downto 0);
+ signal DEBUG_cts_read : unsigned(31 downto 0);
+ signal DEBUG_enable_fifo_rdEn : std_logic;
+ signal DEBUG_cts_dataready : std_logic := '0';
+ signal DEBUG_EvtLength : unsigned(15 downto 0);
- signal already_asked : std_logic := '0';
- signal rd_enabled : std_logic := '1';
+ signal already_asked : std_logic := '0';
+ signal rd_enabled : std_logic := '1';
signal my_network_address : std_logic_vector(15 downto 0);
---------------------------
----- TDC CALIBRATION -----
---------------------------
- signal tdc_cal_data_out : std_logic_vector(31 downto 0);
- signal tdc_cal_type_out : std_logic_vector( 3 downto 0);
- signal tdc_cal_ready_out : std_logic;
- signal tdc_cal_stat_out : std_logic_vector(31 downto 0);
- signal FPGA : std_logic_vector(15 downto 0);
+ signal tdc_cal_data_out : std_logic_vector(31 downto 0);
+ signal tdc_cal_type_out : std_logic_vector( 3 downto 0);
+ signal tdc_cal_ready_out : std_logic;
+ signal tdc_cal_stat_out : std_logic_vector(31 downto 0);
+ signal FPGA : std_logic_vector(15 downto 0);
- signal MUX_cal_dout : std_logic_vector(31 downto 0);
- signal MUX_cal_dout_type : std_logic_vector( 3 downto 0);
- signal MUX_cal_dout_ready : std_logic;
- signal MUX_cal_dout_stat : std_logic_vector(31 downto 0);
- signal MUX_cal_sw : std_logic := '1';
+ signal MUX_cal_dout : std_logic_vector(31 downto 0);
+ signal MUX_cal_dout_type : std_logic_vector( 3 downto 0);
+ signal MUX_cal_dout_ready : std_logic;
+ signal MUX_cal_dout_stat : std_logic_vector(31 downto 0);
+ signal MUX_cal_sw : std_logic := '1';
signal DEBUG_read_enable_fifo_vnt : std_logic_vector(31 downto 0);
signal DEBUG_read_enable_fifo_cnt : std_logic_vector(31 downto 0);
signal DEBUG_read_enable_fifo_vnt1 : std_logic_vector(31 downto 0);
signal DEBUG_read_enable_fifo_cnt2 : std_logic_vector(31 downto 0);
+
+ signal Trigger_type : std_logic_vector( 3 downto 0);
+
component FIFO_36x64 is
port (
Data: in std_logic_vector(35 downto 0);
component fifo_36x32k_oreg
port (
- Data : in std_logic_vector(35 downto 0);
- Clock : in std_logic;
- WrEn : in std_logic;
- RdEn : in std_logic;
- Reset : in std_logic;
- AmFullThresh : in std_logic_vector(14 downto 0);
- Q : out std_logic_vector(35 downto 0);
- WCNT : out std_logic_vector(15 downto 0);
- Empty : out std_logic;
- Full : out std_logic;
- AlmostFull : out std_logic);
+ Data : in std_logic_vector(35 downto 0);
+ Clock : in std_logic;
+ WrEn : in std_logic;
+ RdEn : in std_logic;
+ Reset : in std_logic;
+ AmFullThresh : in std_logic_vector(14 downto 0);
+ Q : out std_logic_vector(35 downto 0);
+ WCNT : out std_logic_vector(15 downto 0);
+ Empty : out std_logic;
+ Full : out std_logic;
+ AlmostFull : out std_logic);
end component;
begin
THE_DATAPACKER_FSM_RX : process
- variable sse_length_cntr : unsigned(15 downto 0) := x"0000";
- variable pckr_Data_Length_Ev_cntr : unsigned(15 downto 0);
- variable fpga_flag : std_logic := '0';
+ variable sse_length_cntr : unsigned(15 downto 0) := x"0000";
+ variable pckr_Data_Length_Ev_cntr : unsigned(15 downto 0);
+ variable fpga_flag : std_logic := '0';
begin
wait until rising_edge(clk_sys);
else
case pckr_RX_state is
- when IDLE =>
- if cts_start_readout = '1' then
- pckr_RX_state <= WAITING;
- EvInf_data <= (others => '0');
- end if;
- FSM_state_RX <= x"00000001";
-
- when WAITING =>
- if fee_busy = '1' then
- pckr_RX_state <= EVINF_H;
- end if;
- FSM_state_RX <= x"00000002";
-
- when EVINF_H =>
- if (fee_dataready and fee_read) = '1' then
- EvInf_data(31 downto 16) <= fee_data; --not necessry
- pckr_Data(31 downto 16) <= fee_data;
- pckr_RX_state <= EVINF_L;
- end if;
- FSM_state_RX <= x"00000003";
-
- when EVINF_L => --triggerNMBR
- if (fee_dataready and fee_read) = '1' then
- EvInf_data(15 downto 0) <= fee_data; --not necessry
- pckr_Data(15 downto 0) <= fee_data;
- pckr_Data_type <= x"1";
- pckr_Data_ready <= '1';
- pckr_RX_state <= LENGTH;
- end if;
- FSM_state_RX <= x"00000004";
-
- when LENGTH =>
- if (fee_dataready and fee_read) = '1' then
- pckr_Data(31 downto 16) <= fee_data;
- pckr_Data_Length_Ev <= fee_data; --for CTS
- pckr_Data_Length_Ev_cntr := unsigned(fee_data);
- pckr_RX_state <= SOURCE;
- end if;
- FSM_state_RX <= x"00000005";
-
- when SOURCE =>
- if (fee_dataready and fee_read) = '1' then
- pckr_Data_Source <= fee_data; --not necessary
- pckr_Data(15 downto 0) <= fee_data;
- my_network_address <= fee_data;
- pckr_Data_type <= x"2";
- pckr_Data_ready <= '1';
- pckr_RX_state <= SSE_DATA_H;--SSE_LENGTH; CHANGED FOR PACKING MODE
- end if;
- fpga_flag := '0';
- sse_length_cntr := x"0000";
- FSM_state_RX <= x"00000006";
-
- when SSE_LENGTH =>
- if (fee_dataready and fee_read) = '1' then
- pckr_Data(31 downto 16) <= fee_data;
- --see_length <= fee_data;
- sse_length_cntr := unsigned(fee_data);
- pckr_RX_state <= SSE_FEE_ID;
- end if;
- FSM_state_RX <= x"00000007";
-
- when SSE_FEE_ID => --Analysing Data
- if (fee_dataready and fee_read) = '1' then
- pckr_Data(15 downto 0) <= fee_data;
- pckr_Data_type <= x"3"; --SSE_HDR
- pckr_Data_ready <= '1';
- sse_fee_addr <= fee_data;
- pckr_RX_state <= SSE_DATA_H;
-
- pckr_Data_Length_Ev_cntr := pckr_Data_Length_Ev_cntr - 1;
- -- if sse_length_cntr = x"0000" then
- -- pckr_RX_state <= SSE_LENGTH;
- -- end if;
- end if;
- FSM_state_RX <= x"00000008";
-
- when SSE_DATA_H =>
- if (fee_dataready and fee_read) = '1' then
- pckr_Data(31 downto 16) <= fee_data;
- pckr_RX_state <= SSE_DATA_L;
- if sse_length_cntr = x"0000" then -- FPGA Number
- sse_length_cntr := unsigned(fee_data);
- fpga_flag := '1';
- else
- sse_length_cntr := sse_length_cntr - 1;
- end if;
- end if;
- FSM_state_RX <= x"00000009";
-
- when SSE_DATA_L => --Analysing Data
- if (fee_dataready and fee_read) = '1' then
- pckr_Data(15 downto 0) <= fee_data;
- if fpga_flag = '1' then
- pckr_Data_type <= x"5"; --SSE_DATA
- else
- pckr_Data_type <= x"4"; --SSE_DATA
- end if;
- pckr_Data_ready <= '1';
- if fpga_flag = '1' then
- FPGA <= fee_data;
- fpga_flag := '0';
- end if;
- pckr_Data_Length_Ev_cntr := pckr_Data_Length_Ev_cntr - 1;
-
- -- data handling
- --------------------------- NON PACKING --------------
- -- if sse_length_cntr = x"0000" then
- -- if pckr_Data_Length_Ev_cntr = x"0000" then
- -- pckr_RX_state <= STAT_BITS;
- -- else
- -- pckr_RX_state <= SSE_LENGTH;
- -- end if;
- -- else
- -- pckr_RX_state <= SSE_DATA_H;
- -- end if;
+ when IDLE =>
+ if cts_start_readout = '1' then
+ pckr_RX_state <= WAITING;
+ EvInf_data <= (others => '0');
+ end if;
+ FSM_state_RX <= x"00000001";
+
+ when WAITING =>
+ if fee_busy = '1' then
+ pckr_RX_state <= EVINF_H;
+ end if;
+ FSM_state_RX <= x"00000002";
+
+ when EVINF_H =>
+ if (fee_dataready and fee_read) = '1' then
+ EvInf_data(31 downto 16) <= fee_data; --not necessry
+ Trigger_type <= fee_data(11 downto 8);
+ pckr_Data(31 downto 16) <= fee_data;
+ pckr_RX_state <= EVINF_L;
+ end if;
+ FSM_state_RX <= x"00000003";
+
+ when EVINF_L => --triggerNMBR
+ if (fee_dataready and fee_read) = '1' then
+ EvInf_data(15 downto 0) <= fee_data; --not necessry
+ pckr_Data(15 downto 0) <= fee_data;
+ pckr_Data_type <= x"1";
+ pckr_Data_ready <= '1';
+ pckr_RX_state <= LENGTH;
+ end if;
+ FSM_state_RX <= x"00000004";
+
+ when LENGTH =>
+ if (fee_dataready and fee_read) = '1' then
+ pckr_Data(31 downto 16) <= fee_data;
+ pckr_Data_Length_Ev <= fee_data; --for CTS
+ pckr_Data_Length_Ev_cntr := unsigned(fee_data);
+ pckr_RX_state <= SOURCE;
+ end if;
+ FSM_state_RX <= x"00000005";
+
+ when SOURCE =>
+ if (fee_dataready and fee_read) = '1' then
+ pckr_Data_Source <= fee_data; --not necessary
+ pckr_Data(15 downto 0) <= fee_data;
+ my_network_address <= fee_data;
+ pckr_Data_type <= x"2";
+ pckr_Data_ready <= '1';
+ pckr_RX_state <= SSE_DATA_H;--SSE_LENGTH; CHANGED FOR PACKING MODE
+ end if;
+ fpga_flag := '0';
+ sse_length_cntr := x"0000";
+ FSM_state_RX <= x"00000006";
+
+ when SSE_LENGTH =>
+ if (fee_dataready and fee_read) = '1' then
+ pckr_Data(31 downto 16) <= fee_data;
+ --see_length <= fee_data;
+ sse_length_cntr := unsigned(fee_data);
+ pckr_RX_state <= SSE_FEE_ID;
+ end if;
+ FSM_state_RX <= x"00000007";
+
+ when SSE_FEE_ID => --Analysing Data
+ if (fee_dataready and fee_read) = '1' then
+ pckr_Data(15 downto 0) <= fee_data;
+ pckr_Data_type <= x"3"; --SSE_HDR
+ pckr_Data_ready <= '1';
+ sse_fee_addr <= fee_data;
+ pckr_RX_state <= SSE_DATA_H;
+
+ pckr_Data_Length_Ev_cntr := pckr_Data_Length_Ev_cntr - 1;
+ -- if sse_length_cntr = x"0000" then
+ -- pckr_RX_state <= SSE_LENGTH;
+ -- end if;
+ end if;
+ FSM_state_RX <= x"00000008";
+
+ when SSE_DATA_H =>
+ if (fee_dataready and fee_read) = '1' then
+ pckr_Data(31 downto 16) <= fee_data;
+ pckr_RX_state <= SSE_DATA_L;
+ if sse_length_cntr = x"0000" then -- FPGA Number
+ sse_length_cntr := unsigned(fee_data);
+ fpga_flag := '1';
+ else
+ sse_length_cntr := sse_length_cntr - 1;
+ end if;
+ end if;
+ FSM_state_RX <= x"00000009";
+
+ when SSE_DATA_L => --Analysing Data
+ if (fee_dataready and fee_read) = '1' then
+ pckr_Data(15 downto 0) <= fee_data;
+ if fpga_flag = '1' then
+ pckr_Data_type <= x"5"; --SSE_DATA
+ else
+ pckr_Data_type <= x"4"; --SSE_DATA
+ end if;
+ pckr_Data_ready <= '1';
+ if fpga_flag = '1' then
+ FPGA <= fee_data;
+ fpga_flag := '0';
+ end if;
+ pckr_Data_Length_Ev_cntr := pckr_Data_Length_Ev_cntr - 1;
+
+ -- data handling
+ --------------------------- NON PACKING --------------
+ -- if sse_length_cntr = x"0000" then
+ -- if pckr_Data_Length_Ev_cntr = x"0000" then
+ -- pckr_RX_state <= STAT_BITS;
+ -- else
+ -- pckr_RX_state <= SSE_LENGTH;
+ -- end if;
+ -- else
+ -- pckr_RX_state <= SSE_DATA_H;
+ -- end if;
- if pckr_Data_Length_Ev_cntr = x"0000" then
- pckr_RX_state <= STAT_BITS;
- else
- pckr_RX_state <= SSE_DATA_H;
- end if;
+ if pckr_Data_Length_Ev_cntr = x"0000" then
+ pckr_RX_state <= STAT_BITS;
+ else
+ pckr_RX_state <= SSE_DATA_H;
+ end if;
- end if;
- FSM_state_RX <= x"0000000A";
-
- when STAT_BITS => --Analysing Data
- if (fee_busy) = '0' then
- EvStatBits <= fee_status_bits;
- pckr_RX_state <= IDLE;
- end if;
- FSM_state_RX <= x"0000000B";
-
- when others =>
- FSM_state_RX <= x"00000000";
-
-
+ end if;
+ FSM_state_RX <= x"0000000A";
+
+ when STAT_BITS => --Analysing Data
+ if (fee_busy) = '0' then
+ EvStatBits <= fee_status_bits;
+ pckr_RX_state <= IDLE;
+ end if;
+ FSM_state_RX <= x"0000000B";
+
+ when others =>
+ FSM_state_RX <= x"00000000";
+
+
end case;
end if;
end process;
-----------------------------------------------------------------------
THE_TDC_CAL : entity work.TDC_Calibration
+ generic map(
+ IS_COMBINER => c_YES,
+ USE_STAT_BITS => c_NO,
+ USE_DATA_WRITE => c_NO,
+ USE_DATA_FINISHED => c_NO,
+ USE_BUSY_RELEASE => c_NO
+ )
port map (
- CLK => clk_sys,
- RESET => reset_i,
- DIN => pckr_Data,
- DIN_TYPE => pckr_Data_type,
- DIN_READY => pckr_Data_ready,
- DIN_STAT => EvStatBits,
- FPGA_in => FPGA,
- DOUT => tdc_cal_data_out,
- DOUT_TYPE => tdc_cal_type_out,
- DOUT_READY => tdc_cal_ready_out,
- DOUT_STAT => tdc_cal_stat_out,
- BUS_RX => bustdccal_rx,
- BUS_TX => bustdccal_tx);
+ CLK => clk_sys,
+ RESET => reset_i,
+ DIN => pckr_Data,
+ DIN_TYPE => pckr_Data_type,
+ DIN_READY => pckr_Data_ready,
+ DIN_STAT => EvStatBits,
+ FPGA_in => FPGA,
+ TRIGG_TYPE => Trigger_type,
+ DOUT => tdc_cal_data_out,
+ DOUT_TYPE => tdc_cal_type_out,
+ DOUT_READY => tdc_cal_ready_out,
+ DOUT_STAT => tdc_cal_stat_out,
+ BUS_RX => bustdccal_rx,
+ BUS_TX => bustdccal_tx,
+ DIN_info => (others => '0'),
+ DOUT_info => open);
-----------------------------------------------------------------------
- THE_CAL_MUX : process
- begin
- wait until rising_edge(clk_sys);
+ THE_CAL_MUX : process
+ begin
+ wait until rising_edge(clk_sys);
- if MUX_cal_sw = '0' then
- MUX_cal_dout <= pckr_Data;
- MUX_cal_dout_type <= pckr_Data_type;
- MUX_cal_dout_ready <= pckr_Data_ready;
- MUX_cal_dout_stat <= EvStatBits;
- else
- MUX_cal_dout <= tdc_cal_data_out;
- MUX_cal_dout_type <= tdc_cal_type_out;
- MUX_cal_dout_ready <= tdc_cal_ready_out;
- MUX_cal_dout_stat <= tdc_cal_stat_out;
- end if;
- end process;
+ if MUX_cal_sw = '0' then
+ MUX_cal_dout <= pckr_Data;
+ MUX_cal_dout_type <= pckr_Data_type;
+ MUX_cal_dout_ready <= pckr_Data_ready;
+ MUX_cal_dout_stat <= EvStatBits;
+ else
+ MUX_cal_dout <= tdc_cal_data_out;
+ MUX_cal_dout_type <= tdc_cal_type_out;
+ MUX_cal_dout_ready <= tdc_cal_ready_out;
+ MUX_cal_dout_stat <= tdc_cal_stat_out;
+ end if;
+ end process;
-----------------------------------------------------------------------
THE_FIFO_36x32k : fifo_36x32k_oreg
port map (
- Data(31 downto 0) => MUX_cal_dout,
- Data(35 downto 32) => MUX_cal_dout_type,
- Clock => clk_sys,
- WrEn => MUX_cal_dout_ready,
- RdEn => fifo_rdEn,
- Reset => reset_i,
- AmFullThresh(14 downto 0) => b"011111111111111",
- Q => fifo_data_out,
- WCNT(15 downto 0) => WCNT_i,
- Empty => pckr_fifo_empty,
- Full => pckr_fifo_full,
- AlmostFull => open);
+ Data(31 downto 0) => MUX_cal_dout,
+ Data(35 downto 32) => MUX_cal_dout_type,
+ Clock => clk_sys,
+ WrEn => MUX_cal_dout_ready,
+ RdEn => fifo_rdEn,
+ Reset => reset_i,
+ AmFullThresh(14 downto 0) => b"011111111111111",
+ Q => fifo_data_out,
+ WCNT(15 downto 0) => WCNT_i,
+ Empty => pckr_fifo_empty,
+ Full => pckr_fifo_full,
+ AlmostFull => open);
-----------------------------------------------------------------------
THE_DATAPACKER_FSM_TX : process --data buffer is necessary
- variable EvInf_TX : std_logic_vector(31 downto 0);
- variable EvLength_TX : std_logic_vector(15 downto 0);
- variable EvLength_TX_cntr : unsigned(15 downto 0);
- variable Header_ready : std_logic:='0';
- variable Data_Fifo : std_logic_vector(35 downto 0);
- variable pckr_TX_data : std_logic_vector(31 downto 0);
- variable pckr_TX_data_type : std_logic_vector( 3 downto 0);
- variable buf_fifo_0 : std_logic_vector(35 downto 0);
- variable buf_fifo_1 : std_logic_vector(35 downto 0);
- variable buf_fifo_2 : std_logic_vector(35 downto 0);
- variable buf_fifo_cnt : std_logic_vector( 1 downto 0) := "00";
- variable enable_fifo_rdEn : std_logic;
+ variable EvInf_TX : std_logic_vector(31 downto 0);
+ variable EvLength_TX : std_logic_vector(15 downto 0);
+ variable EvLength_TX_cntr : unsigned(15 downto 0);
+ variable Header_ready : std_logic:='0';
+ variable Data_Fifo : std_logic_vector(35 downto 0);
+ variable pckr_TX_data : std_logic_vector(31 downto 0);
+ variable pckr_TX_data_type : std_logic_vector( 3 downto 0);
+ variable buf_fifo_0 : std_logic_vector(35 downto 0);
+ variable buf_fifo_1 : std_logic_vector(35 downto 0);
+ variable buf_fifo_2 : std_logic_vector(35 downto 0);
+ variable buf_fifo_cnt : std_logic_vector( 1 downto 0) := "00";
+ variable enable_fifo_rdEn : std_logic;
variable pckr_TX_data_ready : std_logic;
- variable dataready : std_logic;
+ variable dataready : std_logic;
begin
wait until rising_edge(clk_sys);
cts_finished <= '0';
- fifo_rdEn <= '0';
- fifo_rdEn_r <= fifo_rdEn;
+ fifo_rdEn <= '0';
+ fifo_rdEn_r <= fifo_rdEn;
fifo_rdEn_2r <= fifo_rdEn_r; --2r is readySignal
dataready := '0';
--is executed
- if reset_i = '1' then
- pckr_TX_state <= EVNT;
- already_asked <= '0';
- else
-
- if already_asked = '0' then
- if cts_dataready = '0' then
- already_asked <= '1';
- rd_enabled <= '0';
- DEBUG_read_enable_fifo_cnt <= std_logic_vector(unsigned(DEBUG_read_enable_fifo_cnt) + 1);
- end if;
- end if;
+ if reset_i = '1' then
+ pckr_TX_state <= EVNT;
+ already_asked <= '0';
+ else
+
+ if already_asked = '0' then
+ if cts_dataready = '0' then
+ already_asked <= '1';
+ rd_enabled <= '0';
+ DEBUG_read_enable_fifo_cnt <= std_logic_vector(unsigned(DEBUG_read_enable_fifo_cnt) + 1);
+ end if;
+ end if;
- if already_asked = '1' then
- if pckr_fifo_empty = '0' and rd_enabled = '0' then
- fifo_rdEn <= '1';
- rd_enabled <= '1';
- else
-
- end if;
- if fifo_rdEn_2r = '1' then
- dataready := '1';
- already_asked <= '0';
- DEBUG_read_enable_fifo_cnt2 <= std_logic_vector(unsigned(DEBUG_read_enable_fifo_cnt2) + 1);
- pckr_TX_data := fifo_data_out(31 downto 0);
- pckr_TX_data_type := fifo_data_out(35 downto 32);
- end if;
- end if;
+ if already_asked = '1' then
+ if pckr_fifo_empty = '0' and rd_enabled = '0' then
+ fifo_rdEn <= '1';
+ rd_enabled <= '1';
+ else
+
+ end if;
+ if fifo_rdEn_2r = '1' then
+ dataready := '1';
+ already_asked <= '0';
+ DEBUG_read_enable_fifo_cnt2 <= std_logic_vector(unsigned(DEBUG_read_enable_fifo_cnt2) + 1);
+ pckr_TX_data := fifo_data_out(31 downto 0);
+ pckr_TX_data_type := fifo_data_out(35 downto 32);
+ end if;
+ end if;
- case pckr_TX_state is
- when EVNT =>
- if cts_start_readout = '1' then
- if dataready = '1' then
- DEBUG_read_enable_fifo_vnt1 <= std_logic_vector(unsigned(DEBUG_read_enable_fifo_vnt1) + 1);
- if pckr_TX_data_type = x"1" then
- --EvInf_TX := pckr_TX_data;
- cts_data <= pckr_TX_data;
- end if; --maybe a flag that x"1" is set before x"2" comes?
+ case pckr_TX_state is
+ when EVNT =>
+ if cts_start_readout = '1' then
+ if dataready = '1' then
+ DEBUG_read_enable_fifo_vnt1 <= std_logic_vector(unsigned(DEBUG_read_enable_fifo_vnt1) + 1);
+ if pckr_TX_data_type = x"1" then
+ --EvInf_TX := pckr_TX_data;
+ cts_data <= pckr_TX_data;
+ end if; --maybe a flag that x"1" is set before x"2" comes?
- if pckr_TX_data_type = x"2" then
- cts_length <= pckr_TX_data(31 downto 16);
- EvLength_TX_cntr := pckr_TX_data(31 downto 16);
- Header_ready := '1';
- end if;
- end if;
- --cts_data <= EvInf_TX;
- --cts_length <= EvLength_TX;
+ if pckr_TX_data_type = x"2" then
+ cts_length <= pckr_TX_data(31 downto 16);
+ EvLength_TX_cntr := pckr_TX_data(31 downto 16);
+ Header_ready := '1';
+ end if;
+ end if;
+ --cts_data <= EvInf_TX;
+ --cts_length <= EvLength_TX;
- if Header_ready = '1' then
- DEBUG_read_enable_fifo_vnt <= std_logic_vector(unsigned(DEBUG_read_enable_fifo_vnt) + 1);
- cts_dataready <= '1';
- if cts_read = '1' and cts_dataready = '1' then
- pckr_TX_state <= DATA;
- cts_dataready <= '0';
- Header_ready := '0';
- end if;
- end if;
- FSM_state_TX <= x"00000001";
- end if;
-
- when DATA =>
-
- if pckr_TX_data_type = x"3" or pckr_TX_data_type = x"4" or pckr_TX_data_type = x"5" then
- if dataready = '1' then
- cts_data <= pckr_TX_data;
- cts_dataready <= '1';
- end if;
-
- if cts_read = '1' and cts_dataready = '1' then
- EvLength_TX_cntr := EvLength_TX_cntr - 1;
- cts_dataready <= '0';
- end if;
-
- if EvLength_TX_cntr = 0 then
- pckr_TX_state <= FINISH;
- cts_dataready <= '0';
- end if;
- end if;
- DEBUG_EvtLength <= EvLength_TX_cntr;
- FSM_state_TX <= x"00000002";
-
- when FINISH =>
- cts_finished <= '1';
- pckr_TX_state <= EVNT;
- FSM_state_TX <= x"00000003";
-
- when others =>
- FSM_state_TX <= x"00000004";
- end case;
+ if Header_ready = '1' then
+ DEBUG_read_enable_fifo_vnt <= std_logic_vector(unsigned(DEBUG_read_enable_fifo_vnt) + 1);
+ cts_dataready <= '1';
+ if cts_read = '1' and cts_dataready = '1' then
+ pckr_TX_state <= DATA;
+ cts_dataready <= '0';
+ Header_ready := '0';
+ end if;
+ end if;
+ FSM_state_TX <= x"00000001";
+ end if;
+
+ when DATA =>
+
+ if pckr_TX_data_type = x"3" or pckr_TX_data_type = x"4" or pckr_TX_data_type = x"5" then
+ if dataready = '1' then
+ cts_data <= pckr_TX_data;
+ cts_dataready <= '1';
+ end if;
+
+ if cts_read = '1' and cts_dataready = '1' then
+ EvLength_TX_cntr := EvLength_TX_cntr - 1;
+ cts_dataready <= '0';
+ end if;
+
+ if EvLength_TX_cntr = 0 then
+ pckr_TX_state <= FINISH;
+ cts_dataready <= '0';
+ end if;
+ end if;
+ DEBUG_EvtLength <= EvLength_TX_cntr;
+ FSM_state_TX <= x"00000002";
+
+ when FINISH =>
+ cts_finished <= '1';
+ pckr_TX_state <= EVNT;
+ FSM_state_TX <= x"00000003";
+
+ when others =>
+ FSM_state_TX <= x"00000004";
+ end case;
- DEBUG_enable_fifo_rdEn <= enable_fifo_rdEn;
- DEBUG_cts_dataready <= dataready;
- end if;
- end process;
+ DEBUG_enable_fifo_rdEn <= enable_fifo_rdEn;
+ DEBUG_cts_dataready <= dataready;
+ end if;
+ end process;
STAT_DEBUG => open
);
- THE_DEBUG : process begin
- wait until rising_edge(clk_sys);
- busdebug_tx.ack <= '0';
- busdebug_tx.nack <= '0';
- busdebug_tx.unknown <= '0';
-
- if busdebug_rx.read = '1' then
- if busdebug_rx.addr(7 downto 0) = x"00" then
- busdebug_tx.data <= FSM_state_RX;
- end if;
- if busdebug_rx.addr(7 downto 0) = x"01" then
- busdebug_tx.data <= FSM_state_TX;
- end if;
- if busdebug_rx.addr(7 downto 0) = x"02" then
- busdebug_tx.data(0) <= pckr_fifo_empty;
- busdebug_tx.data(3 downto 1) <= (others => '0');
- busdebug_tx.data(4) <= pckr_fifo_full;
- busdebug_tx.data(15 downto 5) <= (others => '0');
- busdebug_tx.data(31 downto 16) <= WCNT_i;
- end if;
- if busdebug_rx.addr(7 downto 0) = x"03" then
- busdebug_tx.data <= fifo_data_out(31 DOWNTO 0);
- end if;
- if busdebug_rx.addr( 7 downto 0) = x"04" then
- busdebug_tx.data(0) <= fee_dataready;
- busdebug_tx.data( 3 downto 1) <= (others => '0');
- busdebug_tx.data(4) <= fee_read;
- busdebug_tx.data( 7 downto 5) <= (others => '0');
- busdebug_tx.data(8) <= fee_busy;
- busdebug_tx.data(11 downto 9) <= (others => '0');
- busdebug_tx.data(12) <= cts_start_readout;
- busdebug_tx.data(15 downto 13) <= (others => '0');
- busdebug_tx.data(31 downto 16) <= fee_data;
- end if;
- if busdebug_rx.addr( 7 downto 0) = x"05" then
- busdebug_tx.data <= pckr_Data;
- end if;
- if busdebug_rx.addr( 7 downto 0) = x"06" then
- busdebug_tx.data( 3 downto 0) <= pckr_Data_type;
- busdebug_tx.data(31 downto 4) <= (others => '0');
- end if;
- if busdebug_rx.addr( 7 downto 0) = x"07" then
- busdebug_tx.data(15 downto 0) <= std_logic_vector(DEBUG_EvtLength);
- busdebug_tx.data(31 downto 16) <= (others => '0');
- end if;
- if busdebug_rx.addr( 7 downto 0) = x"08" then
- busdebug_tx.data <= std_logic_vector(DEBUG_cts_read);
- end if;
- if busdebug_rx.addr( 7 downto 0) = x"09" then
- busdebug_tx.data(0) <= DEBUG_enable_fifo_rdEn;
- busdebug_tx.data(1) <= DEBUG_cts_dataready;
- busdebug_tx.data(31 downto 2) <= (others => '0');
- end if;
- if busdebug_rx.addr( 7 downto 0) = x"0A" then
- busdebug_tx.data(15 downto 0) <= pckr_Data_Length_Ev;
- busdebug_tx.data(31 downto 16) <= (others => '0');
- end if;
- if busdebug_rx.addr( 7 downto 0) = x"0B" then
- busdebug_tx.data(15 downto 0) <= pckr_Data_Source;
- busdebug_tx.data(31 downto 16) <= (others => '0');
- end if;
- if busdebug_rx.addr( 7 downto 0) = x"0C" then
- busdebug_tx.data( 0) <= MUX_cal_sw;
- busdebug_tx.data(31 downto 1) <= (others => '0');
- end if;
- if busdebug_rx.addr( 7 downto 0) = x"0D" then
- busdebug_tx.data(23 downto 0) <= DEBUG_read_enable_fifo_vnt(23 downto 0);
- busdebug_tx.data(24) <= cts_dataready;
- busdebug_tx.data(27 downto 25) <= (others => '0');
- busdebug_tx.data(28) <= already_asked;
- busdebug_tx.data(31 downto 29) <= (others => '0');
- end if;
- if busdebug_rx.addr( 7 downto 0) = x"0E" then
- busdebug_tx.data <= cts_data;
- end if;
- if busdebug_rx.addr( 7 downto 0) = x"0F" then
- busdebug_tx.data(15 downto 0) <= cts_length;
- busdebug_tx.data(31 downto 15) <= (others => '0');
- end if;
-
- if busdebug_rx.addr( 7 downto 0) = x"10" then
- busdebug_tx.data(30 downto 0) <= DEBUG_read_enable_fifo_cnt(30 downto 0);
- busdebug_tx.data(31) <= rd_enabled;
- end if;
- if busdebug_rx.addr( 7 downto 0) = x"11" then
- busdebug_tx.data(30 downto 0) <= DEBUG_read_enable_fifo_vnt1(30 downto 0);
- busdebug_tx.data(31) <= cts_read;
- end if;
- if busdebug_rx.addr( 7 downto 0) = x"12" then
- busdebug_tx.data <= DEBUG_read_enable_fifo_cnt2;
- end if;
-
- if busdebug_rx.addr( 7 downto 0) = x"13" then
- busdebug_tx.data(15 downto 0) <= FPGA;
- busdebug_tx.data(31 downto 16) <= (others => '0');
- end if;
-
- busdebug_tx.ack <= '1';
- elsif busdebug_rx.write = '1' then
- --additional_reg_i <= busdebug_rx.data(additional_reg_i'left downto 0);
- if busdebug_rx.addr( 7 downto 0) = x"0C" then
- MUX_cal_sw <= busdebug_rx.data(0);
- end if;
- busdebug_tx.ack <= '1';
- end if;
- end process;
+ THE_DEBUG : process begin
+ wait until rising_edge(clk_sys);
+ busdebug_tx.ack <= '0';
+ busdebug_tx.nack <= '0';
+ busdebug_tx.unknown <= '0';
+
+ if busdebug_rx.read = '1' then
+ if busdebug_rx.addr(7 downto 0) = x"00" then
+ busdebug_tx.data <= FSM_state_RX;
+ end if;
+ if busdebug_rx.addr(7 downto 0) = x"01" then
+ busdebug_tx.data <= FSM_state_TX;
+ end if;
+ if busdebug_rx.addr(7 downto 0) = x"02" then
+ busdebug_tx.data(0) <= pckr_fifo_empty;
+ busdebug_tx.data(3 downto 1) <= (others => '0');
+ busdebug_tx.data(4) <= pckr_fifo_full;
+ busdebug_tx.data(15 downto 5) <= (others => '0');
+ busdebug_tx.data(31 downto 16) <= WCNT_i;
+ end if;
+ if busdebug_rx.addr(7 downto 0) = x"03" then
+ busdebug_tx.data <= fifo_data_out(31 DOWNTO 0);
+ end if;
+ if busdebug_rx.addr( 7 downto 0) = x"04" then
+ busdebug_tx.data(0) <= fee_dataready;
+ busdebug_tx.data( 3 downto 1) <= (others => '0');
+ busdebug_tx.data(4) <= fee_read;
+ busdebug_tx.data( 7 downto 5) <= (others => '0');
+ busdebug_tx.data(8) <= fee_busy;
+ busdebug_tx.data(11 downto 9) <= (others => '0');
+ busdebug_tx.data(12) <= cts_start_readout;
+ busdebug_tx.data(15 downto 13) <= (others => '0');
+ busdebug_tx.data(31 downto 16) <= fee_data;
+ end if;
+ if busdebug_rx.addr( 7 downto 0) = x"05" then
+ busdebug_tx.data <= pckr_Data;
+ end if;
+ if busdebug_rx.addr( 7 downto 0) = x"06" then
+ busdebug_tx.data( 3 downto 0) <= pckr_Data_type;
+ busdebug_tx.data(31 downto 4) <= (others => '0');
+ end if;
+ if busdebug_rx.addr( 7 downto 0) = x"07" then
+ busdebug_tx.data(15 downto 0) <= std_logic_vector(DEBUG_EvtLength);
+ busdebug_tx.data(31 downto 16) <= (others => '0');
+ end if;
+ if busdebug_rx.addr( 7 downto 0) = x"08" then
+ busdebug_tx.data <= std_logic_vector(DEBUG_cts_read);
+ end if;
+ if busdebug_rx.addr( 7 downto 0) = x"09" then
+ busdebug_tx.data(0) <= DEBUG_enable_fifo_rdEn;
+ busdebug_tx.data(1) <= DEBUG_cts_dataready;
+ busdebug_tx.data(31 downto 2) <= (others => '0');
+ end if;
+ if busdebug_rx.addr( 7 downto 0) = x"0A" then
+ busdebug_tx.data(15 downto 0) <= pckr_Data_Length_Ev;
+ busdebug_tx.data(31 downto 16) <= (others => '0');
+ end if;
+ if busdebug_rx.addr( 7 downto 0) = x"0B" then
+ busdebug_tx.data(15 downto 0) <= pckr_Data_Source;
+ busdebug_tx.data(31 downto 16) <= (others => '0');
+ end if;
+ if busdebug_rx.addr( 7 downto 0) = x"0C" then
+ busdebug_tx.data( 0) <= MUX_cal_sw;
+ busdebug_tx.data(31 downto 1) <= (others => '0');
+ end if;
+ if busdebug_rx.addr( 7 downto 0) = x"0D" then
+ busdebug_tx.data(23 downto 0) <= DEBUG_read_enable_fifo_vnt(23 downto 0);
+ busdebug_tx.data(24) <= cts_dataready;
+ busdebug_tx.data(27 downto 25) <= (others => '0');
+ busdebug_tx.data(28) <= already_asked;
+ busdebug_tx.data(31 downto 29) <= (others => '0');
+ end if;
+ if busdebug_rx.addr( 7 downto 0) = x"0E" then
+ busdebug_tx.data <= cts_data;
+ end if;
+ if busdebug_rx.addr( 7 downto 0) = x"0F" then
+ busdebug_tx.data(15 downto 0) <= cts_length;
+ busdebug_tx.data(31 downto 15) <= (others => '0');
+ end if;
+
+ if busdebug_rx.addr( 7 downto 0) = x"10" then
+ busdebug_tx.data(30 downto 0) <= DEBUG_read_enable_fifo_cnt(30 downto 0);
+ busdebug_tx.data(31) <= rd_enabled;
+ end if;
+ if busdebug_rx.addr( 7 downto 0) = x"11" then
+ busdebug_tx.data(30 downto 0) <= DEBUG_read_enable_fifo_vnt1(30 downto 0);
+ busdebug_tx.data(31) <= cts_read;
+ end if;
+ if busdebug_rx.addr( 7 downto 0) = x"12" then
+ busdebug_tx.data <= DEBUG_read_enable_fifo_cnt2;
+ end if;
+
+ if busdebug_rx.addr( 7 downto 0) = x"13" then
+ busdebug_tx.data(15 downto 0) <= FPGA;
+ busdebug_tx.data(31 downto 16) <= (others => '0');
+ end if;
+
+ busdebug_tx.ack <= '1';
+ elsif busdebug_rx.write = '1' then
+ --additional_reg_i <= busdebug_rx.data(additional_reg_i'left downto 0);
+ if busdebug_rx.addr( 7 downto 0) = x"0C" then
+ MUX_cal_sw <= busdebug_rx.data(0);
+ end if;
+ busdebug_tx.ack <= '1';
+ end if;
+ end process;
handlerbus_rx <= ctrlbus_rx when bus_master_active = '0' else bus_master_out;
jspc29 / dirich.git / commitdiff