);
port(
CLK : in std_logic;
- RESET : in std_logic;
+ RESET : in std_logic;
+ API_RESET : in std_logic;
CLK_EN : in std_logic;
-
+
--LVDS
LVDS_IN : in std_logic_vector(15 downto 0);
LVDS_OUT : out std_logic_vector(15 downto 0);
-
+
-- APL Transmitter port
APL_DATA_IN: in STD_LOGIC_VECTOR (47 downto 0); -- Data word "application to network"
APL_WRITE_IN: in STD_LOGIC; -- Data word is valid and should be transmitted
APL_TYP_OUT: out STD_LOGIC_VECTOR (2 downto 0); -- Which kind of data word: DAT, HDR or TRM
APL_DATAREADY_OUT: out STD_LOGIC; -- Data word is valid and might be read out
APL_READ_IN: in STD_LOGIC; -- Read data word
-
+
-- APL Control port
APL_RUN_OUT: out STD_LOGIC; -- Data transfer is running
APL_MY_ADDRESS_IN: in STD_LOGIC_VECTOR (15 downto 0); -- My own address (temporary solution!!!)
APL_SEQNR_OUT: out STD_LOGIC_VECTOR (7 downto 0);
-
-
+
-- Status and Control registers
API_STAT_GEN: out std_logic_vector(31 downto 0);
API_STAT_LOCKED: out std_logic_vector(31 downto 0);
API_STAT_INIT_BUFFER: out std_logic_vector(31 downto 0);
API_STAT_REPLY_BUFFER: out std_logic_vector(31 downto 0);
+ API_STAT_FIFO_TO_INT: out std_logic_vector(31 downto 0);
+ API_STAT_FIFO_TO_APL: out std_logic_vector(31 downto 0);
LVDS_STAT: out std_logic_vector(31 downto 0);
LVDS_CTRL: in std_logic_vector(31 downto 0);
MPLEX_CTRL: in std_logic_vector(31 downto 0)
CTRL_LOCKED: in STD_LOGIC_VECTOR (31 downto 0);
STAT_CTRL_INIT_BUFFER: in STD_LOGIC_VECTOR (31 downto 0);
STAT_CTRL_REPLY_BUFFER: in STD_LOGIC_VECTOR (31 downto 0);
- MPLEX_CTRL: in STD_LOGIC_VECTOR (31 downto 0)
+ MPLEX_CTRL: in STD_LOGIC_VECTOR (31 downto 0);
+ API_STAT_FIFO_TO_INT: out std_logic_vector(31 downto 0);
+ API_STAT_FIFO_TO_APL: out std_logic_vector(31 downto 0)
);
end component;
CTRL_LOCKED: in STD_LOGIC_VECTOR (31 downto 0);
STAT_CTRL_INIT_BUFFER: in STD_LOGIC_VECTOR (31 downto 0);
STAT_CTRL_REPLY_BUFFER: in STD_LOGIC_VECTOR (31 downto 0);
- MPLEX_CTRL: in STD_LOGIC_VECTOR (31 downto 0)
+ MPLEX_CTRL: in STD_LOGIC_VECTOR (31 downto 0);
+ API_STAT_FIFO_TO_INT: out std_logic_vector(31 downto 0);
+ API_STAT_FIFO_TO_APL: out std_logic_vector(31 downto 0)
);
end component;
signal API_MED_READ_OUT : std_logic;
signal API_MED_ERROR_OUT : std_logic_vector(2 downto 0);
signal API_ctrl : std_logic_vector(31 downto 0);
-
+ --signal API_STAT_FIFO_TO_INT, API_STAT_FIFO_TO_APL : std_logic_vector(31 downto 0);
signal C5518_D55_DATA_IN, C5518_D55_DATA_OUT : std_logic_vector(55 downto 0);
-----------------------------------------------------------------------
CTRL => LVDS_CTRL
);
- LVDS_OUT(12 downto 0) <= LVDS_MED_DATA_OUT;
+ LVDS_OUT(10 downto 0) <= LVDS_MED_DATA_OUT(10 downto 0);
+ LVDS_OUT(11) <= LVDS_MED_DATA_OUT(11) and not API_RESET;
+ LVDS_OUT(12) <= LVDS_MED_DATA_OUT(12);
LVDS_OUT(13) <= LVDS_MED_TRANSMISSION_CLK_OUT;
LVDS_OUT(14) <= LVDS_MED_CARRIER_OUT;
LVDS_OUT(15) <= LVDS_MED_PARITY_OUT;
LVDS_MED_DATA_IN <= LVDS_IN(12 downto 0);
LVDS_MED_TRANSMISSION_CLK_IN <= LVDS_IN(13);
LVDS_MED_CARRIER_IN <= LVDS_IN(14);
- LVDS_MED_PARITY_IN <= LVDS_IN(13);
+ LVDS_MED_PARITY_IN <= LVDS_IN(15);
-----------------------------------------------------------------------
port map(
-- Misc
CLK => CLK,
- RESET => RESET,
+ RESET => API_RESET,
CLK_EN => CLK_EN,
D55_DATA_IN => C5518_D55_DATA_IN,
FIFO_TERM_BUFFER_DEPTH => 3)
port map (
CLK => CLK,
- RESET => RESET,
+ RESET => API_RESET,
CLK_EN => CLK_EN,
-- APL Transmitter port
APL_DATA_IN => APL_DATA_IN,
APL_READ_IN => APL_READ_IN,
-- APL Control port
APL_RUN_OUT => APL_RUN_OUT,
- APL_SEQNR_OUT => APL_SEQNR_OUT,
APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN,
+ APL_SEQNR_OUT => APL_SEQNR_OUT,
-- Media direction
MED_DATAREADY_OUT => API_MED_DATAREADY_OUT,
MED_DATA_OUT => API_MED_DATA_OUT,
STAT_CTRL_INIT_BUFFER => (others => '0'),
STAT_CTRL_REPLY_BUFFER => (others => '0'),
- MPLEX_CTRL => MPLEX_CTRL
+ MPLEX_CTRL => MPLEX_CTRL,
+ API_STAT_FIFO_TO_INT => API_STAT_FIFO_TO_INT,
+ API_STAT_FIFO_TO_APL => API_STAT_FIFO_TO_APL
);
end generate;
FIFO_TERM_BUFFER_DEPTH => 3)
port map (
CLK => CLK,
- RESET => RESET,
+ RESET => API_RESET,
CLK_EN => CLK_EN,
-- APL Transmitter port
APL_DATA_IN => APL_DATA_IN,
STAT_REPLY_BUFFER => API_STAT_REPLY_BUFFER,
STAT_CTRL_INIT_BUFFER => (others => '0'),
STAT_CTRL_REPLY_BUFFER => (others => '0'),
- MPLEX_CTRL => MPLEX_CTRL
+ MPLEX_CTRL => MPLEX_CTRL,
+ API_STAT_FIFO_TO_INT => API_STAT_FIFO_TO_INT,
+ API_STAT_FIFO_TO_APL => API_STAT_FIFO_TO_APL
);
end generate;
WIDTH : integer := 8; -- FIFO word width
DEPTH : integer := 4); -- Depth of the FIFO, 2^(n+1)
port (
- CLK : in std_logic;
- RESET : in std_logic;
+ CLK : in std_logic;
+ RESET : in std_logic;
CLK_EN : in std_logic;
DATA_IN : in std_logic_vector(WIDTH - 1 downto 0); -- Input data
- WRITE_ENABLE_IN : in std_logic;
+ WRITE_ENABLE_IN : in std_logic;
DATA_OUT : out std_logic_vector(WIDTH - 1 downto 0); -- Output data
READ_ENABLE_IN : in std_logic;
FULL_OUT : out std_logic; -- Full Flag
component trb_net_dummy_fifo is
generic (WIDTH : integer := 8); -- Depth of the FIFO, 2^(n+1)
port (
- CLK : in std_logic;
- RESET : in std_logic;
+ CLK : in std_logic;
+ RESET : in std_logic;
CLK_EN : in std_logic;
DATA_IN : in std_logic_vector(WIDTH - 1 downto 0); -- Input data
- WRITE_ENABLE_IN : in std_logic;
+ WRITE_ENABLE_IN : in std_logic;
DATA_OUT : out std_logic_vector(WIDTH - 1 downto 0); -- Output data
READ_ENABLE_IN : in std_logic;
FULL_OUT : out std_logic; -- Full Flag
EMPTY_OUT : out std_logic;
DEPTH_OUT : out std_logic_vector(7 downto 0)
- );
+ );
end component;
component trb_net_sbuf is
VERSION: integer := 1);
port(
-- Misc
- CLK : in std_logic;
- RESET : in std_logic;
+ CLK : in std_logic;
+ RESET : in std_logic;
CLK_EN : in std_logic;
-- port to combinatorial logic
COMB_DATAREADY_IN: in STD_LOGIC; --comb logic provides data word
-- path, if set to 0 no buffer is used at all
port(
-- Misc
- CLK : in std_logic;
- RESET : in std_logic;
+ CLK : in std_logic;
+ RESET : in std_logic;
CLK_EN : in std_logic;
-- Internal direction port
-- termination for active api
---------------------------------------
- gen_term: if API_TYPE = 1 generate
+-- gen_term: if API_TYPE = 1 generate
TrbNetTerm: trb_net_term
generic map(FIFO_TERM_BUFFER_DEPTH => 0)
port map(
APL_ERROR_PATTERN_IN => (others => '0'),
APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN
);
- end generate;
+-- end generate;
-- gen_noterm: if API_TYPE = 0 generate
-- INT_SLAVE_READ_OUT <= '0';
STAT_FIFO_TO_INT(15) <= fifo_to_int_empty;
STAT_FIFO_TO_INT(7 downto 4) <= (others => '0');
STAT_FIFO_TO_INT(13 downto 12) <= (others => '0');
- STAT_FIFO_TO_INT(31 downto 16) <= (others => '0');
-
+ STAT_FIFO_TO_INT(28 downto 16) <= (others => '0');
+ STAT_FIFO_TO_INT(31 downto 29) <= state_bits;
---------------------------------------
-- fifo to apl
---------------------------------------
STAT_FIFO_TO_APL(2 downto 0) <= fifo_to_apl_data_in(2 downto 0);
STAT_FIFO_TO_APL(3) <= fifo_to_apl_write;
- STAT_FIFO_TO_APL(10 downto 8) <= fifo_to_apl_data_out(2 downto 0);
+ STAT_FIFO_TO_APL(9 downto 8) <= fifo_to_apl_data_out(1 downto 0);
STAT_FIFO_TO_APL(11) <= fifo_to_apl_read;
STAT_FIFO_TO_APL(14) <= fifo_to_apl_full;
STAT_FIFO_TO_APL(15) <= fifo_to_apl_empty;
STAT_FIFO_TO_APL(7 downto 4) <= (others => '0');
- STAT_FIFO_TO_APL(13 downto 12) <= (others => '0');
+ --STAT_FIFO_TO_APL(13 downto 12) <= (others => '0');
STAT_FIFO_TO_APL(31 downto 16) <= (others => '0');
-
-
+ STAT_FIFO_TO_APL(13) <= reg_INT_SLAVE_READ_OUT;
+ STAT_FIFO_TO_APL(12) <= INT_SLAVE_DATAREADY_IN;
+ STAT_FIFO_TO_APL(10) <= reg_APL_DATAREADY_OUT;
+
---------------------------------------
-- a sbuf on the active channel
---------------------------------------
if reg_INT_SLAVE_READ_OUT = '1' and INT_SLAVE_DATAREADY_IN = '1' then
fifo_to_apl_write <= '1'; -- use fifo as the pipe
end if;
-
+
-- part 2: connection to apl
- if (fifo_to_apl_empty = '0') then
+-- if fifo_to_apl_empty = '0' then
+ if fifo_to_apl_empty = '0' and reg_APL_DATAREADY_OUT = '0' then --is this really correct????
next_APL_DATAREADY_OUT <= '1';
end if; -- read/no read
if reg_APL_DATAREADY_OUT = '1' and APL_READ_IN = '1' then
-- valid read
fifo_to_apl_read <= '1';
- if reg_APL_TYP_OUT = TYPE_TRM or reg_APL_TYP_OUT = TYPE_HDR then
+ if (reg_APL_TYP_OUT = TYPE_TRM or reg_APL_TYP_OUT = TYPE_HDR) then
next_slave_running <= '1';
end if;
- if reg_APL_TYP_OUT = TYPE_TRM and (fifo_to_apl_read = '1' and reg_APL_DATAREADY_OUT = '1') then
+ if reg_APL_TYP_OUT = TYPE_TRM and (APL_READ_IN = '1' and reg_APL_DATAREADY_OUT = '1') then --fifo_to_apl_read = '1'
next_state <= IDLE;
end if;
end if;
fifo_to_int_write <= (APL_WRITE_IN and not fifo_to_int_full) when (current_state = IDLE or
current_state = SEND_HEADER or
current_state = RUNNING)
+
else '0';
+
+
APL_FIFO_FULL_OUT <= fifo_to_int_full; -- APL has to stop writing
INT_SLAVE_READ_OUT <= reg_INT_SLAVE_READ_OUT;
-
+ process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ reg_APL_DATAREADY_OUT <= '0';
+ reg_APL_DATA_OUT <= (others => '0');
+ reg_APL_TYP_OUT <= (others => '0');
+ else
+ reg_APL_DATAREADY_OUT <= next_APL_DATAREADY_OUT;
+ reg_APL_DATA_OUT <= next_APL_DATA_OUT;
+ reg_APL_TYP_OUT <= next_APL_TYP_OUT;
+ end if;
+ end if;
+ end process;
+
+
-- connect receiver
fifo_to_apl_data_in <= INT_SLAVE_DATA_IN;
- reg_APL_DATAREADY_OUT <= next_APL_DATAREADY_OUT;
- reg_APL_DATA_OUT <= next_APL_DATA_OUT;
- reg_APL_TYP_OUT <= next_APL_TYP_OUT;
+-- reg_APL_DATAREADY_OUT <= next_APL_DATAREADY_OUT;
+-- reg_APL_DATA_OUT <= next_APL_DATA_OUT;
+-- reg_APL_TYP_OUT <= next_APL_TYP_OUT;
APL_DATAREADY_OUT <= reg_APL_DATAREADY_OUT;
APL_DATA_OUT <= reg_APL_DATA_OUT;
APL_TYP_OUT <= reg_APL_TYP_OUT;
-------------------------------------------------
--format on LVDS: 0-7 Data
--- 8-11 free
+-- 8-10 free
+-- 11 "handshake"
-- 12 first packet indicator
-- 13 transmission clock
-- 14 carrier
-- 15 parity(0-7)
-------------------------------------------------
+-- "handshake": if this is low, you can not send, if it goes down during a transfer,
+-- then probably some data is lost
+
--Please check the timing report for setup/hold-errors on the receiving ports
--In case of an error, adjust the PHASE_SHIFT of the DCM. A change of one unit
--results in a shift of (CLK_PERIOD/256)
entity trb_net_med_8bit_fast is
port(
-- Misc
- CLK : in std_logic;
- RESET : in std_logic;
+ CLK : in std_logic;
+ RESET : in std_logic;
CLK_EN : in std_logic;
-- 1st part: from the medium to the internal logic (trbnet)
signal sbuff_next_read_out : std_logic;
signal buf_comb_data_in : std_logic_vector(17 downto 0);
-signal DCM_LOCKED, RESET_RECV : std_logic;
+signal DCM_LOCKED, RESET_RECV, next_RESET_RECV : std_logic;
begin
-----------------------------------------------------------------------
port map(
-- Misc
CLK => CLK,
- RESET => RESET,
+ RESET => RESET_RECV,
CLK_EN => CLK_EN,
D18_DATAREADY_IN => INT_DATAREADY_IN,
PSCLK => '0',
RST => RESET,
CLK0 => CLK_FB_Out, -- for feedback
- CLK180=> CLK_RECV_Out,
+ CLK180=> CLK_RECV_Out,
LOCKED => DCM_LOCKED
);
--
if RESET_RECV = '1' then
fifo_write_enable <= '0';
fifo_data_in(15 downto 0) <= (others => '0');
+ fifo_data_in(17) <= '0';
elsif rising_edge(CLK_TRANS) then
fifo_write_enable <= next_fifo_write_enable;
fifo_data_in <= next_fifo_data_in;
begin
if RESET_RECV = '1' then
buf_MED_IN_fal(15 downto 0) <= (others => '0');
- elsif falling_edge(CLK_TRANS) then
+ elsif falling_edge(CLK_TRANS) and MED_CARRIER_IN = '1' then
buf_MED_IN_fal(14) <= MED_CARRIER_IN;
buf_MED_IN_fal(15) <= MED_PARITY_IN;
buf_MED_IN_fal(13) <= '1';
end if;
end process;
- process(CLK,RESET)
+ process(CLK,RESET_RECV)
begin
- if RESET = '1' then
+ if RESET_RECV = '1' then
last_fifo_read_enable <= '0';
buf_int_error_out <= ERROR_NC;
- buf_int_packet_nr_out <= "00";
+ buf_int_packet_nr_out <= "11";
elsif rising_edge(CLK) then
last_fifo_read_enable <= fifo_read_enable;
buf_int_error_out <= next_int_error_out;
generic map(DATA_WIDTH => 18, VERSION => 0)
port map (
CLK => CLK,
- RESET => RESET,
+ RESET => RESET_RECV,
CLK_EN => CLK_EN,
COMB_DATAREADY_IN => last_fifo_read_enable,
COMB_next_READ_OUT => sbuff_next_read_out,
-----------------------------------------------------------------------
CONV_READ_IN <= DCM_LOCKED;
-RESET_RECV <= RESET or not DCM_LOCKED;
+--RESET_RECV <= RESET or not DCM_LOCKED or not MED_DATA_IN(11);
+
+ process(RESET,DCM_LOCKED,MED_DATA_IN(11))
+ begin
+ if DCM_LOCKED = '0' or not MED_DATA_IN(11) = '1' then
+ next_RESET_RECV <= '1';
+ else
+ next_RESET_RECV <= '0';
+ end if;
+ end process;
+
+ process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ RESET_RECV <= '1';
+ else
+ RESET_RECV <= next_RESET_RECV;
+ end if;
+ end if;
+ end process;
process(CONV_DATAREADY_OUT, CONV_DATA_OUT, CONV_PACKET_NR_OUT, CONV_READ_IN,
end if;
end process;
- process(CLK, RESET)
+ process(CLK, RESET_RECV)
begin
- if RESET = '1' then
+ if RESET_RECV = '1' then
send_data_byte1 <= (others => '0');
send_data_byte2 <= (others => '0');
send_data_byte1_parity <= '0';
PRE => '0'
);
- process(CLK, RESET)
+ process(CLK, RESET_RECV)
begin
- if RESET = '1' then
+ if RESET_RECV = '1' then
buf_MED_DATA_OUT(12) <= '0';
buf_MED_CARRIER_OUT <= '0';
elsif falling_edge(CLK) then
MED_PARITY_OUT <= buf_MED_PARITY_OUT;
MED_CARRIER_OUT <= buf_MED_CARRIER_OUT;
MED_TRANSMISSION_CLK_OUT <= buf_MED_TRANSMISSION_CLK_OUT;
-MED_DATA_OUT(9 downto 0) <= buf_MED_DATA_OUT(9 downto 0);
+MED_DATA_OUT(8 downto 0) <= buf_MED_DATA_OUT(8 downto 0);
+MED_DATA_OUT(9) <= RESET_RECV;
MED_DATA_OUT(12) <= buf_MED_DATA_OUT(12);
--MED_DATA_OUT(8) <= '0';
--MED_DATA_OUT(9) <= CLK_TRANS;
--MED_DATA_OUT(8) <= buf_MED_TRANSMISSION_CLK_IN;
MED_DATA_OUT(10) <= fifo_data_in(0);
-MED_DATA_OUT(11) <= fifo_data_in(17);
+MED_DATA_OUT(11) <= (DCM_LOCKED);-- or (fifo_data_in(17) and not RESET_RECV);
-- MED_DATA_OUT(10) <= CLK_TRANS;
-- MED_DATA_OUT(11) <= fifo_write_enable;
-- Status and control port
STAT_BUFFER: out STD_LOGIC
);
-END trb_net_sbuf;
+end trb_net_sbuf;
architecture trb_net_sbuf_arch of trb_net_sbuf is
jspc29 / trbnet.git / commitdiff