-- Fifo Delay
signal fifo_delay : std_logic_vector(7 downto 0);
signal fifo_delay_reset : std_logic;
+
+ -- Frame Rate Counter
+ signal rate_timer : unsigned(27 downto 0);
+ signal frame_rate_in_ctr_t : unsigned(27 downto 0);
+ signal frame_rate_out_ctr_t : unsigned(27 downto 0);
+ signal frame_rate_input : unsigned(27 downto 0);
+ signal frame_rate_output : unsigned(27 downto 0);
+
+ -- Error Status
+ signal data_clk_shift : std_logic_vector(3 downto 0);
+ signal frame_dt_error : std_logic;
+ signal frame_dt_error_ctr : unsigned(15 downto 0);
+ signal frame_rate_error : std_logic;
+
+ signal data_clk_out_shift : std_logic_vector(3 downto 0);
+ signal frame_dt_out_error : std_logic;
+ signal frame_dt_out_error_ctr : unsigned(15 downto 0);
+ signal frame_rate_out_error : std_logic;
+
+ signal error_o : std_logic;
-- Slave Bus
signal slv_data_o : std_logic_vector(31 downto 0);
end if;
end if;
end process PROC_FIFO_DELAY;
+
+ PROC_CAL_RATES: process (CLK_IN)
+ begin
+ if( rising_edge(CLK_IN) ) then
+ if (RESET_IN = '1') then
+ rate_timer <= (others => '0');
+ frame_rate_input <= (others => '0');
+ frame_rate_output <= (others => '0');
+ frame_rate_in_ctr_t <= (others => '0');
+ frame_rate_out_ctr_t <= (others => '0');
+ else
+ if (rate_timer < x"5f5e100") then
+ if (DATA_CLK_IN = '1') then
+ frame_rate_in_ctr_t <= frame_rate_in_ctr_t + 1;
+ end if;
+ if (data_clk_o = '1') then
+ frame_rate_out_ctr_t <= frame_rate_out_ctr_t + 1;
+ end if;
+ rate_timer <= rate_timer + 1;
+ else
+ frame_rate_input <= frame_rate_in_ctr_t;
+ frame_rate_in_ctr_t(27 downto 1) <= (others => '0');
+ frame_rate_in_ctr_t(0) <= DATA_CLK_IN;
+
+ frame_rate_output <= frame_rate_out_ctr_t;
+ frame_rate_out_ctr_t(27 downto 1) <= (others => '0');
+ frame_rate_out_ctr_t(0) <= data_clk_o;
+
+ rate_timer <= (others => '0');
+ end if;
+ end if;
+ end if;
+ end process PROC_CAL_RATES;
+
+ PROC_DATA_STREAM_DELTA_T: process(CLK_IN)
+ begin
+ if (rising_edge(CLK_IN)) then
+ if (RESET_IN = '1') then
+ data_clk_shift <= (others => '0');
+ frame_dt_error_ctr <= (others => '0');
+ frame_dt_error <= '0';
+ data_clk_out_shift <= (others => '0');
+ frame_dt_out_error_ctr <= (others => '0');
+ frame_dt_out_error <= '0';
+ else
+ -- Frame
+ data_clk_shift(0) <= DATA_CLK_IN;
+ data_clk_shift(3 downto 1) <= data_clk_shift(2 downto 0);
+
+ data_clk_out_shift(0) <= data_clk_o;
+ data_clk_out_shift(3 downto 1) <= data_clk_out_shift(2 downto 0);
+
+ case data_clk_shift is
+ when "1100" | "1110" | "1111" | "0000" =>
+ frame_dt_error_ctr <= frame_dt_error_ctr + 1;
+ frame_dt_error <= '1';
+
+ when others =>
+ frame_dt_error <= '0';
+
+ end case;
+
+ case data_clk_out_shift is
+ when "1100" | "1110" | "1111" | "0000" =>
+ frame_dt_out_error_ctr <= frame_dt_out_error_ctr + 1;
+ frame_dt_out_error <= '1';
+
+ when others =>
+ frame_dt_out_error <= '0';
+
+ end case;
+
+ end if;
+ end if;
+ end process PROC_DATA_STREAM_DELTA_T;
-----------------------------------------------------------------------------
-- TRBNet Slave Bus
slv_ack_o <= '1';
when x"0001" =>
+ slv_data_o(27 downto 0) <= frame_rate_input;
+ slv_data_o(31 downto 28) <= (others => '0');
+ slv_ack_o <= '1';
+
+ when x"0002" =>
+ slv_data_o(27 downto 0) <= frame_rate_output;
+ slv_data_o(31 downto 28) <= (others => '0');
+ slv_ack_o <= '1';
+
+ when x"0003" =>
+ slv_data_o(15 downto 0) <= frame_dt_error_ctr;
+ slv_data_o(31 downto 16) <= (others => '0');
+ slv_ack_o <= '1';
+
+ when x"0004" =>
+ slv_data_o(15 downto 0) <= frame_dt_out_error_ctr;
+ slv_data_o(31 downto 16) <= (others => '0');
+ slv_ack_o <= '1';
+
+ when x"0005" =>
slv_data_o(0) <= debug_r;
slv_data_o(31 downto 1) <= (others => '0');
slv_ack_o <= '1';
fifo_reset_r <= '1';
slv_ack_o <= '1';
- when x"0001" =>
+ when x"0005" =>
debug_r <= SLV_DATA_IN(0);
slv_ack_o <= '1';
signal adc_data_s : std_logic_vector(11 downto 0);
signal adc_data_s_clk : std_logic;
- signal adc_notlock_ctr : unsigned(7 downto 0);
+ signal adc_notlock_ctr : unsigned(11 downto 0);
signal ADC_DEBUG : std_logic_vector(15 downto 0);
-- Merge Data Streams
signal nx_frame_word_delay_r : unsigned(1 downto 0);
signal adc_dt_error_ctr_r : unsigned(11 downto 0);
signal timestamp_dt_error_ctr_r : unsigned(11 downto 0);
- signal adc_notlock_ctr_r : unsigned(7 downto 0);
+ signal adc_notlock_ctr_r : unsigned(11 downto 0);
signal merge_error_ctr_r : unsigned(11 downto 0);
signal nx_frame_synced_rr : std_logic;
signal nx_frame_synced_r : std_logic;
signal rs_timeout_timer_reset : std_logic;
signal nx_timestamp_reset_o : std_logic;
signal nx_fifo_reset_handler : std_logic;
-
+
+ signal reset_handler_trigger : std_logic_vector(15 downto 0);
+
type R_STATES is (R_IDLE,
R_START,
R_WAIT_0,
adc_dt_shift_reg(3 downto 1) <= adc_dt_shift_reg(2 downto 0);
case adc_dt_shift_reg is
- when "1000" | "0100" | "0010" | "0001" |
- "1001" | "0011" | "0110" | "1100" =>
- adc_dt_error_p <= '0';
-
- when others =>
+ when "1100" | "1110" | "1111" | "0000" =>
adc_dt_error_ctr <= adc_dt_error_ctr + 1;
adc_dt_error_p <= '1';
-
+
+ when others =>
+ adc_dt_error_p <= '0';
+
end case;
-- TimeStamp
<= timestamp_dt_shift_reg(2 downto 0);
case timestamp_dt_shift_reg is
- when "1000" | "0100" | "0010" | "0001" |
- "1001" | "0011" | "0110" | "1100" =>
- timestamp_dt_error_p <= '0';
-
- when others =>
+ when "1100" | "1110" | "0000" =>
timestamp_dt_error_ctr <= timestamp_dt_error_ctr + 1;
timestamp_dt_error_p <= '1';
+ when others =>
+ timestamp_dt_error_p <= '0';
+
end case;
end if;
reset_timeout_flag <= '0';
startup_reset <= '1';
nx_timestamp_reset_o <= '0';
+ reset_handler_trigger <= (others => '0');
R_STATE <= R_IDLE;
else
frame_rates_reset <= '0';
-- Reset by register always wins, start it
rs_timeout_timer_reset <= '1';
reset_timeout_flag <= '0';
+ reset_handler_trigger(0) <= '1';
+ reset_handler_trigger(15 downto 1) <= (others => '0');
R_STATE <= R_START;
elsif (rs_timeout_timer_done = '1') then
-- Reset Timeout, retry RESET
rs_timeout_timer_reset <= '1';
reset_timeout_flag <= '1';
+ reset_handler_trigger(0) <= '0';
+ reset_handler_trigger(1) <= '1';
+ reset_handler_trigger(15 downto 2) <= (others => '0');
R_STATE <= R_START;
else
startup_reset = '1'
)
) then
+
+ reset_handler_trigger(1 downto 0) <= (others => '0');
+ reset_handler_trigger( 2) <= startup_reset;
+ reset_handler_trigger( 3) <= reset_after_offline;
+ reset_handler_trigger( 4) <= nx_frame_rate_error;
+ reset_handler_trigger( 5) <= parity_rate_error;
+ reset_handler_trigger( 6) <= timestamp_dt_error;
+ reset_handler_trigger( 7) <= nx_frame_rate_error;
+ reset_handler_trigger( 8) <= not adc_locked;
+ reset_handler_trigger( 9) <= not adc_sclk_ok_c100;
+ reset_handler_trigger(10) <= adc_dt_error;
+ reset_handler_trigger(11) <= adc_frame_rate_error;
+ reset_handler_trigger(12) <= adc_reset_sync;
+ reset_handler_trigger(13) <= pll_adc_not_lock;
+ reset_handler_trigger(15 downto 14) <= (others => '0');
+
R_STATE <= R_START;
else
reset_timeout_flag <= '0';
when x"0001" =>
slv_data_out_o(0) <= reset_handler_busy;
slv_data_out_o(1) <= reset_timeout_flag;
- slv_data_out_o(31 downto 2) <= (others => '0');
+ slv_data_out_o(15 downto 2) <= (others => '0');
+ slv_data_out_o(31 downto 16) <= reset_handler_trigger;
slv_ack_o <= '1';
when x"0002" =>
when x"0008" =>
slv_data_out_o(15 downto 0) <=
std_logic_vector(reset_handler_counter);
- slv_data_out_o(31 downto 6) <= (others => '0');
+ slv_data_out_o(31 downto 16) <= (others => '0');
slv_ack_o <= '1';
when x"0009" =>
slv_ack_o <= '1';
when x"000a" =>
- slv_data_out_o(7 downto 0) <=
+ slv_data_out_o(11 downto 0) <=
std_logic_vector(adc_notlock_ctr_r);
- slv_data_out_o(31 downto 8) <= (others => '0');
+ slv_data_out_o(31 downto 12) <= (others => '0');
slv_ack_o <= '1';
when x"000b" =>
std_logic_vector(adc_notlock_counter);
slv_data_out_o(31 downto 28) <= (others => '0');
slv_ack_o <= '1';
-
-
+
when x"001d" =>
slv_data_out_o(1 downto 0) <= johnson_counter_sync_r;
slv_data_out_o(31 downto 2) <= (others => '0');
-- Output Signals
data_o <= data_m;
- data_clk_o <=data_clk_m;
+ data_clk_o <= data_clk_m;
NX_TIMESTAMP_RESET_OUT <= nx_timestamp_reset_o;
DATA_OUT <= data_o;
signal pileup_ctr : unsigned(15 downto 0);
signal trigger_rate_inc : std_logic;
- signal frame_rate_inc : std_logic;
signal pileup_rate_inc : std_logic;
signal overflow_rate_inc : std_logic;
-- Rate Calculation
signal nx_trigger_ctr_t : unsigned(27 downto 0);
signal nx_trigger_ctr_t_nr : unsigned(31 downto 0);
- signal nx_frame_ctr_t : unsigned(27 downto 0);
+ signal frame_ctr_t : unsigned(27 downto 0);
signal nx_pileup_ctr_t : unsigned(27 downto 0);
signal nx_overflow_ctr_t : unsigned(27 downto 0);
signal adc_tr_error_ctr_t : unsigned(27 downto 0);
-
+ signal adc_tr_update_ctr_t : unsigned(27 downto 0);
+ signal adc_tr_data_ctr_t : unsigned(27 downto 0);
+
signal nx_rate_timer : unsigned(27 downto 0);
-- ADC Averages
signal adc_data_last : std_logic_vector(11 downto 0);
-- Token Return Average
- signal nx_token_return_pipec : std_logic_vector(4 downto 0);
- signal nx_token_return_pipev : std_logic_vector(8 downto 0);
+ signal nx_token_return_pipec : std_logic_vector(9 downto 0);
+ signal nx_token_return_pipev : std_logic_vector(11 downto 0);
signal adc_tr_value_tmp : std_logic_vector(11 downto 0);
signal adc_tr_value : std_logic_vector(11 downto 0);
signal adc_tr_data_p : unsigned(11 downto 0);
signal readout_type : std_logic_vector(1 downto 0);
-- Error Status
+ signal new_timestamp_shift : std_logic_vector(3 downto 0);
+ signal frame_dt_error : std_logic;
+ signal frame_dt_error_ctr : unsigned(15 downto 0);
+ signal frame_rate_error : std_logic;
signal error_o : std_logic;
-- Slave Bus
signal slv_ack_o : std_logic;
signal clear_counters : std_logic;
signal nx_hit_rate : unsigned(27 downto 0);
- signal nx_frame_rate : unsigned(27 downto 0);
+ signal frame_rate : unsigned(27 downto 0);
signal nx_pileup_rate : unsigned(27 downto 0);
signal nx_overflow_rate : unsigned(27 downto 0);
signal adc_tr_error_rate : unsigned(27 downto 0);
+ signal adc_tr_update_rate : unsigned(27 downto 0);
+ signal adc_tr_data_rate : unsigned(27 downto 0);
signal invalid_adc : std_logic;
signal adc_tr_value_r : std_logic_vector(11 downto 0);
nx_token_return_o <= '0';
nx_nomore_data_o <= '0';
trigger_rate_inc <= '0';
- frame_rate_inc <= '0';
pileup_rate_inc <= '0';
overflow_rate_inc <= '0';
parity_error_ctr <= (others => '0');
adc_data_o <= (others => '0');
data_clk_o <= '0';
trigger_rate_inc <= '0';
- frame_rate_inc <= '0';
pileup_rate_inc <= '0';
overflow_rate_inc <= '0';
invalid_adc <= '0';
if (new_timestamp = '1') then
adc_data_last <= adc_data;
-
+
if (parity_error = '1') then
parity_error_ctr <= parity_error_ctr + 1;
end if;
trigger_rate_inc <= '1';
if (nx_token_return_o = '1' and
- nx_token_return_pipec = "11111") then
+ nx_token_return_pipec = "1111111111") then
-- First Data Word after 5 empty Frames
adc_tr_data_p <= unsigned(adc_data_last);
adc_tr_data_c <= unsigned(adc_data);
end case;
- frame_rate_inc <= '1';
-
-- Token Return Check Handler
case TR_STATE is
when S_IDLE =>
- if (nx_token_return_pipev(4 downto 0) = "11111") then
+ if (nx_token_return_pipev(6 downto 0) = "1111111") then
adc_tr_value_tmp <= adc_data_last;
TR_STATE <= S_START;
else
state_debug <= "01";
when S_START =>
- if (nx_token_return_pipev = "111111111") then
+ if (nx_token_return_pipev = "111111111111") then
TR_STATE <= S_END;
- elsif (nx_token_return_pipev(5 downto 0) = "111111" or
- nx_token_return_pipev(6 downto 0) = "1111111" or
- nx_token_return_pipev(7 downto 0) = "11111111") then
+ elsif (nx_token_return_pipev( 6 downto 0) = "1111111" or
+ nx_token_return_pipev( 7 downto 0) = "11111111" or
+ nx_token_return_pipev( 8 downto 0) = "111111111" or
+ nx_token_return_pipev( 9 downto 0) = "1111111111" or
+ nx_token_return_pipev(10 downto 0) = "11111111111") then
TR_STATE <= S_START;
else
TR_STATE <= S_IDLE;
-- Token Return Pipeline
nx_token_return_pipec(0) <= nx_token_return_o;
- for I in 1 to 4 loop
+ for I in 1 to 9 loop
nx_token_return_pipec(I) <= nx_token_return_pipec(I - 1);
end loop;
if (TR_STATE /= S_END) then
nx_token_return_pipev(0) <= nx_token_return_o;
- for I in 1 to 8 loop
+ for I in 1 to 11 loop
nx_token_return_pipev(I) <= nx_token_return_pipev(I - 1);
end loop;
else
begin
if( rising_edge(CLK_IN) ) then
if (RESET_IN = '1') then
- nx_trigger_ctr_t <= (others => '0');
- nx_trigger_ctr_t_nr <= (others => '0');
- nx_frame_ctr_t <= (others => '0');
nx_rate_timer <= (others => '0');
- nx_hit_rate <= (others => '0');
- nx_frame_rate <= (others => '0');
+
+ nx_trigger_ctr_t <= (others => '0');
+ frame_ctr_t <= (others => '0');
adc_tr_error_ctr_t <= (others => '0');
- adc_tr_error_ctr <= (others => '0');
+ adc_tr_update_ctr_t <= (others => '0');
+ adc_tr_data_ctr_t <= (others => '0');
+
+ nx_hit_rate <= (others => '0');
+ frame_rate <= (others => '0');
adc_tr_error_rate <= (others => '0');
+ adc_tr_update_rate <= (others => '0');
+ adc_tr_data_rate <= (others => '0');
+
+ nx_trigger_ctr_t_nr <= (others => '0');
+ adc_tr_error_ctr <= (others => '0');
else
if (nx_rate_timer < x"5f5e100") then
if (trigger_rate_inc = '1') then
nx_trigger_ctr_t <= nx_trigger_ctr_t + 1;
nx_trigger_ctr_t_nr <= nx_trigger_ctr_t_nr + 1;
end if;
- if (frame_rate_inc = '1') then
- nx_frame_ctr_t <= nx_frame_ctr_t + 1;
+ if (new_timestamp = '1') then
+ frame_ctr_t <= frame_ctr_t + 1;
end if;
if (pileup_rate_inc = '1') then
nx_pileup_ctr_t <= nx_pileup_ctr_t + 1;
adc_tr_error_ctr_t <= adc_tr_error_ctr_t + 1;
adc_tr_error_ctr <= adc_tr_error_ctr + 1;
end if;
+ if (adc_tr_value_update = '1') then
+ adc_tr_update_ctr_t <= adc_tr_update_ctr_t + 1;
+ end if;
+ if (adc_tr_data_clk = '1') then
+ adc_tr_data_ctr_t <= adc_tr_data_ctr_t + 1;
+ end if;
+
nx_rate_timer <= nx_rate_timer + 1;
else
nx_hit_rate <= nx_trigger_ctr_t;
- nx_frame_rate <= nx_frame_ctr_t;
+ frame_rate <= frame_ctr_t;
nx_pileup_rate <= nx_pileup_ctr_t;
nx_overflow_rate <= nx_overflow_ctr_t;
adc_tr_error_rate <= adc_tr_error_ctr_t;
-
+ adc_tr_update_rate <= adc_tr_update_ctr_t;
+ adc_tr_data_rate <= adc_tr_data_ctr_t;
+
nx_trigger_ctr_t(27 downto 1) <= (others => '0');
nx_trigger_ctr_t(0) <= trigger_rate_inc;
- nx_frame_ctr_t(27 downto 1) <= (others => '0');
- nx_frame_ctr_t(0) <= frame_rate_inc;
+ frame_ctr_t(27 downto 1) <= (others => '0');
+ frame_ctr_t(0) <= new_timestamp;
nx_pileup_ctr_t(27 downto 1) <= (others => '0');
nx_pileup_ctr_t(0) <= pileup_rate_inc;
adc_tr_error_ctr_t(27 downto 0) <= (others => '0');
adc_tr_error_ctr_t(0) <= adc_tr_error;
+
+ adc_tr_update_ctr_t(27 downto 0) <= (others => '0');
+ adc_tr_update_ctr_t(0) <= adc_tr_value_update;
+
+ adc_tr_data_ctr_t(27 downto 0) <= (others => '0');
+ adc_tr_data_ctr_t(0) <= adc_tr_data_clk;
nx_rate_timer <= (others => '0');
end if;
end if;
end process PROC_ADC_TOKEN_RETURN;
- PROC_ADC_TOKEN_RETURN_ERROR: process(CLK_IN)
+ PROC_ERROR_HANDLER: process(CLK_IN)
begin
if (rising_edge(CLK_IN) ) then
if (RESET_IN = '1') then
- error_o <= '0';
+ frame_rate_error <= '0';
+ error_o <= '0';
else
if (adc_tr_error_rate > x"0000020" and DISABLE_ADC_IN = '0') then
- error_o <= '1';
+ error_o <= '1';
else
- error_o <= '0';
+ error_o <= '0';
+ end if;
+
+ if ((frame_rate < x"1dc_d64e" or
+ frame_rate > x"1dc_d652")) then
+ frame_rate_error <= '1';
+ else
+ frame_rate_error <= '0';
end if;
end if;
end if;
- end process PROC_ADC_TOKEN_RETURN_ERROR;
-
+ end process PROC_ERROR_HANDLER;
+
+ PROC_DATA_STREAM_DELTA_T: process(CLK_IN)
+ begin
+ if (rising_edge(CLK_IN)) then
+ if (RESET_IN = '1') then
+ new_timestamp_shift <= (others => '0');
+ frame_dt_error_ctr <= (others => '0');
+ frame_dt_error <= '0';
+ else
+ -- Frame
+ new_timestamp_shift(0) <= new_timestamp;
+ new_timestamp_shift(3 downto 1) <= new_timestamp_shift(2 downto 0);
+
+ case new_timestamp_shift is
+ when "1100" | "1110" | "1111" | "0000" =>
+ frame_dt_error_ctr <= frame_dt_error_ctr + 1;
+ frame_dt_error <= '1';
+
+ when others =>
+ frame_dt_error <= '0';
+
+ end case;
+
+ end if;
+ end if;
+ end process PROC_DATA_STREAM_DELTA_T;
+
-----------------------------------------------------------------------------
-- TRBNet Slave Bus
-----------------------------------------------------------------------------
when x"0001" =>
slv_data_out_o(27 downto 0) <=
- std_logic_vector(nx_frame_rate);
- slv_data_out_o(31 downto 28) <= (others => '0');
+ std_logic_vector(frame_rate);
+ slv_data_out_o(30 downto 28) <= (others => '0');
+ slv_data_out_o(31) <= frame_rate_error;
slv_ack_o <= '1';
-
+
when x"0002" =>
+ slv_data_out_o(15 downto 0)
+ <= std_logic_vector(parity_error_ctr);
+ slv_data_out_o(31 downto 16) <= (others => '0');
+ slv_ack_o <= '1';
+
+ when x"0003" =>
+ slv_data_out_o(15 downto 0) <=
+ std_logic_vector(invalid_frame_ctr);
+ slv_data_out_o(31 downto 16) <= (others => '0');
+ slv_ack_o <= '1';
+
+ when x"0004" =>
slv_data_out_o(27 downto 0) <=
std_logic_vector(nx_pileup_rate);
slv_data_out_o(31 downto 28) <= (others => '0');
slv_ack_o <= '1';
- when x"0003" =>
+ when x"0005" =>
slv_data_out_o(27 downto 0) <=
std_logic_vector(nx_overflow_rate);
slv_data_out_o(31 downto 28) <= (others => '0');
- slv_ack_o <= '1';
-
- when x"0004" =>
- slv_data_out_o(3 downto 0) <=
- std_logic_vector(adc_average_divisor);
- slv_data_out_o(31 downto 4) <= (others => '0');
slv_ack_o <= '1';
-
- when x"0005" =>
- slv_data_out_o(11 downto 0) <= std_logic_vector(adc_average);
- slv_data_out_o(31 downto 12) <= (others => '0');
- slv_ack_o <= '1';
-
+
when x"0006" =>
slv_data_out_o(1 downto 0) <= adc_tr_error_status;
slv_data_out_o(31 downto 2) <= (others => '0');
slv_ack_o <= '1';
when x"0009" =>
- slv_data_out_o(15 downto 0)
- <= std_logic_vector(parity_error_ctr);
- slv_data_out_o(31 downto 16) <= (others => '0');
- slv_ack_o <= '1';
+ slv_data_out_o(27 downto 0)
+ <= std_logic_vector(adc_tr_update_rate);
+ slv_data_out_o(31 downto 28) <= (others => '0');
+ slv_ack_o <= '1';
when x"000a" =>
+ slv_data_out_o(27 downto 0)
+ <= std_logic_vector(adc_tr_data_rate);
+ slv_data_out_o(31 downto 28) <= (others => '0');
+ slv_ack_o <= '1';
+
+ when x"000b" =>
slv_data_out_o(11 downto 0)
<= std_logic_vector(adc_tr_limit);
slv_data_out_o(31 downto 12) <= (others => '0');
slv_ack_o <= '1';
- when x"000b" =>
- slv_data_out_o(11 downto 0)
- <= std_logic_vector(adc_tr_error_ctr);
+ when x"000c" =>
+ slv_data_out_o(11 downto 0) <= std_logic_vector(adc_average);
slv_data_out_o(31 downto 12) <= (others => '0');
slv_ack_o <= '1';
-
- when x"000c" =>
+
+ when x"000d" =>
+ slv_data_out_o(3 downto 0) <=
+ std_logic_vector(adc_average_divisor);
+ slv_data_out_o(31 downto 4) <= (others => '0');
+ slv_ack_o <= '1';
+
+ when x"000e" =>
slv_data_out_o(15 downto 0) <=
std_logic_vector(pileup_ctr);
slv_data_out_o(31 downto 16) <= (others => '0');
slv_ack_o <= '1';
- when x"000d" =>
+ when x"000f" =>
slv_data_out_o(15 downto 0) <=
std_logic_vector(overflow_ctr);
slv_data_out_o(31 downto 16) <= (others => '0');
slv_ack_o <= '1';
- when x"000e" =>
- slv_data_out_o(15 downto 0) <=
- std_logic_vector(invalid_frame_ctr);
- slv_data_out_o(31 downto 16) <= (others => '0');
+ when x"0010" =>
+ slv_data_out_o(11 downto 0)
+ <= std_logic_vector(adc_tr_error_ctr);
+ slv_data_out_o(31 downto 12) <= (others => '0');
slv_ack_o <= '1';
-
- when x"000f" =>
+
+ when x"0011" =>
slv_data_out_o(0) <= adc_tr_debug_mode;
slv_data_out_o(31 downto 1) <= (others => '0');
slv_ack_o <= '1';
- when x"0010" =>
+ when x"0012" =>
slv_data_out_o <= nx_trigger_ctr_t_nr;
slv_ack_o <= '1';
+ when x"0013" =>
+ slv_data_out_o(15 downto 0) <= frame_dt_error_ctr;
+ slv_data_out_o(31 downto 16) <= (others => '0');
+ slv_ack_o <= '1';
+
when others =>
slv_unknown_addr_o <= '1';
slv_ack_o <= '0';
when x"0000" =>
clear_counters <= '1';
slv_ack_o <= '1';
-
- when x"0004" =>
- adc_average_divisor <= SLV_DATA_IN(3 downto 0);
- slv_ack_o <= '1';
-
- when x"000a" =>
+
+ when x"000b" =>
adc_tr_limit
<= unsigned(SLV_DATA_IN(11 downto 0));
slv_ack_o <= '1';
- when x"000f" =>
+ when x"000d" =>
+ adc_average_divisor <= SLV_DATA_IN(3 downto 0);
+ slv_ack_o <= '1';
+
+ when x"0011" =>
adc_tr_debug_mode <= SLV_DATA_IN(0);
slv_ack_o <= '1';
slv_ack_o <= '1';
when x"000a" =>
- status_trigger_type <= SLV_DATA_IN(3 downto 0);
+ calibration_trigger_type <= SLV_DATA_IN(3 downto 0);
slv_ack_o <= '1';
when others =>
signal reset_hists_o : std_logic;
-- Timestamp Trigger Window Settings
- signal nxyter_cv_time : unsigned(11 downto 0);
- signal cts_trigger_delay : unsigned(11 downto 0);
- signal ts_window_offset : signed(11 downto 0);
- signal ts_window_width : unsigned(9 downto 0);
- signal readout_time_max : unsigned(11 downto 0);
- signal fpga_timestamp_offset : unsigned(11 downto 0);
-
- signal state_d : std_logic_vector(1 downto 0);
+ signal nxyter_cv_time : unsigned(11 downto 0);
+ signal cts_trigger_delay : unsigned(11 downto 0);
+ signal trigger_calibration_delay : unsigned(11 downto 0);
+ signal ts_window_offset : signed(11 downto 0);
+ signal ts_window_width : unsigned(9 downto 0);
+ signal readout_time_max : unsigned(11 downto 0);
+ signal fpga_timestamp_offset : unsigned(11 downto 0);
+
+ signal state_d : std_logic_vector(1 downto 0);
+ -----------------------------------------------------------------------------
+
attribute syn_keep : boolean;
attribute syn_keep of timestamp_fpga_ff : signal is true;
attribute syn_keep of timestamp_fpga_f : signal is true;
-- Calculate Thresholds and values for FIFO Delay
-----------------------------------------------------------------------
- if (trigger_calibration = '0') then
- cts_trigger_delay_tmp := cts_trigger_delay;
- else
- cts_trigger_delay_tmp := (others => '0');
- end if;
-
+ cts_trigger_delay_tmp := cts_trigger_delay;
+
if (ts_window_offset(11) = '1') then
-- Offset is negative
ts_window_offset_unsigned :=
-- Final lower Threshold value relative to TS Reference TS
window_lower_thr := timestamp_fpga - window_lower_thr;
-
window_upper_thr :=
window_lower_thr + resize(ts_window_width, 12);
+
ts_window_check_value :=
unsigned(TIMESTAMP_IN(13 downto 2)) - window_lower_thr;
-
+
-- Timestamp to be stored
deltaTStore(13 downto 2) := ts_window_check_value;
deltaTStore( 1 downto 0) := unsigned(TIMESTAMP_IN(1 downto 0));
min_validation_time + wait_for_data_time;
wait_for_data_time := x"00001";
end if;
+
+ if (trigger_calibration = '1') then
+ min_validation_time :=
+ min_validation_time + resize(trigger_calibration_delay, 20);
+ end if;
+
min_validation_time_r <= min_validation_time;
wait_for_data_time_r <= wait_for_data_time;
timestamp_fpga <=
timestamp_fpga_f + fpga_timestamp_offset;
end if;
+
+ if (trigger_calibration = '1') then
+ timestamp_fpga <=
+ timestamp_fpga_f + trigger_calibration_delay;
+ end if;
STATE <= S_WRITE_HEADER;
end if;
histogram_limits <= '0';
histogram_trig_filter <= '0';
histogram_ts_range <= "100";
+ trigger_calibration_delay <= x"190"; -- 400ns
else
slv_data_out_o <= (others => '0');
slv_unknown_addr_o <= '0';
when x"0003" =>
slv_data_out_o(9 downto 0) <=
std_logic_vector(cts_trigger_delay(9 downto 0));
- slv_data_out_o(31 downto 10) <= (others => '0');
+ slv_data_out_o(15 downto 10) <= (others => '0');
+ slv_data_out_o(27 downto 16) <=
+ std_logic_vector(trigger_calibration_delay);
+ slv_data_out_o(31 downto 28) <= (others => '0');
slv_ack_o <= '1';
when x"0004" =>
when x"001a" =>
slv_data_out_o(11 downto 0) <=
std_logic_vector(nxyter_cv_time);
- slv_data_out_o(31 downto 12) <= (others => '0');
+ slv_data_out_o(31 downto 12) <= (others => '0');
slv_ack_o <= '1';
-
+
when x"001b" =>
slv_data_out_o(19 downto 0) <=
std_logic_vector(min_validation_time_r);
when x"0003" =>
cts_trigger_delay(9 downto 0) <=
unsigned(SLV_DATA_IN(9 downto 0));
+ trigger_calibration_delay <=
+ unsigned(SLV_DATA_IN(27 downto 16));
slv_ack_o <= '1';
when x"0004" =>
when x"0020" =>
histogram_lower_limit <= SLV_DATA_IN(13 downto 0);
histogram_upper_limit <= SLV_DATA_IN(28 downto 15);
- reset_hists <= SLV_DATA_IN(29);
histogram_limits <= SLV_DATA_IN(30);
histogram_trig_filter <= SLV_DATA_IN(31);
+ reset_hists <= '1';
slv_ack_o <= '1';
when x"0021" =>
+ reset_hists <= '1';
histogram_ts_range <= SLV_DATA_IN(2 downto 0);
slv_ack_o <= '1';
error_all(0) <= error_data_receiver;
error_all(1) <= error_data_validate;
error_all(2) <= error_event_buffer;
- error_all(7 downto 3) <= (others => '0');
+ error_all(3) <= not nxyter_online;
+ error_all(7 downto 4) <= (others => '0');
-------------------------------------------------------------------------------
-- Port Maps
9 => 9, -- NX Register Setup
10 => 11, -- NX Histograms
11 => 0, -- Debug Handler
- 12 => 1, -- Data Delay
+ 12 => 3, -- Data Delay
others => 0
),
USE EDGE2EDGE NET "NX_CLK_ADC_DAT";
USE PRIMARY NET "nXyter_FEE_board_0/nx_data_receiver_1/adc_ad9228_1/DDR_DATA_CLK_c";
-PRIORITIZE NET "NX1_DATA_CLK_IN_c" 40;
-PRIORITIZE NET "nXyter_FEE_board_0/nx_data_receiver_1/adc_ad9228_1/DDR_DATA_CLK_c" 50;
+#PRIORITIZE NET "NX1_DATA_CLK_IN_c" 40;
+#PRIORITIZE NET "nXyter_FEE_board_0/nx_data_receiver_1/adc_ad9228_1/DDR_DATA_CLK_c" 50;
#################################################################
# Reset Nets
MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_event_buffer_*/fifo_almost_full_thr_*" 100 ns;
-MULTICYCLE FROM CELL "nXyter_FEE_board_*/debug_multiplexer_*/port_select_*" 100 ns;
+MULTICYCLE FROM CELL "nXyter_FEE_board_*/debug_multiplexer_*/port_select_*" 500 ns;
MULTICYCLE TO GROUP "TEST_LINE_group" 500.000000 ns ;
MULTICYCLE TO GROUP "NX1_DEBUG_LINE_group" 500.000000 ns ;
-i 2
-l 5
-n 40
--t 20
+-t 40
-s 1
-c 1
-e 2
jspc29 / trb3.git / commitdiff