]> jspc29.x-matter.uni-frankfurt.de Git - TOMcat.git/commitdiff
preparations for forwarder test
authorMichael Boehmer <mboehmer@ph.tum.de>
Mon, 18 Jul 2022 09:40:27 +0000 (11:40 +0200)
committerMichael Boehmer <mboehmer@ph.tum.de>
Mon, 18 Jul 2022 09:40:27 +0000 (11:40 +0200)
code/clock_reset_handler.vhd
code/tomcat_tools.vhd
gbe/tomcat_gbe.prj
gbe/tomcat_gbe.vhd

index 3f40f415b9efb76debc3bc48836c1166bf580388..43bfcf6cd8d67498c6fa6eed4000e08008ce48b2 100644 (file)
@@ -20,6 +20,8 @@ entity clock_reset_handler is
     CLEAR_OUT         : out std_logic;
     CLEAR_N_OUT       : out std_logic;
     --
+    TICK_MS_OUT       : out std_logic;
+    --
     LED_RED_OUT       : out std_logic;
     LED_GREEN_OUT     : out std_logic
   );
@@ -31,6 +33,10 @@ signal timer                        : unsigned(15 downto 0) := (others => '0');
 signal clear_n_i                    : std_logic;
 signal reset_i                      : std_logic;
 
+signal counter                      : unsigned(16 downto 0);
+signal counter_done_x               : std_logic;
+signal counter_done                 : std_logic;
+
 attribute syn_keep                  : boolean;
 attribute syn_preserve              : boolean;
 attribute syn_keep of clear_n_i     : signal is true;
@@ -42,6 +48,24 @@ begin
 
   CLK_OUT <= CLK_IN;
 
+---------------------------------------------------------------------------
+---------------------------------------------------------------------------
+THE_MS_COUNTER_PROC: process( CLK_IN )
+begin
+  if( rising_edge(CLK_IN) ) then
+    counter_done <= counter_done_x;
+    if( counter_done = '1' ) then
+      counter <= b"1_1110_1000_0100_0110";
+    else
+      counter <= counter - 1;
+    end if;
+  end if;
+end process THE_MS_COUNTER_PROC;
+
+counter_done_x <= '1' when (counter = b"0_0000_0000_0000_0000") else '0';
+
+TICK_MS_OUT <= counter_done;
+
 ---------------------------------------------------------------------------
 -- Startup timer, generates inital reset
 ---------------------------------------------------------------------------          
index 15a7a2a0879d4c2f17fd5986c04d13ddab32bfc6..2af7719a2ba763175db14ea4e11be99c35582d41 100644 (file)
@@ -28,6 +28,10 @@ entity tomcat_tools is
     BUS_MASTER_ACTIVE : out   std_logic;
     -- Additional regs
     ADDITIONAL_REG    : out   std_logic_vector(31 downto 0);
+    -- Ethernet registers
+    FWD_MAC_OUT       : out   std_logic_vector(47 downto 0);
+    FWD_IP_OUT        : out   std_logic_vector(31 downto 0);
+    FWD_PORT_OUT      : out   std_logic_vector(15 downto 0);
     -- I2C
     SDA_INOUT         : inout std_logic;
     SCL_INOUT         : inout std_logic;
@@ -51,7 +55,6 @@ signal debug_rx           : std_logic;
 signal debug_tx           : std_logic;
 signal debug_status       : std_logic_vector(31 downto 0);
 signal debug_spi          : std_logic_vector(31 downto 0);
-signal additional_reg_i   : std_logic_vector(31 downto 0);
 
 signal i2c_reg0_i         : std_logic_vector(31 downto 0) := x"0000_0000";
 signal i2c_reg1_i         : std_logic_vector(31 downto 0) := x"0000_0000";
@@ -63,6 +66,15 @@ signal scl_drv            : std_logic;
 signal i2c_start_x        : std_logic;
 signal i2c_start          : std_logic;
 
+signal add_reg0_i         : std_logic_vector(31 downto 0) := x"0000_0000";
+signal add_reg1_i         : std_logic_vector(31 downto 0) := x"0000_0011";
+signal add_reg2_i         : std_logic_vector(31 downto 0) := x"0000_0022";
+signal add_reg3_i         : std_logic_vector(31 downto 0) := x"0000_0033";
+signal add_reg4_i         : std_logic_vector(31 downto 0) := x"0000_0044";
+signal add_reg5_i         : std_logic_vector(31 downto 0) := x"0000_0055";
+signal add_reg6_i         : std_logic_vector(31 downto 0) := x"0000_0066";
+signal add_reg7_i         : std_logic_vector(31 downto 0) := x"0000_0077";
+
 begin
 
 ---------------------------------------------------------------------------
@@ -72,7 +84,7 @@ begin
   generic map(
     PORT_NUMBER      => 4,
     PORT_ADDRESSES   => (0 => x"0000", 1 => x"0180", 2 => x"0580", 3 => x"0700", others => x"0000"),
-    PORT_ADDR_MASK   => (0 => 9,       1 => 4,       2 => 0,       3 => 2,       others => 0),
+    PORT_ADDR_MASK   => (0 => 9,       1 => 4,       2 => 3,       3 => 2,       others => 0),
     PORT_MASK_ENABLE => 1
   )
   -- 0 flash, 1 flashset, 2 ctrl, 3 I2C
@@ -180,26 +192,51 @@ gen_nodebug : if INCLUDE_DEBUG_INTERFACE = 0 generate
   debug_tx <= 'Z';
   debug_active <= '0';
 end generate;
-  
+
 ---------------------------------------------------------------------------
--- Additional control register
----------------------------------------------------------------------------  
-  PROC_ADD_REG : process begin
-    wait until rising_edge(CLK);
-    busctrl_tx.ack     <= '0';
-    busctrl_tx.nack    <= '0';
-    busctrl_tx.unknown <= '0';
-  
-    if busctrl_rx.read = '1' then
-      busctrl_tx.data(additional_reg_i'left downto 0) <= additional_reg_i;
-      busctrl_tx.ack <= '1';
-    elsif busctrl_rx.write = '1' then
-      additional_reg_i <= busctrl_rx.data(additional_reg_i'left downto 0);
-      busctrl_tx.ack <= '1';
+-- Additional registers
+---------------------------------------------------------------------------
+  THE_ADD_REG_PROC: process( CLK )
+  begin
+    if( rising_edge(CLK) ) then
+      busctrl_tx.ack     <= '0';
+      busctrl_tx.nack    <= '0';
+      busctrl_tx.unknown <= '0';
+    
+      if   ( busctrl_rx.read = '1' ) then
+        case busctrl_rx.addr(2 downto 0) is
+          when b"000"  => busctrl_tx.data <= add_reg0_i;
+          when b"001"  => busctrl_tx.data <= add_reg1_i;
+          when b"010"  => busctrl_tx.data <= add_reg2_i;
+          when b"011"  => busctrl_tx.data <= add_reg3_i;
+          when b"100"  => busctrl_tx.data <= add_reg4_i;
+          when b"101"  => busctrl_tx.data <= add_reg5_i;
+          when b"110"  => busctrl_tx.data <= add_reg6_i;
+          when others  => busctrl_tx.data <= add_reg7_i;
+        end case;
+        busctrl_tx.ack <= '1';
+      elsif( busctrl_rx.write = '1' ) then
+        case busctrl_rx.addr(2 downto 0) is
+          when b"000"  => add_reg0_i <= busctrl_rx.data;
+          when b"001"  => add_reg1_i <= busctrl_rx.data;
+          when b"010"  => add_reg2_i <= busctrl_rx.data;
+          when b"011"  => add_reg3_i <= busctrl_rx.data;
+          when b"100"  => add_reg4_i <= busctrl_rx.data;
+          when b"101"  => add_reg5_i <= busctrl_rx.data;
+          when b"110"  => add_reg6_i <= busctrl_rx.data;
+          when others  => add_reg7_i <= busctrl_rx.data;
+        end case;
+        busctrl_tx.ack <= '1';
+      end if;
     end if;
-  end process PROC_ADD_REG;
+  end process THE_ADD_REG_PROC;
+
+  ADDITIONAL_REG <= add_reg0_i;
 
-  ADDITIONAL_REG <= additional_reg_i;
+  FWD_MAC_OUT(31 downto 0)  <= add_reg4_i;
+  FWD_MAC_OUT(47 downto 32) <= add_reg5_i(15 downto 0);
+  FWD_IP_OUT                <= add_reg6_i;
+  FWD_PORT_OUT              <= add_reg7_i(15 downto 0);
 
 ---------------------------------------------------------------------------
 -- I2C
index e90064de33f02a9d4c1f1f41ee6a9e05647435f2..72fb0b106a977c315bf0506fd4b094f2dd2cf1c5 100644 (file)
@@ -215,4 +215,13 @@ add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_8kx9_af_cnt.vhd
 add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_2kx9x18_wcnt.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_4kx18x9_wcnt.vhd"
 
+# Link Delay Measurement stuff
+#add_file -vhdl -lib work "../../dlm/base/ddmtd.vhd"
+#add_file -vhdl -lib work "../../dlm/base/deglitch.vhd"
+#add_file -vhdl -lib work "../../dlm/base/statistics.vhd"
+#add_file -vhdl -lib work "../../dlm/base/clockbox.vhd"
+#add_file -vhdl -lib work "../../dlm/base/clockpoint.vhd"
+#add_file -vhdl -lib work "../../dlm/cores/ecp5-5g/statmem.vhd"
+#add_file -vhdl -lib work "../../dlm/base/phaserbox.vhd"
+
 add_file -vhdl -lib work "./tomcat_gbe.vhd"
index 7dfa12b995ea6ee3d587b17c8ba17990b8d07ed9..c3cf2f810989fc001092c4ed5e625de004e8c6d9 100644 (file)
@@ -150,6 +150,12 @@ architecture arch of tomcat_gbe is
   signal sniffer_eof                : std_logic;
   signal sniffer_error              : std_logic;
 
+  signal tick_int                   : std_logic;
+
+  signal fwd_mac_int                : std_logic_vector(47 downto 0);
+  signal fwd_ip_int                 : std_logic_vector(31 downto 0);
+  signal fwd_port_int               : std_logic_vector(15 downto 0);
+  
 begin
 
 ---------------------------------------------------------------------------
@@ -178,6 +184,8 @@ begin
     CLEAR_OUT         => clear_i,
     CLEAR_N_OUT       => clear_n_i,
     --
+    TICK_MS_OUT       => tick_int,
+    --
     LED_RED_OUT       => open,
     LED_GREEN_OUT     => open
   );
@@ -247,8 +255,8 @@ begin
   debug(28) <= port_sel(0);
   debug(29) <= ul_rx_fifofull;
   debug(30) <= ul_tx_fifofull;
-  debug(31) <= scatter_cycle_done;
-  debug(32) <= gather_cycle_done;
+  debug(31) <= '0';
+  debug(32) <= tick_int;
   debug(33) <= clk_sys;
 ---------------------------------------------------------------------------
 ---------------------------------------------------------------------------
@@ -278,6 +286,7 @@ begin
     FRAME_REQ_OUT(0 downto 0)    => dl_rx_frame_req(0 downto 0),
     FRAME_ACK_IN(0 downto 0)     => dl_rx_frame_ack(0 downto 0),
     PORT_SELECT_OUT(0 downto 0)  => port_sel,
+    PORT_MUX_OUT                 => open, 
     CYCLE_DONE_OUT               => gather_cycle_done, --open,
     --
     DEBUG                        => open
@@ -312,7 +321,7 @@ begin
       -- Trigger
       TRIGGER_IN               => '0',
       -- we connect to FIFO interface directly
-      -- FIFO interface RX
+      -- FIFO interface TX (transmit frames)
       FIFO_DATA_OUT            => dl_rx_data(0)(8 downto 0),
       FIFO_FULL_IN             => ul_tx_fifofull,
       FIFO_WR_OUT              => dl_rx_data(0)(9),
@@ -325,15 +334,9 @@ begin
       MAC_RX_WRITE_IN          => sniffer_wr,
       MAC_RX_EOF_IN            => sniffer_eof,
       MAC_RX_ERROR_IN          => sniffer_error,
---      -- FIFO interface TX
---      FIFO_FULL_OUT            => dl_tx_fifofull(0),
---      FIFO_WR_IN               => ul_rx_data(9),
---      FIFO_DATA_IN             => ul_rx_data(8 downto 0),
---      FRAME_START_IN           => ul_rx_data(10),
       --
       PCS_AN_READY_IN          => link_active,
       LINK_ACTIVE_IN           => link_active,
-      --                        
       -- unique adresses
       MC_UNIQUE_ID_IN          => timer.uid,
       MY_TRBNET_ADDRESS_IN     => timer.network_address,
@@ -354,6 +357,16 @@ begin
       BUS_IP_TX                => busgbeip_tx,
       BUS_REG_RX               => busgbereg_rx,
       BUS_REG_TX               => busgbereg_tx,
+      -- Forwarder
+      FWD_DST_MAC_IN           => fwd_mac_int,
+      FWD_DST_IP_IN            => fwd_ip_int,
+      FWD_DST_UDP_IN           => fwd_port_int,
+      FWD_DATA_IN              => x"00", --: in  std_logic_vector(7 downto 0) := (others => '0');
+      FWD_DATA_VALID_IN        => '0', --: in  std_logic := '0';
+      FWD_SOP_IN               => '0', --: in  std_logic := '0';
+      FWD_EOP_IN               => '0', --: in  std_logic := '0';
+      FWD_READY_OUT            => open, --: out std_logic;
+      FWD_FULL_OUT             => open, --: out std_logic;
       -- reset
       MAKE_RESET_OUT           => reset_via_gbe,
       -- debug
@@ -466,6 +479,10 @@ begin
       SCL_INOUT          => SFP_MOD_1, --open, --SI2C_SCL,      
       -- Additional register
       ADDITIONAL_REG     => additional_reg,
+      -- Ethernet registers
+      FWD_MAC_OUT        => open,
+      FWD_IP_OUT         => open,
+      FWD_PORT_OUT       => open,
       --Slowcontrol
       BUS_RX             => bustools_rx,
       BUS_TX             => bustools_tx,
@@ -500,10 +517,10 @@ begin
   
 --  GPIO                <= (others => '0');
   GPIO(15 downto 14)  <= (others => '0');
---  GPIO(13 downto 0)   <= debug(33 downto 20);
-  GPIO(8 downto 0)    <= debug(28 downto 20);
-  GPIO(12 downto 9)   <= debug(71 downto 68);
-  GPIO(13 downto 13)  <= debug(33 downto 33);
+  GPIO(13 downto 0)   <= debug(33 downto 20);
+--  GPIO(8 downto 0)    <= debug(28 downto 20);
+--  GPIO(12 downto 9)   <= debug(71 downto 68);
+--  GPIO(13 downto 13)  <= debug(33 downto 33);
 --  GPIO                <= (others => 'Z');
   
   TIMING_TEST         <= reset_via_gbe; --'0';