use work.trb_net_gbe_components.all;
use work.trb_net_gbe_protocols.all;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+use work.trb_net16_hub_func.all;
+
entity testbench is
end testbench;
architecture behavior of testbench is
+component trb_net16_hub_streaming_port_sctrl is
+ generic(
+ --hub control
+ INIT_ADDRESS : std_logic_vector(15 downto 0) := x"F004";
+ INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := (others => '0');
+ COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000";
+ COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001";
+ HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678";
+ INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001";
+ BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"7E";
+ CLOCK_FREQUENCY : integer range 1 to 200 := 100;
+ USE_ONEWIRE : integer range 0 to 2 := c_YES;
+ BROADCAST_SPECIAL_ADDR : std_logic_vector(7 downto 0) := x"FF";
+ --media interfaces
+ MII_NUMBER : integer range 2 to c_MAX_MII_PER_HUB := 12;
+ MII_IS_UPLINK : hub_mii_config_t := (others => c_YES);
+ MII_IS_DOWNLINK : hub_mii_config_t := (others => c_YES);
+ MII_IS_UPLINK_ONLY : hub_mii_config_t := (others => c_NO)
+ );
+
+ port(
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+
+ --Media Interface
+ MED_DATAREADY_OUT : out std_logic_vector (MII_NUMBER-1 downto 0);
+ MED_DATA_OUT : out std_logic_vector (MII_NUMBER*c_DATA_WIDTH-1 downto 0);
+ MED_PACKET_NUM_OUT : out std_logic_vector (MII_NUMBER*c_NUM_WIDTH-1 downto 0);
+ MED_READ_IN : in std_logic_vector (MII_NUMBER-1 downto 0);
+ MED_DATAREADY_IN : in std_logic_vector (MII_NUMBER-1 downto 0);
+ MED_DATA_IN : in std_logic_vector (MII_NUMBER*c_DATA_WIDTH-1 downto 0);
+ MED_PACKET_NUM_IN : in std_logic_vector (MII_NUMBER*c_NUM_WIDTH-1 downto 0);
+ MED_READ_OUT : out std_logic_vector (MII_NUMBER-1 downto 0);
+ MED_STAT_OP : in std_logic_vector (MII_NUMBER*16-1 downto 0);
+ MED_CTRL_OP : out std_logic_vector (MII_NUMBER*16-1 downto 0);
+
+ --Event information coming from CTS
+ CTS_NUMBER_OUT : out std_logic_vector (15 downto 0);
+ CTS_CODE_OUT : out std_logic_vector (7 downto 0);
+ CTS_INFORMATION_OUT : out std_logic_vector (7 downto 0);
+ CTS_READOUT_TYPE_OUT : out std_logic_vector (3 downto 0);
+ CTS_START_READOUT_OUT : out std_logic;
+
+ --Information sent to CTS
+ --status data, equipped with DHDR
+ CTS_DATA_IN : in std_logic_vector (31 downto 0);
+ CTS_DATAREADY_IN : in std_logic;
+ CTS_READOUT_FINISHED_IN : in std_logic; --no more data, end transfer, send TRM
+ CTS_READ_OUT : out std_logic;
+ CTS_LENGTH_IN : in std_logic_vector (15 downto 0);
+ CTS_STATUS_BITS_IN : in std_logic_vector (31 downto 0);
+
+ -- Data from Frontends
+ FEE_DATA_OUT : out std_logic_vector (15 downto 0);
+ FEE_DATAREADY_OUT : out std_logic;
+ FEE_READ_IN : in std_logic; --must be high when idle, otherwise you will never get a dataready
+ FEE_STATUS_BITS_OUT : out std_logic_vector (31 downto 0);
+ FEE_BUSY_OUT : out std_logic;
+
+ MY_ADDRESS_IN : in std_logic_vector (15 downto 0);
+
+ COMMON_STAT_REGS : out std_logic_vector (std_COMSTATREG*32-1 downto 0); --Status of common STAT regs
+ COMMON_CTRL_REGS : out std_logic_vector (std_COMCTRLREG*32-1 downto 0); --Status of common STAT regs
+ ONEWIRE : inout std_logic;
+ ONEWIRE_MONITOR_IN : in std_logic;
+ ONEWIRE_MONITOR_OUT : out std_logic;
+ MY_ADDRESS_OUT : out std_logic_vector(15 downto 0);
+ UNIQUE_ID_OUT : out std_logic_vector (63 downto 0);
+
+ --REGIO INTERFACE
+ REGIO_ADDR_OUT : out std_logic_vector(16-1 downto 0);
+ REGIO_READ_ENABLE_OUT : out std_logic;
+ REGIO_WRITE_ENABLE_OUT : out std_logic;
+ REGIO_DATA_OUT : out std_logic_vector(32-1 downto 0);
+ REGIO_DATA_IN : in std_logic_vector(32-1 downto 0) := (others => '0');
+ REGIO_DATAREADY_IN : in std_logic := '0';
+ REGIO_NO_MORE_DATA_IN : in std_logic := '0';
+ REGIO_WRITE_ACK_IN : in std_logic := '0';
+ REGIO_UNKNOWN_ADDR_IN : in std_logic := '0';
+ REGIO_TIMEOUT_OUT : out std_logic;
+
+
+ --Gbe Sctrl Input
+ GSC_INIT_DATAREADY_IN : in std_logic;
+ GSC_INIT_DATA_IN : in std_logic_vector(15 downto 0);
+ GSC_INIT_PACKET_NUM_IN : in std_logic_vector(2 downto 0);
+ GSC_INIT_READ_OUT : out std_logic;
+ GSC_REPLY_DATAREADY_OUT : out std_logic;
+ GSC_REPLY_DATA_OUT : out std_logic_vector(15 downto 0);
+ GSC_REPLY_PACKET_NUM_OUT : out std_logic_vector(2 downto 0);
+ GSC_REPLY_READ_IN : in std_logic;
+ GSC_BUSY_OUT : out std_logic;
+
+ --status and control ports
+ HUB_STAT_CHANNEL : out std_logic_vector (2**(c_MUX_WIDTH-1)*16-1 downto 0);
+ HUB_STAT_GEN : out std_logic_vector (31 downto 0);
+ MPLEX_CTRL : in std_logic_vector (MII_NUMBER*32-1 downto 0);
+ MPLEX_STAT : out std_logic_vector (MII_NUMBER*32-1 downto 0);
+ STAT_REGS : out std_logic_vector (8*32-1 downto 0); --Status of custom STAT regs
+ STAT_CTRL_REGS : out std_logic_vector (8*32-1 downto 0); --Status of custom CTRL regs
+ --Debugging registers
+ STAT_DEBUG : out std_logic_vector (31 downto 0); --free status regs for debugging
+ CTRL_DEBUG : in std_logic_vector (31 downto 0) --free control regs for debugging
+ );
+end component;
+
signal CLK : std_logic;
signal RESET : std_logic;
signal LINK_OK_IN : std_logic;
signal pc_ready, pc_sos, pc_transmit_on, pc_wr_en, pc_sod, pc_eod, pc_fc_h_ready, pc_fc_ready : std_logic;
signal pc_data : std_logic_vector(7 downto 0);
signal pc_ip_size, pc_udp_size : std_logic_vector(15 downto 0);
+signal gsc_init_read, gsc_init_dataready : std_logic;
+signal gsc_reply_read, gsc_reply_dataready : std_logic;
+signal gsc_reply_data, gsc_init_data : std_logic_vector(15 downto 0);
+signal gsc_busy : std_logic;
+signal gsc_init_packet_num, gsc_reply_packet_num : std_logic_vector(2 downto 0);
begin
+HUB_STR : trb_net16_hub_streaming_port_sctrl
+ generic map(
+ --media interfaces
+ MII_NUMBER => 5,
+ MII_IS_UPLINK => (0,0,0,0,1,0,1,0,0,0,0,0,0,0,0,0,0),
+ MII_IS_DOWNLINK => (1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0),
+ MII_IS_UPLINK_ONLY => (0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0)
+ )
+ port map(
+ CLK => CLK,
+ RESET => RESET,
+ CLK_EN => '1',
+
+ --Media Interface
+ MED_DATAREADY_OUT => open,
+ MED_DATA_OUT => open,
+ MED_PACKET_NUM_OUT => open,
+ MED_READ_IN => (others => '0'),
+ MED_DATAREADY_IN => (others => '0'),
+ MED_DATA_IN => (others => '0'),
+ MED_PACKET_NUM_IN => (others => '0'),
+ MED_READ_OUT => open,
+ MED_STAT_OP => x"0007_0007_0007_0007_0007",
+ MED_CTRL_OP => open,
+
+ --Event information coming from CTS
+ CTS_NUMBER_OUT => open,
+ CTS_CODE_OUT => open,
+ CTS_INFORMATION_OUT => open,
+ CTS_READOUT_TYPE_OUT => open,
+ CTS_START_READOUT_OUT => open,
+
+ --Information sent to CTS
+ --status data, equipped with DHDR
+ CTS_DATA_IN => (others => '0'),
+ CTS_DATAREADY_IN => '0',
+ CTS_READOUT_FINISHED_IN => '0',
+ CTS_READ_OUT => open,
+ CTS_LENGTH_IN => (others => '0'),
+ CTS_STATUS_BITS_IN => (others => '0'),
+
+ -- Data from Frontends
+ FEE_DATA_OUT => open,
+ FEE_DATAREADY_OUT => open,
+ FEE_READ_IN => '0',
+ FEE_STATUS_BITS_OUT => open,
+ FEE_BUSY_OUT => open,
+
+ MY_ADDRESS_IN => (others => '0'),
+
+ COMMON_STAT_REGS => open,
+ COMMON_CTRL_REGS => open,
+ ONEWIRE => open,
+ ONEWIRE_MONITOR_IN => '0',
+ ONEWIRE_MONITOR_OUT => open,
+ MY_ADDRESS_OUT => open,
+ UNIQUE_ID_OUT => open,
+
+ --REGIO INTERFACE
+ REGIO_ADDR_OUT => open,
+ REGIO_READ_ENABLE_OUT => open,
+ REGIO_WRITE_ENABLE_OUT => open,
+ REGIO_DATA_OUT => open,
+ REGIO_DATA_IN => (others => '0'),
+ REGIO_DATAREADY_IN => '0',
+ REGIO_NO_MORE_DATA_IN => '0',
+ REGIO_WRITE_ACK_IN => '0',
+ REGIO_UNKNOWN_ADDR_IN => '0',
+ REGIO_TIMEOUT_OUT => open,
+
+
+ --Gbe Sctrl Input
+ GSC_INIT_DATAREADY_IN => gsc_init_dataready,
+ GSC_INIT_DATA_IN => gsc_init_data,
+ GSC_INIT_PACKET_NUM_IN => gsc_init_packet_num,
+ GSC_INIT_READ_OUT => gsc_init_read,
+ GSC_REPLY_DATAREADY_OUT => gsc_reply_dataready,
+ GSC_REPLY_DATA_OUT => gsc_reply_data,
+ GSC_REPLY_PACKET_NUM_OUT => gsc_reply_packet_num,
+ GSC_REPLY_READ_IN => gsc_reply_read,
+ GSC_BUSY_OUT => gsc_busy,
+
+ --status and control ports
+ HUB_STAT_CHANNEL => open,
+ HUB_STAT_GEN => open,
+ MPLEX_CTRL => (others => '0'),
+ MPLEX_STAT => open,
+ STAT_REGS => open,
+ STAT_CTRL_REGS => open,
+ --Debugging registers
+ STAT_DEBUG => open,
+ CTRL_DEBUG => (others => '0')
+ );
+
packet_constr : trb_net16_gbe_packet_constr
port map(
RESET => RESET,
PCS_AN_COMPLETE_IN => '1',
-- signals to/from hub
+ MC_UNIQUE_ID_IN => (others => '0'),
+
+ GSC_CLK_IN => CLK,
+ GSC_INIT_DATAREADY_OUT => gsc_init_dataready,
+ GSC_INIT_DATA_OUT => gsc_init_data,
+ GSC_INIT_PACKET_NUM_OUT => gsc_init_packet_num,
+ GSC_INIT_READ_IN => gsc_init_read,
+ GSC_REPLY_DATAREADY_IN => gsc_reply_dataready,
+ GSC_REPLY_DATA_IN => gsc_reply_data,
+ GSC_REPLY_PACKET_NUM_IN => gsc_reply_packet_num,
+ GSC_REPLY_READ_OUT => gsc_reply_read,
+ GSC_BUSY_IN => gsc_busy,
-- signal to/from Host interface of TriSpeed MAC
TSM_HADDR_OUT => open,
end if;
end process CHECK_PROC;
+
TESTBENCH_PROC : process
variable seed1 : positive; -- seed for random generator
fr_allowed_udp <= x"0000_000f";
additional_rand_pause <= '0';
pc_sos <= '0';
-
+-- gsc_init_read <= '0';
+-- gsc_busy <= '0';
+-- gsc_reply_data <= (others => '0');
+-- gsc_reply_dataready <= '0';
+--
wait for 10 ns;
RESET <= '0';
wait for 50 ns;
- wait for 1000 ns;
-
--for i in 0 to 1000 loop
- wait for 700 ns;
+ wait for 200 ns;
+
+ -- FIRST FRAME UDP - SCTRL READ REQUEST
+ wait until rising_edge(RX_MAC_CLK);
+ MAC_RX_EN_IN <= '1';
+-- dest mac
+ MAC_RXD_IN <= x"00";
+ wait until rising_edge(RX_MAC_CLK);
+ MAC_RXD_IN <= x"00";
+ wait until rising_edge(RX_MAC_CLK);
+ MAC_RXD_IN <= x"be";
+ wait until rising_edge(RX_MAC_CLK);
+ MAC_RXD_IN <= x"ef";
+ wait until rising_edge(RX_MAC_CLK);
+ MAC_RXD_IN <= x"be";
+ wait until rising_edge(RX_MAC_CLK);
+ MAC_RXD_IN <= x"ef";
+ wait until rising_edge(RX_MAC_CLK);
+-- src mac
+ MAC_RXD_IN <= x"00";
+ wait until rising_edge(RX_MAC_CLK);
+ MAC_RXD_IN <= x"aa";
+ wait until rising_edge(RX_MAC_CLK);
+ MAC_RXD_IN <= x"bb";
+ wait until rising_edge(RX_MAC_CLK);
+ MAC_RXD_IN <= x"cc";
+ wait until rising_edge(RX_MAC_CLK);
+ MAC_RXD_IN <= x"dd";
+ wait until rising_edge(RX_MAC_CLK);
+ MAC_RXD_IN <= x"ee";
+ wait until rising_edge(RX_MAC_CLK);
+-- frame type
+ MAC_RXD_IN <= x"08";
+ wait until rising_edge(RX_MAC_CLK);
+ MAC_RXD_IN <= x"00";
+ wait until rising_edge(RX_MAC_CLK);
+-- ip headers
+ MAC_RXD_IN <= x"45";
+ wait until rising_edge(RX_MAC_CLK);
+ MAC_RXD_IN <= x"10";
+ wait until rising_edge(RX_MAC_CLK);
+ MAC_RXD_IN <= x"01";
+ wait until rising_edge(RX_MAC_CLK);
+ MAC_RXD_IN <= x"5a";
+ wait until rising_edge(RX_MAC_CLK);
+ MAC_RXD_IN <= x"49";
+ wait until rising_edge(RX_MAC_CLK);
+ MAC_RXD_IN <= x"00";
+ wait until rising_edge(RX_MAC_CLK);
+ MAC_RXD_IN <= x"00";
+ wait until rising_edge(RX_MAC_CLK);
+ MAC_RXD_IN <= x"00";
+ wait until rising_edge(RX_MAC_CLK);
+ MAC_RXD_IN <= x"ff";
+ wait until rising_edge(RX_MAC_CLK);
+ MAC_RXD_IN <= x"11"; -- udp
+ wait until rising_edge(RX_MAC_CLK);
+ MAC_RXD_IN <= x"cc";
+ wait until rising_edge(RX_MAC_CLK);
+ MAC_RXD_IN <= x"cc";
+ wait until rising_edge(RX_MAC_CLK);
+ MAC_RXD_IN <= x"c0";
+ wait until rising_edge(RX_MAC_CLK);
+ MAC_RXD_IN <= x"a8";
+ wait until rising_edge(RX_MAC_CLK);
+ MAC_RXD_IN <= x"00";
+ wait until rising_edge(RX_MAC_CLK);
+ MAC_RXD_IN <= x"01";
+ wait until rising_edge(RX_MAC_CLK);
+ MAC_RXD_IN <= x"c0";
+ wait until rising_edge(RX_MAC_CLK);
+ MAC_RXD_IN <= x"a8";
+ wait until rising_edge(RX_MAC_CLK);
+ MAC_RXD_IN <= x"00";
+ wait until rising_edge(RX_MAC_CLK);
+ MAC_RXD_IN <= x"02";
+-- udp headers
+ wait until rising_edge(RX_MAC_CLK);
+ MAC_RXD_IN <= x"00";
+ wait until rising_edge(RX_MAC_CLK);
+ MAC_RXD_IN <= x"43";
+ wait until rising_edge(RX_MAC_CLK);
+ MAC_RXD_IN <= x"61";
+ wait until rising_edge(RX_MAC_CLK);
+ MAC_RXD_IN <= x"a8";
+ wait until rising_edge(RX_MAC_CLK);
+ MAC_RXD_IN <= x"02";
+ wait until rising_edge(RX_MAC_CLK);
+ MAC_RXD_IN <= x"2c";
+ wait until rising_edge(RX_MAC_CLK);
+ MAC_RXD_IN <= x"aa";
+ wait until rising_edge(RX_MAC_CLK);
+ MAC_RXD_IN <= x"bb";
+-- sctrl data
+ wait until rising_edge(RX_MAC_CLK);
+ MAC_RXD_IN <= x"00";
+ wait until rising_edge(RX_MAC_CLK);
+ MAC_RXD_IN <= x"31";
+ wait until rising_edge(RX_MAC_CLK);
+ MAC_RXD_IN <= x"ff";
+ wait until rising_edge(RX_MAC_CLK);
+ MAC_RXD_IN <= x"ff";
+ wait until rising_edge(RX_MAC_CLK);
+ MAC_RXD_IN <= x"ff";
+ wait until rising_edge(RX_MAC_CLK);
+ MAC_RXD_IN <= x"ff";
+ wait until rising_edge(RX_MAC_CLK);
+ MAC_RXD_IN <= x"ff";
+ wait until rising_edge(RX_MAC_CLK);
+ MAC_RXD_IN <= x"ff";
+ wait until rising_edge(RX_MAC_CLK);
+ MAC_RXD_IN <= x"00";
+ wait until rising_edge(RX_MAC_CLK);
+ MAC_RXD_IN <= x"08";
+ wait until rising_edge(RX_MAC_CLK);
+ MAC_RXD_IN <= x"00";
+ wait until rising_edge(RX_MAC_CLK);
+ MAC_RXD_IN <= x"30";
+ wait until rising_edge(RX_MAC_CLK);
+ MAC_RXD_IN <= x"00";
+ wait until rising_edge(RX_MAC_CLK);
+ MAC_RXD_IN <= x"00";
+ wait until rising_edge(RX_MAC_CLK);
+ MAC_RXD_IN <= x"00";
+ wait until rising_edge(RX_MAC_CLK);
+ MAC_RXD_IN <= x"50";
+ wait until rising_edge(RX_MAC_CLK);
+ MAC_RXD_IN <= x"af";
+ wait until rising_edge(RX_MAC_CLK);
+ MAC_RXD_IN <= x"fe";
+ wait until rising_edge(RX_MAC_CLK);
+ MAC_RXD_IN <= x"de";
+ wait until rising_edge(RX_MAC_CLK);
+ MAC_RXD_IN <= x"ad";
+ wait until rising_edge(RX_MAC_CLK);
+ MAC_RXD_IN <= x"00";
+ wait until rising_edge(RX_MAC_CLK);
+ MAC_RXD_IN <= x"33";
+ wait until rising_edge(RX_MAC_CLK);
+ MAC_RXD_IN <= x"00";
+ wait until rising_edge(RX_MAC_CLK);
+ MAC_RXD_IN <= x"00";
+ wait until rising_edge(RX_MAC_CLK);
+ MAC_RXD_IN <= x"00";
+ wait until rising_edge(RX_MAC_CLK);
+ MAC_RXD_IN <= x"00";
+ wait until rising_edge(RX_MAC_CLK);
+ MAC_RXD_IN <= x"00";
+ wait until rising_edge(RX_MAC_CLK);
+ MAC_RXD_IN <= x"00";
+ wait until rising_edge(RX_MAC_CLK);
+ MAC_RXD_IN <= x"00";
+ wait until rising_edge(RX_MAC_CLK);
+ MAC_RXD_IN <= x"08";
+ MAC_RX_EOF_IN <= '1';
+ wait until rising_edge(RX_MAC_CLK);
+
+ MAC_RX_EN_IN <='0';
+ MAC_RX_EOF_IN <= '0';
+
+
+-- wait until rising_edge(gsc_init_dataready);
+-- wait until rising_edge(CLK);
+-- gsc_init_read <= '1';
+--
+-- wait until falling_edge(gsc_init_dataready);
+-- wait until rising_edge(CLK);
+-- gsc_init_read <= '0';
+--
+-- --wait for 100 ns;
+-- --wait until rising_edge(gsc_reply_read);
+-- wait until rising_edge(CLK);
+-- wait until rising_edge(CLK);
+-- wait until rising_edge(CLK);
+-- wait until rising_edge(CLK);
+-- gsc_reply_data <= x"0101";
+-- gsc_reply_dataready <= '1';
+-- wait until rising_edge(CLK);
+-- gsc_reply_data <= x"0202";
+-- wait until rising_edge(CLK);
+-- gsc_reply_data <= x"0303";
+-- wait until rising_edge(CLK);
+-- gsc_reply_data <= x"0404";
+-- wait until rising_edge(CLK);
+-- gsc_reply_data <= x"0505";
+-- wait until rising_edge(CLK);
+-- gsc_reply_data <= x"0606";
+-- wait until rising_edge(CLK);
+-- gsc_reply_data <= x"0707";
+-- wait until rising_edge(CLK);
+-- gsc_reply_data <= x"0808";
+-- wait until rising_edge(CLK);
+-- gsc_reply_dataready <= '0';
+
+
+ -- STOP HERE
+ wait;
+
+
-- FIRST FRAME (ARP Request)
wait until rising_edge(RX_MAC_CLK);
MAC_RX_EN_IN <= '1';
SFP_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
SFP_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
SFP_TXDIS_OUT : out std_logic; -- SFP disable
+
+ -- interface between main_controller and hub logic
+ MC_UNIQUE_ID_IN : in std_logic_vector(63 downto 0);
+ GSC_CLK_IN : in std_logic;
+ GSC_INIT_DATAREADY_OUT : out std_logic;
+ GSC_INIT_DATA_OUT : out std_logic_vector(15 downto 0);
+ GSC_INIT_PACKET_NUM_OUT : out std_logic_vector(2 downto 0);
+ GSC_INIT_READ_IN : in std_logic;
+ GSC_REPLY_DATAREADY_IN : in std_logic;
+ GSC_REPLY_DATA_IN : in std_logic_vector(15 downto 0);
+ GSC_REPLY_PACKET_NUM_IN : in std_logic_vector(2 downto 0);
+ GSC_REPLY_READ_OUT : out std_logic;
+ GSC_BUSY_IN : in std_logic;
-- for simulation of receiving part only
MAC_RX_EOF_IN : in std_logic;
signal fr_ip_proto : std_logic_vector(7 downto 0);
signal mc_ip_proto : std_logic_vector(7 downto 0);
+attribute syn_preserve : boolean;
+attribute syn_keep : boolean;
+attribute syn_keep of pcs_rxd, pcs_txd, pcs_rx_en, pcs_tx_en, pcs_rx_er, pcs_tx_er : signal is true;
+attribute syn_preserve of pcs_rxd, pcs_txd, pcs_rx_en, pcs_tx_en, pcs_rx_er, pcs_tx_er : signal is true;
+
+signal pcs_txd_q, pcs_rxd_q : std_logic_vector(7 downto 0);
+signal pcs_tx_en_q, pcs_tx_er_q, pcs_rx_en_q, pcs_rx_er_q, mac_col_q, mac_crs_q : std_logic;
+
+signal pcs_txd_qq, pcs_rxd_qq : std_logic_vector(7 downto 0);
+signal pcs_tx_en_qq, pcs_tx_er_qq, pcs_rx_en_qq, pcs_rx_er_qq, mac_col_qq, mac_crs_qq : std_logic;
+
begin
--my_mac <= x"efbeefbe0000"; -- temporary
fc_ttl <= x"ff";
--fc_protocol <= x"11";
---
--- MAIN_CONTROL : trb_net16_gbe_main_control
--- port map(
--- CLK => CLK,
--- CLK_125 => serdes_clk_125,
--- RESET => RESET,
---
--- MC_LINK_OK_OUT => link_ok,
--- MC_RESET_LINK_IN => MR_RESTART_IN,
---
--- -- signals to/from receive controller
--- RC_FRAME_WAITING_IN => rc_frame_ready,
--- RC_LOADING_DONE_OUT => rc_loading_done,
--- RC_DATA_IN => rc_q,
--- RC_RD_EN_OUT => rc_rd_en,
--- RC_FRAME_SIZE_IN => rc_frame_size,
--- RC_FRAME_PROTO_IN => rc_frame_proto,
---
--- RC_SRC_MAC_ADDRESS_IN => rc_src_mac,
--- RC_DEST_MAC_ADDRESS_IN => rc_dest_mac,
--- RC_SRC_IP_ADDRESS_IN => rc_src_ip,
--- RC_DEST_IP_ADDRESS_IN => rc_dest_ip,
--- RC_SRC_UDP_PORT_IN => rc_src_udp,
--- RC_DEST_UDP_PORT_IN => rc_dest_udp,
---
--- -- signals to/from transmit controller
--- TC_TRANSMIT_CTRL_OUT => mc_transmit_ctrl,
--- TC_TRANSMIT_DATA_OUT => mc_transmit_data,
--- TC_DATA_OUT => mc_data,
--- TC_RD_EN_IN => mc_rd_en,
--- TC_FRAME_SIZE_OUT => mc_frame_size,
--- TC_FRAME_TYPE_OUT => mc_type,
--- TC_IP_PROTOCOL_OUT => mc_ip_proto,
---
--- TC_DEST_MAC_OUT => mc_dest_mac,
--- TC_DEST_IP_OUT => mc_dest_ip,
--- TC_DEST_UDP_OUT => mc_dest_udp,
--- TC_SRC_MAC_OUT => mc_src_mac,
--- TC_SRC_IP_OUT => mc_src_ip,
--- TC_SRC_UDP_OUT => mc_src_udp,
---
--- TC_BUSY_IN => mc_busy,
--- TC_TRANSMIT_DONE_IN => mc_transmit_done,
---
--- -- signals to/from packet constructor
--- PC_READY_IN => pc_ready,
--- PC_TRANSMIT_ON_IN => pc_transmit_on,
--- PC_SOD_IN => tc_sod,
---
--- -- signals to/from sgmii/gbe pcs_an_complete
--- PCS_AN_COMPLETE_IN => pcs_an_complete,
---
--- -- signals to/from hub
---
---
--- -- signal to/from Host interface of TriSpeed MAC
--- TSM_HADDR_OUT => mac_haddr,
--- TSM_HDATA_OUT => mac_hdataout,
--- TSM_HCS_N_OUT => mac_hcs,
--- TSM_HWRITE_N_OUT => mac_hwrite,
--- TSM_HREAD_N_OUT => mac_hread,
--- TSM_HREADY_N_IN => mac_hready,
--- TSM_HDATA_EN_N_IN => mac_hdata_en,
---
--- SELECT_REC_FRAMES_OUT => dbg_select_rec,
--- SELECT_SENT_FRAMES_OUT => dbg_select_sent,
--- SELECT_PROTOS_DEBUG_OUT => dbg_select_protos,
---
--- DEBUG_OUT => dbg_mc
--- );
---
---
--- TRANSMIT_CONTROLLER : trb_net16_gbe_transmit_control
--- port map(
--- CLK => CLK,
--- RESET => RESET,
---
--- -- signals to/from packet constructor
--- PC_READY_IN => pc_ready,
--- PC_DATA_IN => tc_data,
--- PC_WR_EN_IN => tc_wr_en,
--- PC_IP_SIZE_IN => tc_ip_size,
--- PC_UDP_SIZE_IN => tc_udp_size,
--- PC_FLAGS_OFFSET_IN => tc_flags_offset,
--- PC_SOD_IN => tc_sod,
--- PC_EOD_IN => tc_eod,
--- PC_FC_READY_OUT => tc_pc_ready,
--- PC_FC_H_READY_OUT => tc_pc_h_ready,
--- PC_TRANSMIT_ON_IN => pc_transmit_on,
---
--- -- signals from ip_configurator used by packet constructor
--- IC_DEST_MAC_ADDRESS_IN => ic_dest_mac,
--- IC_DEST_IP_ADDRESS_IN => ic_dest_ip,
--- IC_DEST_UDP_PORT_IN => ic_dest_udp,
--- IC_SRC_MAC_ADDRESS_IN => ic_src_mac,
--- IC_SRC_IP_ADDRESS_IN => ic_src_ip,
--- IC_SRC_UDP_PORT_IN => ic_src_udp,
---
--- -- signal to/from main controller
--- MC_TRANSMIT_CTRL_IN => mc_transmit_ctrl,
--- MC_TRANSMIT_DATA_IN => mc_transmit_data,
--- MC_DATA_IN => mc_data,
--- MC_RD_EN_OUT => mc_rd_en,
--- MC_FRAME_SIZE_IN => mc_frame_size,
--- MC_FRAME_TYPE_IN => mc_type,
--- MC_IP_PROTOCOL_IN => mc_ip_proto,
---
--- MC_DEST_MAC_IN => mc_dest_mac,
--- MC_DEST_IP_IN => mc_dest_ip,
--- MC_DEST_UDP_IN => mc_dest_udp,
--- MC_SRC_MAC_IN => mc_src_mac,
--- MC_SRC_IP_IN => mc_src_ip,
--- MC_SRC_UDP_IN => mc_src_udp,
---
--- MC_BUSY_OUT => mc_busy,
--- MC_TRANSMIT_DONE_OUT => mc_transmit_done,
---
--- -- signal to/from frame constructor
--- FC_DATA_OUT => fc_data,
--- FC_WR_EN_OUT => fc_wr_en,
--- FC_READY_IN => fc_ready,
--- FC_H_READY_IN => fc_h_ready,
--- FC_FRAME_TYPE_OUT => fc_type,
--- FC_IP_SIZE_OUT => fc_ip_size,
--- FC_UDP_SIZE_OUT => fc_udp_size,
--- FC_IDENT_OUT => fc_ident,
--- FC_FLAGS_OFFSET_OUT => fc_flags_offset,
--- FC_SOD_OUT => fc_sod,
--- FC_EOD_OUT => fc_eod,
--- FC_IP_PROTOCOL_OUT => fc_protocol,
---
--- DEST_MAC_ADDRESS_OUT => fc_dest_mac,
--- DEST_IP_ADDRESS_OUT => fc_dest_ip,
--- DEST_UDP_PORT_OUT => fc_dest_udp,
--- SRC_MAC_ADDRESS_OUT => fc_src_mac,
--- SRC_IP_ADDRESS_OUT => fc_src_ip,
--- SRC_UDP_PORT_OUT => fc_src_udp,
---
---
--- -- debug
--- DEBUG_OUT => dbg_tc
--- );
---
---
--- setup_imp_gen : if (DO_SIMULATION = 0) generate
--- -- gk 22.04.10 new entity to set values via slow control
--- SETUP : gbe_setup
--- port map(
--- CLK => CLK,
--- RESET => RESET,
---
--- -- gk 26.04.10
--- -- interface to regio bus
--- BUS_ADDR_IN => BUS_ADDR_IN,
--- BUS_DATA_IN => BUS_DATA_IN,
--- BUS_DATA_OUT => BUS_DATA_OUT,
--- BUS_WRITE_EN_IN => BUS_WRITE_EN_IN,
--- BUS_READ_EN_IN => BUS_READ_EN_IN,
--- BUS_ACK_OUT => BUS_ACK_OUT,
---
--- GBE_TRIG_NR_IN => pc_trig_nr, -- gk 26.04.10
---
--- -- output to gbe_buf
--- GBE_SUBEVENT_ID_OUT => pc_event_id,
--- GBE_SUBEVENT_DEC_OUT => pc_decoding,
--- GBE_QUEUE_DEC_OUT => pc_queue_dec,
--- GBE_MAX_PACKET_OUT => max_packet,
--- GBE_MIN_PACKET_OUT => min_packet, -- gk 20.07.10
--- GBE_MAX_FRAME_OUT => pc_max_frame_size,
--- GBE_USE_GBE_OUT => use_gbe,
--- GBE_USE_TRBNET_OUT => use_trbnet,
--- GBE_USE_MULTIEVENTS_OUT => use_multievents,
--- GBE_READOUT_CTR_OUT => readout_ctr, -- gk 26.04.10
--- GBE_READOUT_CTR_VALID_OUT => readout_ctr_valid, -- gk 26.04.10
--- GBE_DELAY_OUT => pc_delay,
--- GBE_ALLOW_LARGE_OUT => allow_large, -- gk 21.07.10
--- GBE_ALLOW_RX_OUT => allow_rx,
--- GBE_FRAME_DELAY_OUT => frame_delay, -- gk 09.12.10
--- GBE_ALLOWED_TYPES_OUT => fr_allowed_types,
--- GBE_ALLOWED_IP_OUT => fr_allowed_ip,
--- GBE_ALLOWED_UDP_OUT => fr_allowed_udp,
--- GBE_VLAN_ID_OUT => vlan_id,
--- -- gk 28.07.10
--- MONITOR_BYTES_IN => bytes_sent_ctr,
--- MONITOR_SENT_IN => monitor_sent,
--- MONITOR_DROPPED_IN => monitor_dropped,
--- MONITOR_SM_IN => monitor_sm,
--- MONITOR_LR_IN => monitor_lr,
--- MONITOR_HDR_IN => monitor_hr,
--- MONITOR_FIFOS_IN => monitor_fifos_q,
--- MONITOR_DISCFRM_IN => monitor_discfrm,
--- MONITOR_EMPTY_IN => monitor_empty,
--- MONITOR_LINK_DWN_IN(15 downto 0) => link_down_ctr, -- gk 30.09.10
--- MONITOR_LINK_DWN_IN(19 downto 16) => link_state,
--- MONITOR_LINK_DWN_IN(23 downto 20) => ft_bsm_trans,
--- MONITOR_LINK_DWN_IN(27 downto 24) => fc_bsm_trans,
--- MONITOR_LINK_DWN_IN(31 downto 28) => (others => '0'),
--- MONITOR_RX_FRAMES_IN => rc_frames_rec_ctr,
--- MONITOR_RX_BYTES_IN => rc_bytes_rec,
--- MONITOR_RX_BYTES_R_IN => rc_debug(31 downto 0),
--- -- gk 01.06.10
--- DBG_IPU2GBE1_IN => dbg_ipu2gbe1,
--- DBG_IPU2GBE2_IN => dbg_ipu2gbe2,
--- DBG_IPU2GBE3_IN => dbg_ipu2gbe3,
--- DBG_IPU2GBE4_IN => dbg_ipu2gbe4,
--- DBG_IPU2GBE5_IN => dbg_ipu2gbe5,
--- DBG_IPU2GBE6_IN => dbg_ipu2gbe6,
--- DBG_IPU2GBE7_IN => dbg_ipu2gbe7,
--- DBG_IPU2GBE8_IN => dbg_ipu2gbe8,
--- DBG_IPU2GBE9_IN => dbg_ipu2gbe9,
--- DBG_IPU2GBE10_IN => dbg_ipu2gbe10,
--- DBG_IPU2GBE11_IN => dbg_ipu2gbe11,
--- DBG_IPU2GBE12_IN => dbg_ipu2gbe12,
--- DBG_PC1_IN => dbg_pc1,
--- DBG_PC2_IN => dbg_pc2,
--- DBG_FC1_IN => dbg_fc1,
--- DBG_FC2_IN => dbg_fc2,
--- DBG_FT1_IN => dbg_ft1,
--- DBG_FT2_IN => dbg_ft(31 downto 0),
--- DBG_FR_IN => dbg_fr,
--- DBG_RC_IN => dbg_rc,
--- DBG_MC_IN => dbg_mc,
--- DBG_TC_IN => dbg_tc(31 downto 0),
--- DBG_FIFO_RD_EN_OUT => dbg_rd_en,
---
--- DBG_SELECT_REC_IN => dbg_select_rec,
--- DBG_SELECT_SENT_IN => dbg_select_sent,
--- DBG_SELECT_PROTOS_IN => dbg_select_protos,
---
--- DBG_FIFO_Q_IN => dbg_q
---
--- --DBG_FIFO_RESET_OUT => dbg_reset_fifo -- gk 28.09.10
--- );
--- end generate;
---
--- setup_sim_gen : if (DO_SIMULATION = 1) generate
--- -- gk 22.04.10 new entity to set values via slow control
--- SETUP : gbe_setup
--- port map(
--- CLK => CLK,
--- RESET => RESET,
---
--- -- gk 26.04.10
--- -- interface to regio bus
--- BUS_ADDR_IN => BUS_ADDR_IN,
--- BUS_DATA_IN => BUS_DATA_IN,
--- BUS_DATA_OUT => BUS_DATA_OUT,
--- BUS_WRITE_EN_IN => BUS_WRITE_EN_IN,
--- BUS_READ_EN_IN => BUS_READ_EN_IN,
--- BUS_ACK_OUT => BUS_ACK_OUT,
---
--- GBE_TRIG_NR_IN => pc_trig_nr, -- gk 26.04.10
---
--- -- output to gbe_buf
--- GBE_SUBEVENT_ID_OUT => pc_event_id,
--- GBE_SUBEVENT_DEC_OUT => pc_decoding,
--- GBE_QUEUE_DEC_OUT => pc_queue_dec,
--- GBE_MAX_PACKET_OUT => max_packet,
--- GBE_MIN_PACKET_OUT => min_packet, -- gk 20.07.10
--- GBE_MAX_FRAME_OUT => pc_max_frame_size,
--- GBE_USE_GBE_OUT => use_gbe,
--- GBE_USE_TRBNET_OUT => use_trbnet,
--- GBE_USE_MULTIEVENTS_OUT => use_multievents,
--- GBE_READOUT_CTR_OUT => readout_ctr, -- gk 26.04.10
--- GBE_READOUT_CTR_VALID_OUT => readout_ctr_valid, -- gk 26.04.10
--- GBE_DELAY_OUT => pc_delay,
--- GBE_ALLOW_LARGE_OUT => open,
--- GBE_ALLOW_RX_OUT => open,
--- GBE_FRAME_DELAY_OUT => frame_delay, -- gk 09.12.10
--- GBE_ALLOWED_TYPES_OUT => fr_allowed_types,
--- GBE_ALLOWED_IP_OUT => fr_allowed_ip,
--- GBE_ALLOWED_UDP_OUT => fr_allowed_udp,
--- GBE_VLAN_ID_OUT => vlan_id,
--- -- gk 28.07.10
--- MONITOR_BYTES_IN => bytes_sent_ctr,
--- MONITOR_SENT_IN => monitor_sent,
--- MONITOR_DROPPED_IN => monitor_dropped,
--- MONITOR_SM_IN => monitor_sm,
--- MONITOR_LR_IN => monitor_lr,
--- MONITOR_HDR_IN => monitor_hr,
--- MONITOR_FIFOS_IN => monitor_fifos_q,
--- MONITOR_DISCFRM_IN => monitor_discfrm,
--- MONITOR_EMPTY_IN => monitor_empty,
--- MONITOR_LINK_DWN_IN(15 downto 0) => link_down_ctr, -- gk 30.09.10
--- MONITOR_LINK_DWN_IN(19 downto 16) => link_state,
--- MONITOR_LINK_DWN_IN(23 downto 20) => ft_bsm_trans,
--- MONITOR_LINK_DWN_IN(27 downto 24) => fc_bsm_trans,
--- MONITOR_LINK_DWN_IN(31 downto 28) => (others => '0'),
--- MONITOR_RX_FRAMES_IN => rc_frames_rec_ctr,
--- MONITOR_RX_BYTES_IN => rc_bytes_rec,
--- MONITOR_RX_BYTES_R_IN => rc_debug(31 downto 0),
--- -- gk 01.06.10
--- DBG_IPU2GBE1_IN => dbg_ipu2gbe1,
--- DBG_IPU2GBE2_IN => dbg_ipu2gbe2,
--- DBG_IPU2GBE3_IN => dbg_ipu2gbe3,
--- DBG_IPU2GBE4_IN => dbg_ipu2gbe4,
--- DBG_IPU2GBE5_IN => dbg_ipu2gbe5,
--- DBG_IPU2GBE6_IN => dbg_ipu2gbe6,
--- DBG_IPU2GBE7_IN => dbg_ipu2gbe7,
--- DBG_IPU2GBE8_IN => dbg_ipu2gbe8,
--- DBG_IPU2GBE9_IN => dbg_ipu2gbe9,
--- DBG_IPU2GBE10_IN => dbg_ipu2gbe10,
--- DBG_IPU2GBE11_IN => dbg_ipu2gbe11,
--- DBG_IPU2GBE12_IN => dbg_ipu2gbe12,
--- DBG_PC1_IN => dbg_pc1,
--- DBG_PC2_IN => dbg_pc2,
--- DBG_FC1_IN => dbg_fc1,
--- DBG_FC2_IN => dbg_fc2,
--- DBG_FT1_IN => dbg_ft1,
--- DBG_FT2_IN => dbg_ft(31 downto 0),
--- DBG_FR_IN => dbg_fr,
--- DBG_RC_IN => dbg_rc(31 downto 0),
--- DBG_MC_IN => dbg_mc,
--- DBG_TC_IN => dbg_tc(31 downto 0),
--- DBG_FIFO_RD_EN_OUT => dbg_rd_en,
---
--- DBG_SELECT_REC_IN => dbg_select_rec,
--- DBG_SELECT_SENT_IN => dbg_select_sent,
--- DBG_SELECT_PROTOS_IN => dbg_select_protos,
---
--- DBG_FIFO_Q_IN => dbg_q
--- --DBG_FIFO_RESET_OUT => dbg_reset_fifo -- gk 28.09.10
--- );
---
--- allow_rx <= '1';
--- allow_large <= '0';
---
--- end generate;
---
---
--- -- IP configurator: allows IP config to change for each event builder
--- THE_IP_CONFIGURATOR: ip_configurator
--- port map(
--- CLK => CLK,
--- RESET => RESET,
--- -- configuration interface
--- START_CONFIG_IN => ip_cfg_start, --IP_CFG_START_IN, -- new -- gk 7.03.10
--- BANK_SELECT_IN => ip_cfg_bank, --IP_CFG_BANK_SEL_IN, -- new -- gk 27.03.10
--- CONFIG_DONE_OUT => ip_cfg_done, --IP_CFG_DONE_OUT, -- new -- gk 27.03.10
--- MEM_ADDR_OUT => ip_cfg_mem_addr, --IP_CFG_MEM_ADDR_OUT, -- new -- gk 27.03.10
--- MEM_DATA_IN => ip_cfg_mem_data, --IP_CFG_MEM_DATA_IN, -- new -- gk 27.03.10
--- MEM_CLK_OUT => ip_cfg_mem_clk, --IP_CFG_MEM_CLK_OUT, -- new -- gk 27.03.10
--- -- information for IP cores
--- DEST_MAC_OUT => ic_dest_mac,
--- DEST_IP_OUT => ic_dest_ip,
--- DEST_UDP_OUT => ic_dest_udp,
--- SRC_MAC_OUT => ic_src_mac,
--- SRC_IP_OUT => ic_src_ip,
--- SRC_UDP_OUT => ic_src_udp,
--- MTU_OUT => open, --pc_max_frame_size, -- gk 22.04.10
--- -- Debug
--- DEBUG_OUT => open
--- );
---
--- -- gk 27.03.01
--- MB_IP_CONFIG: slv_mac_memory
--- port map(
--- CLK => CLK, -- clk_100,
--- RESET => RESET, --reset_i,
--- BUSY_IN => '0',
--- -- Slave bus
--- SLV_ADDR_IN => SLV_ADDR_IN, --x"00", --mb_ip_mem_addr(7 downto 0),
--- SLV_READ_IN => SLV_READ_IN, --'0', --mb_ip_mem_read,
--- SLV_WRITE_IN => SLV_WRITE_IN, --mb_ip_mem_write,
--- SLV_BUSY_OUT => SLV_BUSY_OUT,
--- SLV_ACK_OUT => SLV_ACK_OUT, --mb_ip_mem_ack,
--- SLV_DATA_IN => SLV_DATA_IN, --mb_ip_mem_data_wr,
--- SLV_DATA_OUT => SLV_DATA_OUT, --mb_ip_mem_data_rd,
--- -- I/O to the backend
--- MEM_CLK_IN => ip_cfg_mem_clk,
--- MEM_ADDR_IN => ip_cfg_mem_addr,
--- MEM_DATA_OUT => ip_cfg_mem_data,
--- -- Status lines
--- STAT => open
--- );
---
--- -- First stage: get data from IPU channel, buffer it and terminate the IPU transmission to CTS
--- THE_IPU_INTERFACE: trb_net16_ipu2gbe
--- port map(
--- CLK => CLK,
--- RESET => RESET,
--- --Event information coming from CTS
--- CTS_NUMBER_IN => CTS_NUMBER_IN,
--- CTS_CODE_IN => CTS_CODE_IN,
--- CTS_INFORMATION_IN => CTS_INFORMATION_IN,
--- CTS_READOUT_TYPE_IN => CTS_READOUT_TYPE_IN,
--- CTS_START_READOUT_IN => CTS_START_READOUT_IN,
--- --Information sent to CTS
--- --status data, equipped with DHDR
--- CTS_DATA_OUT => cts_data,
--- CTS_DATAREADY_OUT => cts_dataready,
--- CTS_READOUT_FINISHED_OUT => cts_readout_finished,
--- CTS_READ_IN => CTS_READ_IN,
--- CTS_LENGTH_OUT => cts_length,
--- CTS_ERROR_PATTERN_OUT => cts_error_pattern,
--- -- Data from Frontends
--- FEE_DATA_IN => FEE_DATA_IN,
--- FEE_DATAREADY_IN => FEE_DATAREADY_IN,
--- FEE_READ_OUT => fee_read,
--- FEE_STATUS_BITS_IN => FEE_STATUS_BITS_IN,
--- FEE_BUSY_IN => FEE_BUSY_IN,
--- -- slow control interface
--- START_CONFIG_OUT => ip_cfg_start, --open, --: out std_logic; -- reconfigure MACs/IPs/ports/packet size -- gk 27.03.10
--- BANK_SELECT_OUT => ip_cfg_bank, --open, --: out std_logic_vector(3 downto 0); -- configuration page address -- gk 27.03.10
--- CONFIG_DONE_IN => ip_cfg_done, --'1', --: in std_logic; -- configuration finished -- gk 27.03.10
--- DATA_GBE_ENABLE_IN => use_gbe, --'1', --: in std_logic; -- IPU data is forwarded to GbE -- gk 22.04.10
--- DATA_IPU_ENABLE_IN => use_trbnet, --'0', --: in std_logic; -- IPU data is forwarded to CTS / TRBnet -- gk 22.04.10
--- MULT_EVT_ENABLE_IN => use_multievents,
--- MAX_MESSAGE_SIZE_IN => max_packet, --x"0000_FDE8", -- gk 08.04.10 -- temporarily fixed here, to be set by slow ctrl -- gk 22.04.10
--- MIN_MESSAGE_SIZE_IN => min_packet, -- gk 20.07.10
--- READOUT_CTR_IN => readout_ctr, -- gk 26.04.10
--- READOUT_CTR_VALID_IN => readout_ctr_valid, -- gk 26.04.10
--- ALLOW_LARGE_IN => allow_large, -- gk 21.07.10
--- -- PacketConstructor interface
--- PC_WR_EN_OUT => pc_wr_en,
--- PC_DATA_OUT => pc_data,
--- PC_READY_IN => pc_ready,
--- PC_SOS_OUT => pc_sos,
--- PC_EOS_OUT => pc_eos, -- gk 07.10.10
--- PC_EOD_OUT => pc_eod,
--- PC_SUB_SIZE_OUT => pc_sub_size,
--- PC_TRIG_NR_OUT => pc_trig_nr,
--- PC_PADDING_OUT => pc_padding,
--- MONITOR_OUT(31 downto 0) => monitor_sent,
--- MONITOR_OUT(63 downto 32) => monitor_dropped,
--- MONITOR_OUT(95 downto 64) => monitor_hr,
--- MONITOR_OUT(127 downto 96) => monitor_sm,
--- MONITOR_OUT(159 downto 128) => monitor_lr,
--- MONITOR_OUT(191 downto 160) => monitor_fifos,
--- MONITOR_OUT(223 downto 192) => monitor_empty,
--- DEBUG_OUT(31 downto 0) => dbg_ipu2gbe1,
--- DEBUG_OUT(63 downto 32) => dbg_ipu2gbe2,
--- DEBUG_OUT(95 downto 64) => dbg_ipu2gbe3,
--- DEBUG_OUT(127 downto 96) => dbg_ipu2gbe4,
--- DEBUG_OUT(159 downto 128) => dbg_ipu2gbe5,
--- DEBUG_OUT(191 downto 160) => dbg_ipu2gbe6,
--- DEBUG_OUT(223 downto 192) => dbg_ipu2gbe7,
--- DEBUG_OUT(255 downto 224) => dbg_ipu2gbe8,
--- DEBUG_OUT(287 downto 256) => dbg_ipu2gbe9,
--- DEBUG_OUT(319 downto 288) => dbg_ipu2gbe10,
--- DEBUG_OUT(351 downto 320) => dbg_ipu2gbe11,
--- DEBUG_OUT(383 downto 352) => dbg_ipu2gbe12
--- );
---
--- -- Second stage: Packet constructor
--- PACKET_CONSTRUCTOR : trb_net16_gbe_packet_constr
--- port map(
--- -- ports for user logic
--- RESET => RESET,
--- CLK => CLK,
--- MULT_EVT_ENABLE_IN => use_multievents, -- gk 06.10.10
--- PC_WR_EN_IN => pc_wr_en,
--- PC_DATA_IN => pc_data,
--- PC_READY_OUT => pc_ready,
--- PC_START_OF_SUB_IN => dbg_rd_en, -- pc_sos, CHANGED TO SLOW CONTROL PULSE
--- PC_END_OF_SUB_IN => pc_eos, -- gk 07.10.10
--- PC_END_OF_DATA_IN => pc_eod,
--- PC_TRANSMIT_ON_OUT => pc_transmit_on,
--- -- queue and subevent layer headers
--- PC_SUB_SIZE_IN => pc_sub_size,
--- PC_PADDING_IN => pc_padding, -- gk 29.03.10
--- PC_DECODING_IN => pc_decoding,
--- PC_EVENT_ID_IN => pc_event_id,
--- PC_TRIG_NR_IN => pc_trig_nr,
--- PC_QUEUE_DEC_IN => pc_queue_dec,
--- PC_MAX_FRAME_SIZE_IN => pc_max_frame_size,
--- PC_DELAY_IN => pc_delay, -- gk 28.04.10
--- -- NEW PORTS
--- TC_WR_EN_OUT => tc_wr_en,
--- TC_DATA_OUT => tc_data,
--- TC_H_READY_IN => tc_pc_h_ready,
--- TC_READY_IN => tc_pc_ready,
--- TC_IP_SIZE_OUT => tc_ip_size,
--- TC_UDP_SIZE_OUT => tc_udp_size,
--- --FC_IDENT_OUT => fc_ident,
--- TC_FLAGS_OFFSET_OUT => tc_flags_offset,
--- TC_SOD_OUT => tc_sod,
--- TC_EOD_OUT => tc_eod,
--- DEBUG_OUT(31 downto 0) => dbg_pc1,
--- DEBUG_OUT(63 downto 32) => dbg_pc2
--- );
---
--- -- Third stage: Frame Constructor
--- FRAME_CONSTRUCTOR: trb_net16_gbe_frame_constr
--- port map(
--- -- ports for user logic
--- RESET => RESET,
--- CLK => CLK,
--- LINK_OK_IN => link_ok, --pcs_an_complete, -- gk 03.08.10 -- gk 30.09.10
--- --
--- WR_EN_IN => fc_wr_en,
--- DATA_IN => fc_data,
--- START_OF_DATA_IN => fc_sod,
--- END_OF_DATA_IN => fc_eod,
--- IP_F_SIZE_IN => fc_ip_size,
--- UDP_P_SIZE_IN => fc_udp_size,
--- HEADERS_READY_OUT => fc_h_ready,
--- READY_OUT => fc_ready,
--- DEST_MAC_ADDRESS_IN => fc_dest_mac,
--- DEST_IP_ADDRESS_IN => fc_dest_ip,
--- DEST_UDP_PORT_IN => fc_dest_udp,
--- SRC_MAC_ADDRESS_IN => fc_src_mac,
--- SRC_IP_ADDRESS_IN => fc_src_ip,
--- SRC_UDP_PORT_IN => fc_src_udp,
--- FRAME_TYPE_IN => fc_type,
--- IHL_VERSION_IN => fc_ihl_version,
--- TOS_IN => fc_tos,
--- IDENTIFICATION_IN => fc_ident,
--- FLAGS_OFFSET_IN => fc_flags_offset,
--- TTL_IN => fc_ttl,
--- PROTOCOL_IN => fc_protocol,
--- FRAME_DELAY_IN => frame_delay, -- gk 09.12.10
--- -- ports for packetTransmitter
--- RD_CLK => serdes_clk_125,
--- FT_DATA_OUT => ft_data,
--- --FT_EOD_OUT => ft_eod, -- gk 04.05.10
--- FT_TX_EMPTY_OUT => ft_tx_empty,
--- FT_TX_RD_EN_IN => mac_tx_read,
--- FT_START_OF_PACKET_OUT => ft_start_of_packet,
--- FT_TX_DONE_IN => mac_tx_done,
--- FT_TX_DISCFRM_IN => mac_tx_discfrm,
--- -- debug ports
--- BSM_CONSTR_OUT => fc_bsm_constr,
--- BSM_TRANS_OUT => fc_bsm_trans,
--- DEBUG_OUT(31 downto 0) => dbg_fc1,
--- DEBUG_OUT(63 downto 32) => dbg_fc2
--- );
---
---
---
--- RECEIVE_CONTROLLER : trb_net16_gbe_receive_control
--- port map(
--- CLK => CLK,
--- RESET => RESET,
---
--- -- signals to/from frame_receiver
--- RC_DATA_IN => fr_q,
--- FR_RD_EN_OUT => fr_rd_en,
--- FR_FRAME_VALID_IN => fr_frame_valid,
--- FR_GET_FRAME_OUT => fr_get_frame,
--- FR_FRAME_SIZE_IN => fr_frame_size,
--- FR_FRAME_PROTO_IN => fr_frame_proto,
--- FR_IP_PROTOCOL_IN => fr_ip_proto,
---
--- FR_SRC_MAC_ADDRESS_IN => fr_src_mac,
--- FR_DEST_MAC_ADDRESS_IN => fr_dest_mac,
--- FR_SRC_IP_ADDRESS_IN => fr_src_ip,
--- FR_DEST_IP_ADDRESS_IN => fr_dest_ip,
--- FR_SRC_UDP_PORT_IN => fr_src_udp,
--- FR_DEST_UDP_PORT_IN => fr_dest_udp,
---
--- -- signals to/from main controller
--- RC_RD_EN_IN => rc_rd_en,
--- RC_Q_OUT => rc_q,
--- RC_FRAME_WAITING_OUT => rc_frame_ready,
--- RC_LOADING_DONE_IN => rc_loading_done,
--- RC_FRAME_SIZE_OUT => rc_frame_size,
--- RC_FRAME_PROTO_OUT => rc_frame_proto,
---
--- RC_SRC_MAC_ADDRESS_OUT => rc_src_mac,
--- RC_DEST_MAC_ADDRESS_OUT => rc_dest_mac,
--- RC_SRC_IP_ADDRESS_OUT => rc_src_ip,
--- RC_DEST_IP_ADDRESS_OUT => rc_dest_ip,
--- RC_SRC_UDP_PORT_OUT => rc_src_udp,
--- RC_DEST_UDP_PORT_OUT => rc_dest_udp,
---
--- -- statistics
--- FRAMES_RECEIVED_OUT => rc_frames_rec_ctr,
--- BYTES_RECEIVED_OUT => rc_bytes_rec,
---
---
--- DEBUG_OUT => rc_debug
--- );
--- dbg_q(15 downto 9) <= (others => '0');
---
---
--- FRAME_TRANSMITTER: trb_net16_gbe_frame_trans
--- port map(
--- CLK => CLK,
--- RESET => RESET,
--- LINK_OK_IN => link_ok, --pcs_an_complete, -- gk 03.08.10 -- gk 30.09.10
--- TX_MAC_CLK => serdes_clk_125,
--- TX_EMPTY_IN => ft_tx_empty,
--- START_OF_PACKET_IN => ft_start_of_packet,
--- DATA_ENDFLAG_IN => ft_data(8), -- ft_eod -- gk 04.05.10
---
--- TX_FIFOAVAIL_OUT => mac_fifoavail,
--- TX_FIFOEOF_OUT => mac_fifoeof,
--- TX_FIFOEMPTY_OUT => mac_fifoempty,
--- TX_DONE_IN => mac_tx_done,
--- TX_STAT_EN_IN => mac_tx_staten,
--- TX_STATVEC_IN => mac_tx_statevec,
--- TX_DISCFRM_IN => mac_tx_discfrm,
--- -- Debug
--- BSM_INIT_OUT => ft_bsm_init,
--- BSM_MAC_OUT => ft_bsm_mac,
--- BSM_TRANS_OUT => ft_bsm_trans,
--- DBG_RD_DONE_OUT => open,
--- DBG_INIT_DONE_OUT => open,
--- DBG_ENABLED_OUT => open,
--- DEBUG_OUT => dbg_ft
--- --DEBUG_OUT(31 downto 0) => open,
--- --DEBUG_OUT(63 downto 32) => open
--- );
---
---
--- FRAME_RECEIVER : trb_net16_gbe_frame_receiver
--- port map(
--- CLK => CLK,
--- RESET => RESET,
--- LINK_OK_IN => link_ok,
--- ALLOW_RX_IN => allow_rx,
--- RX_MAC_CLK => serdes_clk_125,
---
--- -- input signals from TS_MAC
--- MAC_RX_EOF_IN => mac_rx_eof,
--- MAC_RX_ER_IN => mac_rx_er,
--- MAC_RXD_IN => mac_rxd,
--- MAC_RX_EN_IN => mac_rx_en,
--- MAC_RX_FIFO_ERR_IN => mac_rx_fifo_err,
--- MAC_RX_FIFO_FULL_OUT => mac_rx_fifo_full,
--- MAC_RX_STAT_EN_IN => mac_rx_stat_en,
--- MAC_RX_STAT_VEC_IN => mac_rx_stat_vec,
--- -- output signal to control logic
--- FR_Q_OUT => fr_q,
--- FR_RD_EN_IN => fr_rd_en,
--- FR_FRAME_VALID_OUT => fr_frame_valid,
--- FR_GET_FRAME_IN => fr_get_frame,
--- FR_FRAME_SIZE_OUT => fr_frame_size,
--- FR_FRAME_PROTO_OUT => fr_frame_proto,
--- FR_IP_PROTOCOL_OUT => fr_ip_proto,
--- FR_ALLOWED_TYPES_IN => fr_allowed_types,
--- FR_ALLOWED_IP_IN => fr_allowed_ip,
--- FR_ALLOWED_UDP_IN => fr_allowed_udp,
--- FR_VLAN_ID_IN => vlan_id,
---
--- FR_SRC_MAC_ADDRESS_OUT => fr_src_mac,
--- FR_DEST_MAC_ADDRESS_OUT => fr_dest_mac,
--- FR_SRC_IP_ADDRESS_OUT => fr_src_ip,
--- FR_DEST_IP_ADDRESS_OUT => fr_dest_ip,
--- FR_SRC_UDP_PORT_OUT => fr_src_udp,
--- FR_DEST_UDP_PORT_OUT => fr_dest_udp,
---
--- DEBUG_OUT => dbg_fr
--- );
---
+
+MAIN_CONTROL : trb_net16_gbe_main_control
+ port map(
+ CLK => CLK,
+ CLK_125 => serdes_clk_125,
+ RESET => RESET,
+
+ MC_LINK_OK_OUT => link_ok,
+ MC_RESET_LINK_IN => MR_RESTART_IN,
+
+ -- signals to/from receive controller
+ RC_FRAME_WAITING_IN => rc_frame_ready,
+ RC_LOADING_DONE_OUT => rc_loading_done,
+ RC_DATA_IN => rc_q,
+ RC_RD_EN_OUT => rc_rd_en,
+ RC_FRAME_SIZE_IN => rc_frame_size,
+ RC_FRAME_PROTO_IN => rc_frame_proto,
+
+ RC_SRC_MAC_ADDRESS_IN => rc_src_mac,
+ RC_DEST_MAC_ADDRESS_IN => rc_dest_mac,
+ RC_SRC_IP_ADDRESS_IN => rc_src_ip,
+ RC_DEST_IP_ADDRESS_IN => rc_dest_ip,
+ RC_SRC_UDP_PORT_IN => rc_src_udp,
+ RC_DEST_UDP_PORT_IN => rc_dest_udp,
+
+ -- signals to/from transmit controller
+ TC_TRANSMIT_CTRL_OUT => mc_transmit_ctrl,
+ TC_TRANSMIT_DATA_OUT => mc_transmit_data,
+ TC_DATA_OUT => mc_data,
+ TC_RD_EN_IN => mc_rd_en,
+ TC_FRAME_SIZE_OUT => mc_frame_size,
+ TC_FRAME_TYPE_OUT => mc_type,
+ TC_IP_PROTOCOL_OUT => mc_ip_proto,
+
+ TC_DEST_MAC_OUT => mc_dest_mac,
+ TC_DEST_IP_OUT => mc_dest_ip,
+ TC_DEST_UDP_OUT => mc_dest_udp,
+ TC_SRC_MAC_OUT => mc_src_mac,
+ TC_SRC_IP_OUT => mc_src_ip,
+ TC_SRC_UDP_OUT => mc_src_udp,
+
+ TC_BUSY_IN => mc_busy,
+ TC_TRANSMIT_DONE_IN => mc_transmit_done,
+
+ -- signals to/from packet constructor
+ PC_READY_IN => pc_ready,
+ PC_TRANSMIT_ON_IN => pc_transmit_on,
+ PC_SOD_IN => tc_sod,
+
+ -- signals to/from sgmii/gbe pcs_an_complete
+ PCS_AN_COMPLETE_IN => pcs_an_complete,
+
+ -- signals to/from hub
+ MC_UNIQUE_ID_IN => MC_UNIQUE_ID_IN,
+ GSC_CLK_IN => GSC_CLK_IN,
+ GSC_INIT_DATAREADY_OUT => GSC_INIT_DATAREADY_OUT,
+ GSC_INIT_DATA_OUT => GSC_INIT_DATA_OUT,
+ GSC_INIT_PACKET_NUM_OUT => GSC_INIT_PACKET_NUM_OUT,
+ GSC_INIT_READ_IN => GSC_INIT_READ_IN,
+ GSC_REPLY_DATAREADY_IN => GSC_REPLY_DATAREADY_IN,
+ GSC_REPLY_DATA_IN => GSC_REPLY_DATA_IN,
+ GSC_REPLY_PACKET_NUM_IN => GSC_REPLY_PACKET_NUM_IN,
+ GSC_REPLY_READ_OUT => GSC_REPLY_READ_OUT,
+ GSC_BUSY_IN => GSC_BUSY_IN,
+
+ -- signal to/from Host interface of TriSpeed MAC
+ TSM_HADDR_OUT => mac_haddr,
+ TSM_HDATA_OUT => mac_hdataout,
+ TSM_HCS_N_OUT => mac_hcs,
+ TSM_HWRITE_N_OUT => mac_hwrite,
+ TSM_HREAD_N_OUT => mac_hread,
+ TSM_HREADY_N_IN => mac_hready,
+ TSM_HDATA_EN_N_IN => mac_hdata_en,
+ TSM_RX_STAT_VEC_IN => mac_rx_stat_vec,
+ TSM_RX_STAT_EN_IN => mac_rx_stat_en,
+
+ SELECT_REC_FRAMES_OUT => dbg_select_rec,
+ SELECT_SENT_FRAMES_OUT => dbg_select_sent,
+ SELECT_PROTOS_DEBUG_OUT => dbg_select_protos,
+
+ DEBUG_OUT => dbg_mc
+ );
+
+
+TRANSMIT_CONTROLLER : trb_net16_gbe_transmit_control
+port map(
+ CLK => CLK,
+ RESET => RESET,
+
+-- signals to/from packet constructor
+ PC_READY_IN => pc_ready,
+ PC_DATA_IN => tc_data,
+ PC_WR_EN_IN => tc_wr_en,
+ PC_IP_SIZE_IN => tc_ip_size,
+ PC_UDP_SIZE_IN => tc_udp_size,
+ PC_FLAGS_OFFSET_IN => tc_flags_offset,
+ PC_SOD_IN => tc_sod,
+ PC_EOD_IN => tc_eod,
+ PC_FC_READY_OUT => tc_pc_ready,
+ PC_FC_H_READY_OUT => tc_pc_h_ready,
+ PC_TRANSMIT_ON_IN => pc_transmit_on,
+
+ -- signals from ip_configurator used by packet constructor
+ IC_DEST_MAC_ADDRESS_IN => ic_dest_mac,
+ IC_DEST_IP_ADDRESS_IN => ic_dest_ip,
+ IC_DEST_UDP_PORT_IN => ic_dest_udp,
+ IC_SRC_MAC_ADDRESS_IN => ic_src_mac,
+ IC_SRC_IP_ADDRESS_IN => ic_src_ip,
+ IC_SRC_UDP_PORT_IN => ic_src_udp,
+
+-- signal to/from main controller
+ MC_TRANSMIT_CTRL_IN => mc_transmit_ctrl,
+ MC_TRANSMIT_DATA_IN => mc_transmit_data,
+ MC_DATA_IN => mc_data,
+ MC_RD_EN_OUT => mc_rd_en,
+ MC_FRAME_SIZE_IN => mc_frame_size,
+ MC_FRAME_TYPE_IN => mc_type,
+ MC_IP_PROTOCOL_IN => mc_ip_proto,
+
+ MC_DEST_MAC_IN => mc_dest_mac,
+ MC_DEST_IP_IN => mc_dest_ip,
+ MC_DEST_UDP_IN => mc_dest_udp,
+ MC_SRC_MAC_IN => mc_src_mac,
+ MC_SRC_IP_IN => mc_src_ip,
+ MC_SRC_UDP_IN => mc_src_udp,
+
+ MC_BUSY_OUT => mc_busy,
+ MC_TRANSMIT_DONE_OUT => mc_transmit_done,
+
+-- signal to/from frame constructor
+ FC_DATA_OUT => fc_data,
+ FC_WR_EN_OUT => fc_wr_en,
+ FC_READY_IN => fc_ready,
+ FC_H_READY_IN => fc_h_ready,
+ FC_FRAME_TYPE_OUT => fc_type,
+ FC_IP_SIZE_OUT => fc_ip_size,
+ FC_UDP_SIZE_OUT => fc_udp_size,
+ FC_IDENT_OUT => fc_ident,
+ FC_FLAGS_OFFSET_OUT => fc_flags_offset,
+ FC_SOD_OUT => fc_sod,
+ FC_EOD_OUT => fc_eod,
+ FC_IP_PROTOCOL_OUT => fc_protocol,
+
+ DEST_MAC_ADDRESS_OUT => fc_dest_mac,
+ DEST_IP_ADDRESS_OUT => fc_dest_ip,
+ DEST_UDP_PORT_OUT => fc_dest_udp,
+ SRC_MAC_ADDRESS_OUT => fc_src_mac,
+ SRC_IP_ADDRESS_OUT => fc_src_ip,
+ SRC_UDP_PORT_OUT => fc_src_udp,
+
+
+-- debug
+ DEBUG_OUT => dbg_tc
+);
+
+
+setup_imp_gen : if (DO_SIMULATION = 0) generate
+-- gk 22.04.10 new entity to set values via slow control
+SETUP : gbe_setup
+port map(
+ CLK => CLK,
+ RESET => RESET,
+
+ -- gk 26.04.10
+ -- interface to regio bus
+ BUS_ADDR_IN => BUS_ADDR_IN,
+ BUS_DATA_IN => BUS_DATA_IN,
+ BUS_DATA_OUT => BUS_DATA_OUT,
+ BUS_WRITE_EN_IN => BUS_WRITE_EN_IN,
+ BUS_READ_EN_IN => BUS_READ_EN_IN,
+ BUS_ACK_OUT => BUS_ACK_OUT,
+
+ GBE_TRIG_NR_IN => pc_trig_nr, -- gk 26.04.10
+
+ -- output to gbe_buf
+ GBE_SUBEVENT_ID_OUT => pc_event_id,
+ GBE_SUBEVENT_DEC_OUT => pc_decoding,
+ GBE_QUEUE_DEC_OUT => pc_queue_dec,
+ GBE_MAX_PACKET_OUT => max_packet,
+ GBE_MIN_PACKET_OUT => min_packet, -- gk 20.07.10
+ GBE_MAX_FRAME_OUT => pc_max_frame_size,
+ GBE_USE_GBE_OUT => use_gbe,
+ GBE_USE_TRBNET_OUT => use_trbnet,
+ GBE_USE_MULTIEVENTS_OUT => use_multievents,
+ GBE_READOUT_CTR_OUT => readout_ctr, -- gk 26.04.10
+ GBE_READOUT_CTR_VALID_OUT => readout_ctr_valid, -- gk 26.04.10
+ GBE_DELAY_OUT => pc_delay,
+ GBE_ALLOW_LARGE_OUT => allow_large, -- gk 21.07.10
+ GBE_ALLOW_RX_OUT => allow_rx,
+ GBE_FRAME_DELAY_OUT => frame_delay, -- gk 09.12.10
+ GBE_ALLOWED_TYPES_OUT => fr_allowed_types,
+ GBE_ALLOWED_IP_OUT => fr_allowed_ip,
+ GBE_ALLOWED_UDP_OUT => fr_allowed_udp,
+ GBE_VLAN_ID_OUT => vlan_id,
+ -- gk 28.07.10
+ MONITOR_BYTES_IN => bytes_sent_ctr,
+ MONITOR_SENT_IN => monitor_sent,
+ MONITOR_DROPPED_IN => monitor_dropped,
+ MONITOR_SM_IN => monitor_sm,
+ MONITOR_LR_IN => monitor_lr,
+ MONITOR_HDR_IN => monitor_hr,
+ MONITOR_FIFOS_IN => monitor_fifos_q,
+ MONITOR_DISCFRM_IN => monitor_discfrm,
+ MONITOR_EMPTY_IN => monitor_empty,
+ MONITOR_LINK_DWN_IN(15 downto 0) => link_down_ctr, -- gk 30.09.10
+ MONITOR_LINK_DWN_IN(19 downto 16) => link_state,
+ MONITOR_LINK_DWN_IN(23 downto 20) => ft_bsm_trans,
+ MONITOR_LINK_DWN_IN(27 downto 24) => fc_bsm_trans,
+ MONITOR_LINK_DWN_IN(31 downto 28) => (others => '0'),
+ MONITOR_RX_FRAMES_IN => rc_frames_rec_ctr,
+ MONITOR_RX_BYTES_IN => rc_bytes_rec,
+ MONITOR_RX_BYTES_R_IN => rc_debug(31 downto 0),
+ -- gk 01.06.10
+ DBG_IPU2GBE1_IN => dbg_ipu2gbe1,
+ DBG_IPU2GBE2_IN => dbg_ipu2gbe2,
+ DBG_IPU2GBE3_IN => dbg_ipu2gbe3,
+ DBG_IPU2GBE4_IN => dbg_ipu2gbe4,
+ DBG_IPU2GBE5_IN => dbg_ipu2gbe5,
+ DBG_IPU2GBE6_IN => dbg_ipu2gbe6,
+ DBG_IPU2GBE7_IN => dbg_ipu2gbe7,
+ DBG_IPU2GBE8_IN => dbg_ipu2gbe8,
+ DBG_IPU2GBE9_IN => dbg_ipu2gbe9,
+ DBG_IPU2GBE10_IN => dbg_ipu2gbe10,
+ DBG_IPU2GBE11_IN => dbg_ipu2gbe11,
+ DBG_IPU2GBE12_IN => dbg_ipu2gbe12,
+ DBG_PC1_IN => dbg_pc1,
+ DBG_PC2_IN => dbg_pc2,
+ DBG_FC1_IN => dbg_fc1,
+ DBG_FC2_IN => dbg_fc2,
+ DBG_FT1_IN => dbg_ft1,
+ DBG_FT2_IN => dbg_ft(31 downto 0),
+ DBG_FR_IN => dbg_fr(63 downto 0),
+ DBG_RC_IN => dbg_rc,
+ DBG_MC_IN => dbg_mc,
+ DBG_TC_IN => dbg_tc(31 downto 0),
+ DBG_FIFO_RD_EN_OUT => dbg_rd_en,
+
+ DBG_SELECT_REC_IN => dbg_select_rec,
+ DBG_SELECT_SENT_IN => dbg_select_sent,
+ DBG_SELECT_PROTOS_IN => dbg_select_protos,
+
+ DBG_FIFO_Q_IN => dbg_q
+
+ --DBG_FIFO_RESET_OUT => dbg_reset_fifo -- gk 28.09.10
+);
+end generate;
+
+setup_sim_gen : if (DO_SIMULATION = 1) generate
+-- gk 22.04.10 new entity to set values via slow control
+SETUP : gbe_setup
+port map(
+ CLK => CLK,
+ RESET => RESET,
+
+ -- gk 26.04.10
+ -- interface to regio bus
+ BUS_ADDR_IN => BUS_ADDR_IN,
+ BUS_DATA_IN => BUS_DATA_IN,
+ BUS_DATA_OUT => BUS_DATA_OUT,
+ BUS_WRITE_EN_IN => BUS_WRITE_EN_IN,
+ BUS_READ_EN_IN => BUS_READ_EN_IN,
+ BUS_ACK_OUT => BUS_ACK_OUT,
+
+ GBE_TRIG_NR_IN => pc_trig_nr, -- gk 26.04.10
+
+ -- output to gbe_buf
+ GBE_SUBEVENT_ID_OUT => pc_event_id,
+ GBE_SUBEVENT_DEC_OUT => pc_decoding,
+ GBE_QUEUE_DEC_OUT => pc_queue_dec,
+ GBE_MAX_PACKET_OUT => max_packet,
+ GBE_MIN_PACKET_OUT => min_packet, -- gk 20.07.10
+ GBE_MAX_FRAME_OUT => pc_max_frame_size,
+ GBE_USE_GBE_OUT => use_gbe,
+ GBE_USE_TRBNET_OUT => use_trbnet,
+ GBE_USE_MULTIEVENTS_OUT => use_multievents,
+ GBE_READOUT_CTR_OUT => readout_ctr, -- gk 26.04.10
+ GBE_READOUT_CTR_VALID_OUT => readout_ctr_valid, -- gk 26.04.10
+ GBE_DELAY_OUT => pc_delay,
+ GBE_ALLOW_LARGE_OUT => open,
+ GBE_ALLOW_RX_OUT => open,
+ GBE_FRAME_DELAY_OUT => frame_delay, -- gk 09.12.10
+ GBE_ALLOWED_TYPES_OUT => fr_allowed_types,
+ GBE_ALLOWED_IP_OUT => fr_allowed_ip,
+ GBE_ALLOWED_UDP_OUT => fr_allowed_udp,
+ GBE_VLAN_ID_OUT => vlan_id,
+ -- gk 28.07.10
+ MONITOR_BYTES_IN => bytes_sent_ctr,
+ MONITOR_SENT_IN => monitor_sent,
+ MONITOR_DROPPED_IN => monitor_dropped,
+ MONITOR_SM_IN => monitor_sm,
+ MONITOR_LR_IN => monitor_lr,
+ MONITOR_HDR_IN => monitor_hr,
+ MONITOR_FIFOS_IN => monitor_fifos_q,
+ MONITOR_DISCFRM_IN => monitor_discfrm,
+ MONITOR_EMPTY_IN => monitor_empty,
+ MONITOR_LINK_DWN_IN(15 downto 0) => link_down_ctr, -- gk 30.09.10
+ MONITOR_LINK_DWN_IN(19 downto 16) => link_state,
+ MONITOR_LINK_DWN_IN(23 downto 20) => ft_bsm_trans,
+ MONITOR_LINK_DWN_IN(27 downto 24) => fc_bsm_trans,
+ MONITOR_LINK_DWN_IN(31 downto 28) => (others => '0'),
+ MONITOR_RX_FRAMES_IN => rc_frames_rec_ctr,
+ MONITOR_RX_BYTES_IN => rc_bytes_rec,
+ MONITOR_RX_BYTES_R_IN => rc_debug(31 downto 0),
+ -- gk 01.06.10
+ DBG_IPU2GBE1_IN => dbg_ipu2gbe1,
+ DBG_IPU2GBE2_IN => dbg_ipu2gbe2,
+ DBG_IPU2GBE3_IN => dbg_ipu2gbe3,
+ DBG_IPU2GBE4_IN => dbg_ipu2gbe4,
+ DBG_IPU2GBE5_IN => dbg_ipu2gbe5,
+ DBG_IPU2GBE6_IN => dbg_ipu2gbe6,
+ DBG_IPU2GBE7_IN => dbg_ipu2gbe7,
+ DBG_IPU2GBE8_IN => dbg_ipu2gbe8,
+ DBG_IPU2GBE9_IN => dbg_ipu2gbe9,
+ DBG_IPU2GBE10_IN => dbg_ipu2gbe10,
+ DBG_IPU2GBE11_IN => dbg_ipu2gbe11,
+ DBG_IPU2GBE12_IN => dbg_ipu2gbe12,
+ DBG_PC1_IN => dbg_pc1,
+ DBG_PC2_IN => dbg_pc2,
+ DBG_FC1_IN => dbg_fc1,
+ DBG_FC2_IN => dbg_fc2,
+ DBG_FT1_IN => dbg_ft1,
+ DBG_FT2_IN => dbg_ft(31 downto 0),
+ DBG_FR_IN => dbg_fr,
+ DBG_RC_IN => dbg_rc(31 downto 0),
+ DBG_MC_IN => dbg_mc,
+ DBG_TC_IN => dbg_tc(31 downto 0),
+ DBG_FIFO_RD_EN_OUT => dbg_rd_en,
+
+ DBG_SELECT_REC_IN => dbg_select_rec,
+ DBG_SELECT_SENT_IN => dbg_select_sent,
+ DBG_SELECT_PROTOS_IN => dbg_select_protos,
+
+ DBG_FIFO_Q_IN => dbg_q
+ --DBG_FIFO_RESET_OUT => dbg_reset_fifo -- gk 28.09.10
+);
+
+allow_rx <= '1';
+allow_large <= '0';
+
+end generate;
+
+
+-- IP configurator: allows IP config to change for each event builder
+THE_IP_CONFIGURATOR: ip_configurator
+port map(
+ CLK => CLK,
+ RESET => RESET,
+ -- configuration interface
+ START_CONFIG_IN => ip_cfg_start, --IP_CFG_START_IN, -- new -- gk 7.03.10
+ BANK_SELECT_IN => ip_cfg_bank, --IP_CFG_BANK_SEL_IN, -- new -- gk 27.03.10
+ CONFIG_DONE_OUT => ip_cfg_done, --IP_CFG_DONE_OUT, -- new -- gk 27.03.10
+ MEM_ADDR_OUT => ip_cfg_mem_addr, --IP_CFG_MEM_ADDR_OUT, -- new -- gk 27.03.10
+ MEM_DATA_IN => ip_cfg_mem_data, --IP_CFG_MEM_DATA_IN, -- new -- gk 27.03.10
+ MEM_CLK_OUT => ip_cfg_mem_clk, --IP_CFG_MEM_CLK_OUT, -- new -- gk 27.03.10
+ -- information for IP cores
+ DEST_MAC_OUT => ic_dest_mac,
+ DEST_IP_OUT => ic_dest_ip,
+ DEST_UDP_OUT => ic_dest_udp,
+ SRC_MAC_OUT => ic_src_mac,
+ SRC_IP_OUT => ic_src_ip,
+ SRC_UDP_OUT => ic_src_udp,
+ MTU_OUT => open, --pc_max_frame_size, -- gk 22.04.10
+ -- Debug
+ DEBUG_OUT => open
+);
+
+-- gk 27.03.01
+MB_IP_CONFIG: slv_mac_memory
+port map(
+ CLK => CLK, -- clk_100,
+ RESET => RESET, --reset_i,
+ BUSY_IN => '0',
+ -- Slave bus
+ SLV_ADDR_IN => SLV_ADDR_IN, --x"00", --mb_ip_mem_addr(7 downto 0),
+ SLV_READ_IN => SLV_READ_IN, --'0', --mb_ip_mem_read,
+ SLV_WRITE_IN => SLV_WRITE_IN, --mb_ip_mem_write,
+ SLV_BUSY_OUT => SLV_BUSY_OUT,
+ SLV_ACK_OUT => SLV_ACK_OUT, --mb_ip_mem_ack,
+ SLV_DATA_IN => SLV_DATA_IN, --mb_ip_mem_data_wr,
+ SLV_DATA_OUT => SLV_DATA_OUT, --mb_ip_mem_data_rd,
+ -- I/O to the backend
+ MEM_CLK_IN => ip_cfg_mem_clk,
+ MEM_ADDR_IN => ip_cfg_mem_addr,
+ MEM_DATA_OUT => ip_cfg_mem_data,
+ -- Status lines
+ STAT => open
+);
+
+-- First stage: get data from IPU channel, buffer it and terminate the IPU transmission to CTS
+THE_IPU_INTERFACE: trb_net16_ipu2gbe
+port map(
+ CLK => CLK,
+ RESET => RESET,
+ --Event information coming from CTS
+ CTS_NUMBER_IN => CTS_NUMBER_IN,
+ CTS_CODE_IN => CTS_CODE_IN,
+ CTS_INFORMATION_IN => CTS_INFORMATION_IN,
+ CTS_READOUT_TYPE_IN => CTS_READOUT_TYPE_IN,
+ CTS_START_READOUT_IN => CTS_START_READOUT_IN,
+ --Information sent to CTS
+ --status data, equipped with DHDR
+ CTS_DATA_OUT => cts_data,
+ CTS_DATAREADY_OUT => cts_dataready,
+ CTS_READOUT_FINISHED_OUT => cts_readout_finished,
+ CTS_READ_IN => CTS_READ_IN,
+ CTS_LENGTH_OUT => cts_length,
+ CTS_ERROR_PATTERN_OUT => cts_error_pattern,
+ -- Data from Frontends
+ FEE_DATA_IN => FEE_DATA_IN,
+ FEE_DATAREADY_IN => FEE_DATAREADY_IN,
+ FEE_READ_OUT => fee_read,
+ FEE_STATUS_BITS_IN => FEE_STATUS_BITS_IN,
+ FEE_BUSY_IN => FEE_BUSY_IN,
+ -- slow control interface
+ START_CONFIG_OUT => ip_cfg_start, --open, --: out std_logic; -- reconfigure MACs/IPs/ports/packet size -- gk 27.03.10
+ BANK_SELECT_OUT => ip_cfg_bank, --open, --: out std_logic_vector(3 downto 0); -- configuration page address -- gk 27.03.10
+ CONFIG_DONE_IN => ip_cfg_done, --'1', --: in std_logic; -- configuration finished -- gk 27.03.10
+ DATA_GBE_ENABLE_IN => use_gbe, --'1', --: in std_logic; -- IPU data is forwarded to GbE -- gk 22.04.10
+ DATA_IPU_ENABLE_IN => use_trbnet, --'0', --: in std_logic; -- IPU data is forwarded to CTS / TRBnet -- gk 22.04.10
+ MULT_EVT_ENABLE_IN => use_multievents,
+ MAX_MESSAGE_SIZE_IN => max_packet, --x"0000_FDE8", -- gk 08.04.10 -- temporarily fixed here, to be set by slow ctrl -- gk 22.04.10
+ MIN_MESSAGE_SIZE_IN => min_packet, -- gk 20.07.10
+ READOUT_CTR_IN => readout_ctr, -- gk 26.04.10
+ READOUT_CTR_VALID_IN => readout_ctr_valid, -- gk 26.04.10
+ ALLOW_LARGE_IN => allow_large, -- gk 21.07.10
+ -- PacketConstructor interface
+ PC_WR_EN_OUT => pc_wr_en,
+ PC_DATA_OUT => pc_data,
+ PC_READY_IN => pc_ready,
+ PC_SOS_OUT => pc_sos,
+ PC_EOS_OUT => pc_eos, -- gk 07.10.10
+ PC_EOD_OUT => pc_eod,
+ PC_SUB_SIZE_OUT => pc_sub_size,
+ PC_TRIG_NR_OUT => pc_trig_nr,
+ PC_PADDING_OUT => pc_padding,
+ MONITOR_OUT(31 downto 0) => monitor_sent,
+ MONITOR_OUT(63 downto 32) => monitor_dropped,
+ MONITOR_OUT(95 downto 64) => monitor_hr,
+ MONITOR_OUT(127 downto 96) => monitor_sm,
+ MONITOR_OUT(159 downto 128) => monitor_lr,
+ MONITOR_OUT(191 downto 160) => monitor_fifos,
+ MONITOR_OUT(223 downto 192) => monitor_empty,
+ DEBUG_OUT(31 downto 0) => dbg_ipu2gbe1,
+ DEBUG_OUT(63 downto 32) => dbg_ipu2gbe2,
+ DEBUG_OUT(95 downto 64) => dbg_ipu2gbe3,
+ DEBUG_OUT(127 downto 96) => dbg_ipu2gbe4,
+ DEBUG_OUT(159 downto 128) => dbg_ipu2gbe5,
+ DEBUG_OUT(191 downto 160) => dbg_ipu2gbe6,
+ DEBUG_OUT(223 downto 192) => dbg_ipu2gbe7,
+ DEBUG_OUT(255 downto 224) => dbg_ipu2gbe8,
+ DEBUG_OUT(287 downto 256) => dbg_ipu2gbe9,
+ DEBUG_OUT(319 downto 288) => dbg_ipu2gbe10,
+ DEBUG_OUT(351 downto 320) => dbg_ipu2gbe11,
+ DEBUG_OUT(383 downto 352) => dbg_ipu2gbe12
+);
+
+-- Second stage: Packet constructor
+PACKET_CONSTRUCTOR : trb_net16_gbe_packet_constr
+port map(
+ -- ports for user logic
+ RESET => RESET,
+ CLK => CLK,
+ MULT_EVT_ENABLE_IN => use_multievents, -- gk 06.10.10
+ PC_WR_EN_IN => pc_wr_en,
+ PC_DATA_IN => pc_data,
+ PC_READY_OUT => pc_ready,
+ PC_START_OF_SUB_IN => dbg_rd_en, -- pc_sos, CHANGED TO SLOW CONTROL PULSE
+ PC_END_OF_SUB_IN => pc_eos, -- gk 07.10.10
+ PC_END_OF_DATA_IN => pc_eod,
+ PC_TRANSMIT_ON_OUT => pc_transmit_on,
+ -- queue and subevent layer headers
+ PC_SUB_SIZE_IN => pc_sub_size,
+ PC_PADDING_IN => pc_padding, -- gk 29.03.10
+ PC_DECODING_IN => pc_decoding,
+ PC_EVENT_ID_IN => pc_event_id,
+ PC_TRIG_NR_IN => pc_trig_nr,
+ PC_QUEUE_DEC_IN => pc_queue_dec,
+ PC_MAX_FRAME_SIZE_IN => pc_max_frame_size,
+ PC_DELAY_IN => pc_delay, -- gk 28.04.10
+ -- NEW PORTS
+ TC_WR_EN_OUT => tc_wr_en,
+ TC_DATA_OUT => tc_data,
+ TC_H_READY_IN => tc_pc_h_ready,
+ TC_READY_IN => tc_pc_ready,
+ TC_IP_SIZE_OUT => tc_ip_size,
+ TC_UDP_SIZE_OUT => tc_udp_size,
+ --FC_IDENT_OUT => fc_ident,
+ TC_FLAGS_OFFSET_OUT => tc_flags_offset,
+ TC_SOD_OUT => tc_sod,
+ TC_EOD_OUT => tc_eod,
+ DEBUG_OUT(31 downto 0) => dbg_pc1,
+ DEBUG_OUT(63 downto 32) => dbg_pc2
+);
+
+-- Third stage: Frame Constructor
+FRAME_CONSTRUCTOR: trb_net16_gbe_frame_constr
+port map(
+ -- ports for user logic
+ RESET => RESET,
+ CLK => CLK,
+ LINK_OK_IN => link_ok, --pcs_an_complete, -- gk 03.08.10 -- gk 30.09.10
+ --
+ WR_EN_IN => fc_wr_en,
+ DATA_IN => fc_data,
+ START_OF_DATA_IN => fc_sod,
+ END_OF_DATA_IN => fc_eod,
+ IP_F_SIZE_IN => fc_ip_size,
+ UDP_P_SIZE_IN => fc_udp_size,
+ HEADERS_READY_OUT => fc_h_ready,
+ READY_OUT => fc_ready,
+ DEST_MAC_ADDRESS_IN => fc_dest_mac,
+ DEST_IP_ADDRESS_IN => fc_dest_ip,
+ DEST_UDP_PORT_IN => fc_dest_udp,
+ SRC_MAC_ADDRESS_IN => fc_src_mac,
+ SRC_IP_ADDRESS_IN => fc_src_ip,
+ SRC_UDP_PORT_IN => fc_src_udp,
+ FRAME_TYPE_IN => fc_type,
+ IHL_VERSION_IN => fc_ihl_version,
+ TOS_IN => fc_tos,
+ IDENTIFICATION_IN => fc_ident,
+ FLAGS_OFFSET_IN => fc_flags_offset,
+ TTL_IN => fc_ttl,
+ PROTOCOL_IN => fc_protocol,
+ FRAME_DELAY_IN => frame_delay, -- gk 09.12.10
+ -- ports for packetTransmitter
+ RD_CLK => serdes_clk_125,
+ FT_DATA_OUT => ft_data,
+ --FT_EOD_OUT => ft_eod, -- gk 04.05.10
+ FT_TX_EMPTY_OUT => ft_tx_empty,
+ FT_TX_RD_EN_IN => mac_tx_read,
+ FT_START_OF_PACKET_OUT => ft_start_of_packet,
+ FT_TX_DONE_IN => mac_tx_done,
+ FT_TX_DISCFRM_IN => mac_tx_discfrm,
+ -- debug ports
+ BSM_CONSTR_OUT => fc_bsm_constr,
+ BSM_TRANS_OUT => fc_bsm_trans,
+ DEBUG_OUT(31 downto 0) => dbg_fc1,
+ DEBUG_OUT(63 downto 32) => dbg_fc2
+);
+
+
+
+RECEIVE_CONTROLLER : trb_net16_gbe_receive_control
+port map(
+ CLK => CLK,
+ RESET => RESET,
+
+-- signals to/from frame_receiver
+ RC_DATA_IN => fr_q,
+ FR_RD_EN_OUT => fr_rd_en,
+ FR_FRAME_VALID_IN => fr_frame_valid,
+ FR_GET_FRAME_OUT => fr_get_frame,
+ FR_FRAME_SIZE_IN => fr_frame_size,
+ FR_FRAME_PROTO_IN => fr_frame_proto,
+ FR_IP_PROTOCOL_IN => fr_ip_proto,
+
+ FR_SRC_MAC_ADDRESS_IN => fr_src_mac,
+ FR_DEST_MAC_ADDRESS_IN => fr_dest_mac,
+ FR_SRC_IP_ADDRESS_IN => fr_src_ip,
+ FR_DEST_IP_ADDRESS_IN => fr_dest_ip,
+ FR_SRC_UDP_PORT_IN => fr_src_udp,
+ FR_DEST_UDP_PORT_IN => fr_dest_udp,
+
+-- signals to/from main controller
+ RC_RD_EN_IN => rc_rd_en,
+ RC_Q_OUT => rc_q,
+ RC_FRAME_WAITING_OUT => rc_frame_ready,
+ RC_LOADING_DONE_IN => rc_loading_done,
+ RC_FRAME_SIZE_OUT => rc_frame_size,
+ RC_FRAME_PROTO_OUT => rc_frame_proto,
+
+ RC_SRC_MAC_ADDRESS_OUT => rc_src_mac,
+ RC_DEST_MAC_ADDRESS_OUT => rc_dest_mac,
+ RC_SRC_IP_ADDRESS_OUT => rc_src_ip,
+ RC_DEST_IP_ADDRESS_OUT => rc_dest_ip,
+ RC_SRC_UDP_PORT_OUT => rc_src_udp,
+ RC_DEST_UDP_PORT_OUT => rc_dest_udp,
+
+-- statistics
+ FRAMES_RECEIVED_OUT => rc_frames_rec_ctr,
+ BYTES_RECEIVED_OUT => rc_bytes_rec,
+
+
+ DEBUG_OUT => rc_debug
+);
+dbg_q(15 downto 9) <= (others => '0');
+
+
+FRAME_TRANSMITTER: trb_net16_gbe_frame_trans
+port map(
+ CLK => CLK,
+ RESET => RESET,
+ LINK_OK_IN => link_ok, --pcs_an_complete, -- gk 03.08.10 -- gk 30.09.10
+ TX_MAC_CLK => serdes_clk_125,
+ TX_EMPTY_IN => ft_tx_empty,
+ START_OF_PACKET_IN => ft_start_of_packet,
+ DATA_ENDFLAG_IN => ft_data(8), -- ft_eod -- gk 04.05.10
+
+ TX_FIFOAVAIL_OUT => mac_fifoavail,
+ TX_FIFOEOF_OUT => mac_fifoeof,
+ TX_FIFOEMPTY_OUT => mac_fifoempty,
+ TX_DONE_IN => mac_tx_done,
+ TX_STAT_EN_IN => mac_tx_staten,
+ TX_STATVEC_IN => mac_tx_statevec,
+ TX_DISCFRM_IN => mac_tx_discfrm,
+ -- Debug
+ BSM_INIT_OUT => ft_bsm_init,
+ BSM_MAC_OUT => ft_bsm_mac,
+ BSM_TRANS_OUT => ft_bsm_trans,
+ DBG_RD_DONE_OUT => open,
+ DBG_INIT_DONE_OUT => open,
+ DBG_ENABLED_OUT => open,
+ DEBUG_OUT => dbg_ft
+ --DEBUG_OUT(31 downto 0) => open,
+ --DEBUG_OUT(63 downto 32) => open
+);
+
+
+ FRAME_RECEIVER : trb_net16_gbe_frame_receiver
+ port map(
+ CLK => CLK,
+ RESET => RESET,
+ LINK_OK_IN => link_ok,
+ ALLOW_RX_IN => allow_rx,
+ RX_MAC_CLK => serdes_rx_clk, --serdes_clk_125,
+
+ -- input signals from TS_MAC
+ MAC_RX_EOF_IN => mac_rx_eof,
+ MAC_RX_ER_IN => mac_rx_er,
+ MAC_RXD_IN => mac_rxd,
+ MAC_RX_EN_IN => mac_rx_en,
+ MAC_RX_FIFO_ERR_IN => mac_rx_fifo_err,
+ MAC_RX_FIFO_FULL_OUT => mac_rx_fifo_full,
+ MAC_RX_STAT_EN_IN => mac_rx_stat_en,
+ MAC_RX_STAT_VEC_IN => mac_rx_stat_vec,
+ -- output signal to control logic
+ FR_Q_OUT => fr_q,
+ FR_RD_EN_IN => fr_rd_en,
+ FR_FRAME_VALID_OUT => fr_frame_valid,
+ FR_GET_FRAME_IN => fr_get_frame,
+ FR_FRAME_SIZE_OUT => fr_frame_size,
+ FR_FRAME_PROTO_OUT => fr_frame_proto,
+ FR_IP_PROTOCOL_OUT => fr_ip_proto,
+ FR_ALLOWED_TYPES_IN => fr_allowed_types,
+ FR_ALLOWED_IP_IN => fr_allowed_ip,
+ FR_ALLOWED_UDP_IN => fr_allowed_udp,
+ FR_VLAN_ID_IN => vlan_id,
+
+ FR_SRC_MAC_ADDRESS_OUT => fr_src_mac,
+ FR_DEST_MAC_ADDRESS_OUT => fr_dest_mac,
+ FR_SRC_IP_ADDRESS_OUT => fr_src_ip,
+ FR_DEST_IP_ADDRESS_OUT => fr_dest_ip,
+ FR_SRC_UDP_PORT_OUT => fr_src_udp,
+ FR_DEST_UDP_PORT_OUT => fr_dest_udp,
+
+ DEBUG_OUT => dbg_fr
+ );
+
-- in case of real hardware, we use the IP cores for MAC and PHY, and also put a SerDes in
imp_gen: if (DO_SIMULATION = 0) generate
----------------- clock and reset port declarations ------------------
hclk => CLK,
txmac_clk => serdes_clk_125,
- rxmac_clk => serdes_clk_125,
+ rxmac_clk => serdes_rx_clk, --serdes_clk_125,
reset_n => GSR_N,
txmac_clk_en => mac_tx_clk_en,
rxmac_clk_en => mac_rx_clk_en,
------------------- Input signals to the GMII ---------------- NOT USED
- rxd => pcs_txd, --pcs_rxd, --x"00",
- rx_dv => pcs_tx_en, --pcs_rx_en, --'0',
- rx_er => pcs_tx_er, --pcs_rx_er, --'0',
+ rxd => pcs_rxd_qq, --x"00",
+ rx_dv => pcs_rx_en_qq, --'0',
+ rx_er => pcs_rx_er_qq, --'0',
col => mac_col,
crs => mac_crs,
-------------------- Input signals to the CPU I/F -------------------
rx_eof => mac_rx_eof, --open,
rx_error => mac_rx_er --open
);
+
+ SYNC_GMII_RX_PROC : process(serdes_rx_clk)
+ begin
+ if rising_edge(serdes_rx_clk) then
+ pcs_rxd_q <= pcs_rxd;
+ pcs_rx_en_q <= pcs_rx_en;
+ pcs_rx_er_q <= pcs_rx_er;
+
+ pcs_rxd_qq <= pcs_rxd_q;
+ pcs_rx_en_qq <= pcs_rx_en_q;
+ pcs_rx_er_qq <= pcs_rx_er_q;
+ --mac_col_q <= mac_col;
+ --mac_crs_q <= mac_crs;
+ end if;
+ end process SYNC_GMII_RX_PROC;
+
+ SYNC_GMII_TX_PROC : process(serdes_clk_125)
+ begin
+ if rising_edge(serdes_clk_125) then
+ pcs_txd_q <= pcs_txd;
+ pcs_tx_en_q <= pcs_tx_en;
+ pcs_tx_er_q <= pcs_tx_er;
+
+ pcs_txd_qq <= pcs_txd_q;
+ pcs_tx_en_qq <= pcs_tx_en_q;
+ pcs_tx_er_qq <= pcs_tx_er_q;
+ end if;
+ end process SYNC_GMII_TX_PROC;
-- gk 08.06.10
dbg_statevec_proc : process(serdes_clk_125)
RESET => RESET,
GSR_N => GSR_N,
CLK_125_OUT => serdes_clk_125,
- CLK_125_RX_OUT => open,
+ CLK_125_RX_OUT => serdes_rx_clk, --open,
CLK_125_IN => CLK_125_IN,
FT_TX_CLK_EN_OUT => mac_tx_clk_en,
FT_RX_CLK_EN_OUT => mac_rx_clk_en,
--connection to frame transmitter (tsmac)
FT_COL_OUT => mac_col,
FT_CRS_OUT => mac_crs,
- FT_TXD_IN => pcs_txd,
- FT_TX_EN_IN => pcs_tx_en,
- FT_TX_ER_IN => pcs_tx_er,
+ FT_TXD_IN => pcs_txd_qq,
+ FT_TX_EN_IN => pcs_tx_en_qq,
+ FT_TX_ER_IN => pcs_tx_er_qq,
FT_RXD_OUT => pcs_rxd,
FT_RX_EN_OUT => pcs_rx_en,
FT_RX_ER_OUT => pcs_rx_er,
MR_AN_LP_ABILITY_OUT => pcs_an_lp_ability,
MR_AN_PAGE_RX_OUT => pcs_an_page_rx,
MR_AN_COMPLETE_OUT => pcs_an_complete,
- MR_RESET_IN => RESET, --MR_RESET_IN,
+ MR_RESET_IN => RESET,
MR_MODE_IN => '0', --MR_MODE_IN,
MR_AN_ENABLE_IN => '1', -- do autonegotiation
- MR_RESTART_AN_IN => RESET, --MR_RESTART_IN,
+ MR_RESTART_AN_IN => '0', --MR_RESTART_IN,
-- Status and control port
STAT_OP => open,
CTRL_OP => x"0000",
STAGE_STAT_REGS_OUT <= stage_stat_regs;
ANALYZER_DEBUG_OUT <= analyzer_debug;
-analyzer_debug(0) <= '0'; --serdes_clk_125;
-analyzer_debug(1) <= not pcs_stat_debug(22);
-analyzer_debug(2) <= SFP_PRSNT_N_IN;
-analyzer_debug(3) <= SFP_LOS_IN;
-analyzer_debug(63 downto 4) <= (others => '0');
+--analyzer_debug(0) <= serdes_clk_125;
+--analyzer_debug(1) <= not pcs_stat_debug(22);
+--analyzer_debug(2) <= SFP_PRSNT_N_IN;
+--analyzer_debug(3) <= SFP_LOS_IN;
+--analyzer_debug(63 downto 4) <= (others => '0');
+analyzer_debug(3 downto 0) <= dbg_mc(15 downto 12);
end architecture;
Full => rec_fifo_full
);
+-- BUG HERE, probably more lost bytes in the fifo in other conditions
fifo_wr_en <= '1' when (MAC_RX_EN_IN = '1') and ((filter_current_state = SAVE_FRAME) or
- ( (filter_current_state = REMOVE_TYPE and remove_ctr = x"b" and saved_frame_type /= x"8100" and saved_frame_type /= x"0800") or
- (filter_current_state = REMOVE_VTYPE and remove_ctr = x"f") or
+ --( (filter_current_state = REMOVE_TYPE and remove_ctr = x"b" and saved_frame_type /= x"8100" and saved_frame_type /= x"0800") or
+ ((filter_current_state = REMOVE_VTYPE and remove_ctr = x"f") or
(filter_current_state = DECIDE and frame_type_valid = '1')))
else '0';
PCS_AN_COMPLETE_IN : in std_logic;
-- signals to/from hub
+ MC_UNIQUE_ID_IN : in std_logic_vector(63 downto 0);
+
+ GSC_CLK_IN : in std_logic;
+ GSC_INIT_DATAREADY_OUT : out std_logic;
+ GSC_INIT_DATA_OUT : out std_logic_vector(15 downto 0);
+ GSC_INIT_PACKET_NUM_OUT : out std_logic_vector(2 downto 0);
+ GSC_INIT_READ_IN : in std_logic;
+ GSC_REPLY_DATAREADY_IN : in std_logic;
+ GSC_REPLY_DATA_IN : in std_logic_vector(15 downto 0);
+ GSC_REPLY_PACKET_NUM_IN : in std_logic_vector(2 downto 0);
+ GSC_REPLY_READ_OUT : out std_logic;
+ GSC_BUSY_IN : in std_logic;
-- signal to/from Host interface of TriSpeed MAC
TSM_HADDR_OUT : out std_logic_vector(7 downto 0);
TSM_HREAD_N_OUT : out std_logic;
TSM_HREADY_N_IN : in std_logic;
TSM_HDATA_EN_N_IN : in std_logic;
+ TSM_RX_STAT_VEC_IN : in std_logic_vector(31 downto 0);
+ TSM_RX_STAT_EN_IN : in std_logic;
SELECT_REC_FRAMES_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 16 - 1 downto 0);
SELECT_SENT_FRAMES_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 16 - 1 downto 0);
--attribute HGROUP : string;
--attribute HGROUP of trb_net16_gbe_main_control : architecture is "GBE_MAIN_group";
-signal saved_frame_req : std_logic;
-signal saved_frame_req_q : std_logic;
-signal saved_frame_req_t : std_logic;
-
signal tsm_ready : std_logic;
signal tsm_reconf : std_logic;
signal tsm_haddr : std_logic_vector(7 downto 0);
signal ps_busy_q : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
signal rc_frame_proto_q : std_Logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
-type redirect_states is (IDLE, CHECK_BUSY, LOAD, BUSY, FINISH, CLEANUP);
+type redirect_states is (IDLE, CHECK_TYPE, DROP, CHECK_BUSY, LOAD, BUSY, FINISH, CLEANUP);
signal redirect_current_state, redirect_next_state : redirect_states;
signal frame_type : std_logic_vector(15 downto 0);
+signal disable_redirect, ps_wr_en_q : std_logic;
+
+type stats_states is (IDLE, LOAD_VECTOR, CLEANUP);
+signal stats_current_state, stats_next_state : stats_states;
+
+signal stat_rdy, stat_ack : std_logic;
+signal rx_stat_en_q : std_logic;
+signal rx_stat_vec_q : std_logic_vector(31 downto 0);
+
+type array_of_ctrs is array(15 downto 0) of std_logic_vector(31 downto 0);
+signal arr : array_of_ctrs;
+signal stats_ctr : integer range 0 to 15;
+signal stat_data : std_logic_vector(31 downto 0);
+signal stat_addr : std_logic_vector(7 downto 0);
+
begin
RESET => RESET,
PS_DATA_IN => rc_data_local, -- RC_DATA_IN,
- PS_WR_EN_IN => ps_wr_en,
+ PS_WR_EN_IN => ps_wr_en_q, --ps_wr_en,
PS_PROTO_SELECT_IN => proto_select,
PS_BUSY_OUT => ps_busy,
PS_FRAME_SIZE_IN => RC_FRAME_SIZE_IN,
DHCP_START_IN => dhcp_start,
DHCP_DONE_OUT => dhcp_done,
+ GSC_CLK_IN => GSC_CLK_IN,
+ GSC_INIT_DATAREADY_OUT => GSC_INIT_DATAREADY_OUT,
+ GSC_INIT_DATA_OUT => GSC_INIT_DATA_OUT,
+ GSC_INIT_PACKET_NUM_OUT => GSC_INIT_PACKET_NUM_OUT,
+ GSC_INIT_READ_IN => GSC_INIT_READ_IN,
+ GSC_REPLY_DATAREADY_IN => GSC_REPLY_DATAREADY_IN,
+ GSC_REPLY_DATA_IN => GSC_REPLY_DATA_IN,
+ GSC_REPLY_PACKET_NUM_IN => GSC_REPLY_PACKET_NUM_IN,
+ GSC_REPLY_READ_OUT => GSC_REPLY_READ_OUT,
+ GSC_BUSY_IN => GSC_BUSY_IN,
+
+ -- input for statistics from outside
+ STAT_DATA_IN => stat_data,
+ STAT_ADDR_IN => stat_addr,
+ STAT_DATA_RDY_IN => stat_rdy,
+ STAT_DATA_ACK_OUT => stat_ack,
+
+
DEBUG_OUT => open
);
TC_FRAME_TYPE_OUT <= frame_type when flow_current_state = TRANSMIT_CTRL else x"0008";
-proto_select <= RC_FRAME_PROTO_IN;
---proto_select <= (others => '0') when (redirect_current_state = IDLE and RC_FRAME_WAITING_IN = '0')
--- else RC_FRAME_PROTO_IN;
+-- gk 07.11.11
+-- do not select any response constructors when dropping a frame
+proto_select <= RC_FRAME_PROTO_IN when disable_redirect = '0' else (others => '0');
+-- gk 07.11.11
+DISABLE_REDIRECT_PROC : process(CLK)
+begin
+ if rising_edge(CLK) then
+ if (RESET = '1') then
+ disable_redirect <= '0';
+ elsif (redirect_current_state = CHECK_TYPE) then
+ if (link_current_state /= ACTIVE and link_current_state /= GET_ADDRESS) then
+ disable_redirect <= '1';
+ elsif (link_current_state = GET_ADDRESS and RC_FRAME_PROTO_IN /= "10") then
+ disable_redirect <= '1';
+ else
+ disable_redirect <= '0';
+ end if;
+ end if;
+ end if;
+end process DISABLE_REDIRECT_PROC;
+
+-- warning
SYNC_PROC : process(CLK)
begin
if rising_edge(CLK) then
when IDLE =>
redirect_state <= x"1";
- if (RC_FRAME_WAITING_IN = '1') and (link_current_state = ACTIVE or link_current_state = GET_ADDRESS) then
- -- if (or_all(ps_busy and RC_FRAME_PROTO_IN) = '0') then
- -- redirect_next_state <= LOAD;
- -- else
- -- redirect_next_state <= BUSY;
- -- end if;
- redirect_next_state <= CHECK_BUSY;
+ if (RC_FRAME_WAITING_IN = '1') then
+ redirect_next_state <= CHECK_TYPE;
else
redirect_next_state <= IDLE;
end if;
+ -- gk 16.11.11
+ when CHECK_TYPE =>
+ if (link_current_state = ACTIVE) then
+ redirect_next_state <= CHECK_BUSY;
+ elsif (link_current_state = GET_ADDRESS and RC_FRAME_PROTO_IN = "10") then
+ redirect_next_state <= CHECK_BUSY;
+ else
+ redirect_next_state <= DROP;
+ end if;
+ -- gk 07.11.11
+ when DROP =>
+ redirect_state <= x"7";
+ if (loaded_bytes_ctr = RC_FRAME_SIZE_IN - x"1") then
+ redirect_next_state <= FINISH;
+ else
+ redirect_next_state <= DROP;
+ end if;
when CHECK_BUSY =>
redirect_state <= x"6";
if (or_all(ps_busy and RC_FRAME_PROTO_IN) = '0') then
when LOAD =>
redirect_state <= x"2";
- --if (RC_DATA_IN(8) = '1') and (ps_wr_en = '1') then
if (loaded_bytes_ctr = RC_FRAME_SIZE_IN - x"1") then
redirect_next_state <= FINISH;
else
end case;
end process REDIRECT_MACHINE;
-rc_rd_en <= '1' when redirect_current_state = LOAD else '0';
+rc_rd_en <= '1' when redirect_current_state = LOAD or redirect_current_state = DROP else '0';
RC_RD_EN_OUT <= rc_rd_en;
---RC_RD_EN_PROC : process(CLK)
---begin
--- if rising_edge(CLK) then
--- if (RESET = '1') then
--- rc_rd_en <= '0';
--- elsif (redirect_current_state = LOAD) then
--- rc_rd_en <= '1';
--- else
--- rc_rd_en <= '0';
--- end if;
--- end if;
---end process;
-
LOADING_DONE_PROC : process(CLK)
begin
if rising_edge(CLK) then
end if;
end if;
end process LOADING_DONE_PROC;
---RC_LOADING_DONE_OUT <= '1' when (RC_DATA_IN(8) = '1') and (ps_wr_en = '1') else '0';
PS_WR_EN_PROC : process(CLK)
begin
if rising_edge(CLK) then
- ps_wr_en <= rc_rd_en;
+ ps_wr_en <= rc_rd_en;
+ ps_wr_en_q <= ps_wr_en;
end if;
end process PS_WR_EN_PROC;
if rising_edge(CLK) then
if (RESET = '1') or (redirect_current_state = IDLE) then
loaded_bytes_ctr <= (others => '0');
- elsif (redirect_current_state = LOAD) and (rc_rd_en = '1') then
+ elsif (redirect_current_state = LOAD or redirect_current_state = DROP) and (rc_rd_en = '1') then
loaded_bytes_ctr <= loaded_bytes_ctr + x"1";
end if;
end if;
TC_TRANSMIT_CTRL_OUT <= '1' when (flow_current_state = TRANSMIT_CTRL) else '0';
-
---RC_LOADING_DONE_OUT <= '1' when (flow_current_state = TRANSMIT_CTRL) and (TC_TRANSMIT_DONE_IN = '1') else '0';
-
--***********************
-- LINK STATE CONTROL
begin
if rising_edge(CLK) then
if (RESET = '1') then
- link_current_state <= INACTIVE;
- --link_current_state <= ACTIVE; -- for simulation only
+ if (g_SIMULATE = 0) then
+ link_current_state <= INACTIVE;
+ else
+ link_current_state <= ACTIVE;
+ end if;
else
link_current_state <= link_next_state;
end if;
when ACTIVE =>
link_state <= x"1";
if (PCS_AN_COMPLETE_IN = '0') then
- link_next_state <= INACTIVE; --ENABLE_MAC;
+ link_next_state <= INACTIVE;
else
link_next_state <= ACTIVE;
end if;
link_state <= x"2";
if (PCS_AN_COMPLETE_IN = '1') then
link_next_state <= TIMEOUT;
- --link_next_state <= GET_ADDRESS; -- for simulation only
else
link_next_state <= INACTIVE;
end if;
link_next_state <= INACTIVE;
else
if (wait_ctr = x"3baa_ca00") then
- --if (wait_ctr = x"0000_0010") then -- for simulation
link_next_state <= GET_ADDRESS;
else
link_next_state <= WAIT_FOR_BOOT;
--***************
+-- *****
+-- STATISTICS
+-- *****
+
+
+CTRS_GEN : for n in 0 to 15 generate
+
+ CTR_PROC : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if (RESET = '1') then
+ arr(n) <= (others => '0');
+ elsif (rx_stat_en_q = '1' and rx_stat_vec_q(16 + n) = '1') then
+ arr(n) <= arr(n) + x"1";
+ end if;
+ end if;
+ end process CTR_PROC;
+
+end generate CTRS_GEN;
+
+STAT_VEC_SYNC : signal_sync
+generic map (
+ WIDTH => 32,
+ DEPTH => 2
+)
+port map (
+ RESET => RESET,
+ CLK0 => CLK,
+ CLK1 => CLK,
+ D_IN => TSM_RX_STAT_VEC_IN,
+ D_OUT => rx_stat_vec_q
+);
+
+
+STAT_VEC_EN_SYNC : pulse_sync
+port map(
+ CLK_A_IN => CLK_125,
+ RESET_A_IN => RESET,
+ PULSE_A_IN => TSM_RX_STAT_EN_IN,
+ CLK_B_IN => CLK,
+ RESET_B_IN => RESET,
+ PULSE_B_OUT => rx_stat_en_q
+);
+
+
+STATS_MACHINE_PROC : process(CLK)
+begin
+ if rising_edge(CLK) then
+ if (RESET = '1') then
+ stats_current_state <= IDLE;
+ else
+ stats_current_state <= stats_next_state;
+ end if;
+ end if;
+end process STATS_MACHINE_PROC;
+
+STATS_MACHINE : process(stats_current_state, rx_stat_en_q, stats_ctr)
+begin
+
+ case (stats_current_state) is
+
+ when IDLE =>
+ if (rx_stat_en_q = '1') then
+ stats_next_state <= LOAD_VECTOR;
+ else
+ stats_next_state <= IDLE;
+ end if;
+
+ when LOAD_VECTOR =>
+ --if (stat_ack = '1') then
+ if (stats_ctr = 15) then
+ stats_next_state <= CLEANUP;
+ else
+ stats_next_state <= LOAD_VECTOR;
+ end if;
+
+ when CLEANUP =>
+ stats_next_state <= IDLE;
+
+ end case;
+
+end process STATS_MACHINE;
+
+STATS_CTR_PROC : process(CLK)
+begin
+ if rising_edge(CLK) then
+ if (RESET = '1') or (stats_current_state = IDLE) then
+ stats_ctr <= 0;
+ elsif (stats_current_state = LOAD_VECTOR and stat_ack ='1') then
+ stats_ctr <= stats_ctr + 1;
+ end if;
+ end if;
+end process STATS_CTR_PROC;
+
+--stat_data <= arr(stats_ctr);
+
+stat_addr <= x"0c" + std_logic_vector(to_unsigned(stats_ctr, 8));
+
+stat_rdy <= '1' when stats_current_state /= IDLE and stats_current_state /= CLEANUP else '0';
+
+stat_data(7 downto 0) <= arr(stats_ctr)(31 downto 24);
+stat_data(15 downto 8) <= arr(stats_ctr)(23 downto 16);
+stat_data(23 downto 16) <= arr(stats_ctr)(15 downto 8);
+stat_data(31 downto 24) <= arr(stats_ctr)(7 downto 0);
+
+
-- **** debug
FRAME_WAITING_CTR_PROC : process(CLK)
begin
-- No. 2 = DHCP
if (UDP_PROTOCOL_IN = x"0044") then -- DHCP Client
CODE_OUT(1) <= '1';
+ -- No. 4 = SCTRL
+ elsif (UDP_PROTOCOL_IN = x"61a8") then -- SCTRL module
+ CODE_OUT(3) <= '1';
else
-- branch for pure IPv4
CODE_OUT <= (others => '0');
-- No. 3 = ICMP
elsif (PROTOCOL_CODE_IN = x"01") then -- ICMP
CODE_OUT(2) <= '1';
- -- No. 4 = Test1a
- elsif (PROTOCOL_CODE_IN = x"dd") then -- Test1 b
- CODE_OUT(3) <= '1';
- -- No. 5 = Test1b
- elsif (PROTOCOL_CODE_IN = x"ee") then -- Test1 a
- CODE_OUT(4) <= '1';
else
- CODE_OUT <= (others => '0'); -- vector full of 1 means invalid protocol
+ CODE_OUT <= (others => '0');
end if;
-- No. 1 = ARP
-- misc signals for response constructors
DHCP_START_IN : in std_logic;
DHCP_DONE_OUT : out std_logic;
+
+ GSC_CLK_IN : in std_logic;
+ GSC_INIT_DATAREADY_OUT : out std_logic;
+ GSC_INIT_DATA_OUT : out std_logic_vector(15 downto 0);
+ GSC_INIT_PACKET_NUM_OUT : out std_logic_vector(2 downto 0);
+ GSC_INIT_READ_IN : in std_logic;
+ GSC_REPLY_DATAREADY_IN : in std_logic;
+ GSC_REPLY_DATA_IN : in std_logic_vector(15 downto 0);
+ GSC_REPLY_PACKET_NUM_IN : in std_logic_vector(2 downto 0);
+ GSC_REPLY_READ_OUT : out std_logic;
+ GSC_BUSY_IN : in std_logic;
+
+ -- input for statistics from outside
+ STAT_DATA_IN : in std_logic_vector(31 downto 0);
+ STAT_ADDR_IN : in std_logic_vector(7 downto 0);
+ STAT_DATA_RDY_IN : in std_logic;
+ STAT_DATA_ACK_OUT : out std_logic;
DEBUG_OUT : out std_logic_vector(63 downto 0)
);
signal tc_src_udp : std_logic_vector(c_MAX_PROTOCOLS * 16 - 1 downto 0);
signal tc_ip_proto : std_logic_vector(c_MAX_PROTOCOLS * 8 - 1 downto 0);
+-- plus 1 is for the outside
+signal stat_data : std_logic_vector((c_MAX_PROTOCOLS + 1) * 32 - 1 downto 0);
+signal stat_addr : std_logic_vector((c_MAX_PROTOCOLS + 1) * 8 - 1 downto 0);
+signal stat_rdy : std_logic_vector((c_MAX_PROTOCOLS + 1) - 1 downto 0);
+signal stat_ack : std_logic_vector((c_MAX_PROTOCOLS + 1) - 1 downto 0);
+
begin
-- protocol Nr. 1 ARP
ARP : trb_net16_gbe_response_constructor_ARP
+generic map( STAT_ADDRESS_BASE => 6
+)
port map (
CLK => CLK,
RESET => RESET,
TC_BUSY_IN => TC_BUSY_IN,
+ STAT_DATA_OUT => stat_data(1 * 32 - 1 downto 0 * 32),
+ STAT_ADDR_OUT => stat_addr(1 * 8 - 1 downto 0 * 8),
+ STAT_DATA_RDY_OUT => stat_rdy(0),
+ STAT_DATA_ACK_IN => stat_ack(0),
RECEIVED_FRAMES_OUT => RECEIVED_FRAMES_OUT(1 * 16 - 1 downto 0 * 16),
SENT_FRAMES_OUT => SENT_FRAMES_OUT(1 * 16 - 1 downto 0 * 16),
DEBUG_OUT => PROTOS_DEBUG_OUT(1 * 32 - 1 downto 0 * 32)
-- protocol No. 2 DHCP
DHCP : trb_net16_gbe_response_constructor_DHCP
+generic map( STAT_ADDRESS_BASE => 0
+)
port map (
CLK => CLK,
RESET => RESET,
TC_BUSY_IN => TC_BUSY_IN,
+ STAT_DATA_OUT => stat_data(2 * 32 - 1 downto 1 * 32),
+ STAT_ADDR_OUT => stat_addr(2 * 8 - 1 downto 1 * 8),
+ STAT_DATA_RDY_OUT => stat_rdy(1),
+ STAT_DATA_ACK_IN => stat_ack(1),
RECEIVED_FRAMES_OUT => RECEIVED_FRAMES_OUT(2 * 16 - 1 downto 1 * 16),
SENT_FRAMES_OUT => SENT_FRAMES_OUT(2 * 16 - 1 downto 1 * 16),
-- END OF INTERFACE
-- protocol No. 3 Ping
Ping : trb_net16_gbe_response_constructor_Ping
+generic map( STAT_ADDRESS_BASE => 3
+)
port map (
CLK => CLK,
RESET => RESET,
TC_BUSY_IN => TC_BUSY_IN,
+ STAT_DATA_OUT => stat_data(3 * 32 - 1 downto 2 * 32),
+ STAT_ADDR_OUT => stat_addr(3 * 8 - 1 downto 2 * 8),
+ STAT_DATA_RDY_OUT => stat_rdy(2),
+ STAT_DATA_ACK_IN => stat_ack(2),
RECEIVED_FRAMES_OUT => RECEIVED_FRAMES_OUT(3 * 16 - 1 downto 2 * 16),
SENT_FRAMES_OUT => SENT_FRAMES_OUT(3 * 16 - 1 downto 2 * 16),
DEBUG_OUT => PROTOS_DEBUG_OUT(3 * 32 - 1 downto 2 * 32)
-- END OF INTERFACE
);
-Test1a : trb_net16_gbe_response_constructor_Test1
+SCTRL : trb_net16_gbe_response_constructor_SCTRL
+generic map( STAT_ADDRESS_BASE => 8
+)
port map (
CLK => CLK,
RESET => RESET,
TC_BUSY_IN => TC_BUSY_IN,
+ STAT_DATA_OUT => stat_data(4 * 32 - 1 downto 3 * 32),
+ STAT_ADDR_OUT => stat_addr(4 * 8 - 1 downto 3 * 8),
+ STAT_DATA_RDY_OUT => stat_rdy(3),
+ STAT_DATA_ACK_IN => stat_ack(3),
RECEIVED_FRAMES_OUT => RECEIVED_FRAMES_OUT(4 * 16 - 1 downto 3 * 16),
SENT_FRAMES_OUT => SENT_FRAMES_OUT(4 * 16 - 1 downto 3 * 16),
+ -- END OF INTERFACE
+
+ GSC_CLK_IN => GSC_CLK_IN,
+ GSC_INIT_DATAREADY_OUT => GSC_INIT_DATAREADY_OUT,
+ GSC_INIT_DATA_OUT => GSC_INIT_DATA_OUT,
+ GSC_INIT_PACKET_NUM_OUT => GSC_INIT_PACKET_NUM_OUT,
+ GSC_INIT_READ_IN => GSC_INIT_READ_IN,
+ GSC_REPLY_DATAREADY_IN => GSC_REPLY_DATAREADY_IN,
+ GSC_REPLY_DATA_IN => GSC_REPLY_DATA_IN,
+ GSC_REPLY_PACKET_NUM_IN => GSC_REPLY_PACKET_NUM_IN,
+ GSC_REPLY_READ_OUT => GSC_REPLY_READ_OUT,
+ GSC_BUSY_IN => GSC_BUSY_IN,
+
+
DEBUG_OUT => PROTOS_DEBUG_OUT(4 * 32 - 1 downto 3 * 32)
--- END OF INTERFACE
);
-Test1b : trb_net16_gbe_response_constructor_Test1
+Stat : trb_net16_gbe_response_constructor_Stat
+generic map( STAT_ADDRESS_BASE => 10
+)
port map (
CLK => CLK,
RESET => RESET,
TC_BUSY_IN => TC_BUSY_IN,
+ STAT_DATA_OUT => stat_data(5 * 32 - 1 downto 4 * 32),
+ STAT_ADDR_OUT => stat_addr(5 * 8 - 1 downto 4 * 8),
+ STAT_DATA_RDY_OUT => stat_rdy(4),
+ STAT_DATA_ACK_IN => stat_ack(4),
+
RECEIVED_FRAMES_OUT => RECEIVED_FRAMES_OUT(5 * 16 - 1 downto 4 * 16),
SENT_FRAMES_OUT => SENT_FRAMES_OUT(5 * 16 - 1 downto 4 * 16),
- DEBUG_OUT => PROTOS_DEBUG_OUT(5 * 32 - 1 downto 4 * 32)
+ DEBUG_OUT => PROTOS_DEBUG_OUT(5 * 32 - 1 downto 4 * 32),
+
+ STAT_DATA_IN => stat_data,
+ STAT_ADDR_IN => stat_addr,
+ STAT_DATA_RDY_IN => stat_rdy,
+ STAT_DATA_ACK_OUT => stat_ack
);
--***************
-- DO NOT TOUCH, response selection logic
+
+stat_data((c_MAX_PROTOCOLS + 1) * 32 - 1 downto c_MAX_PROTOCOLS * 32) <= STAT_DATA_IN;
+stat_addr((c_MAX_PROTOCOLS + 1) * 8 - 1 downto c_MAX_PROTOCOLS * 8) <= STAT_ADDR_IN;
+stat_rdy(c_MAX_PROTOCOLS) <= STAT_DATA_RDY_IN;
+STAT_DATA_ACK_OUT <= stat_ack(c_MAX_PROTOCOLS);
+
+
PS_BUSY_OUT <= busy;
SELECTOR_PROC : process(CLK)
-- creates a reply for an incoming ARP request
entity trb_net16_gbe_response_constructor_ARP is
+generic ( STAT_ADDRESS_BASE : integer := 0
+);
port (
CLK : in std_logic; -- system clock
RESET : in std_logic;
TC_BUSY_IN : in std_logic;
+ STAT_DATA_OUT : out std_logic_vector(31 downto 0);
+ STAT_ADDR_OUT : out std_logic_vector(7 downto 0);
+ STAT_DATA_RDY_OUT : out std_logic;
+ STAT_DATA_ACK_IN : in std_logic;
RECEIVED_FRAMES_OUT : out std_logic_vector(15 downto 0);
SENT_FRAMES_OUT : out std_logic_vector(15 downto 0);
-- END OF INTERFACE
signal dissect_current_state, dissect_next_state : dissect_states;
attribute syn_encoding of dissect_current_state: signal is "safe,gray";
+type stats_states is (IDLE, LOAD_SENT, LOAD_RECEIVED, CLEANUP);
+signal stats_current_state, stats_next_state : stats_states;
+attribute syn_encoding of stats_current_state : signal is "safe,gray";
signal saved_opcode : std_logic_vector(15 downto 0);
signal saved_sender_ip : std_logic_vector(31 downto 0);
signal saved_target_ip : std_logic_vector(31 downto 0);
signal state : std_logic_vector(3 downto 0);
signal rec_frames : std_logic_vector(15 downto 0);
signal sent_frames : std_logic_vector(15 downto 0);
+signal stat_data_temp : std_logic_vector(31 downto 0);
begin
DATA_CTR_PROC : process(CLK)
begin
if rising_edge(CLK) then
- if (RESET = '1') or (dissect_current_state = IDLE) or (dissect_current_state = WAIT_FOR_LOAD) then
+ if (RESET = '1') or (dissect_current_state = IDLE and PS_WR_EN_IN = '0') or (dissect_current_state = WAIT_FOR_LOAD) then
data_ctr <= 1;
+ elsif (dissect_current_state = IDLE and PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then
+ data_ctr <= data_ctr + 1;
elsif (dissect_current_state = READ_FRAME and PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then -- in case of saving data from incoming frame
data_ctr <= data_ctr + 1;
elsif (dissect_current_state = LOAD_FRAME and TC_RD_EN_IN = '1' and PS_SELECTED_IN = '1') then -- in case of constructing response
RECEIVED_FRAMES_OUT <= rec_frames;
SENT_FRAMES_OUT <= sent_frames;
+STATS_MACHINE_PROC : process(CLK)
+begin
+ if rising_edge(CLK) then
+ if (RESET = '1') then
+ stats_current_state <= IDLE;
+ else
+ stats_current_state <= stats_next_state;
+ end if;
+ end if;
+end process STATS_MACHINE_PROC;
+
+STATS_MACHINE : process(stats_current_state, PS_WR_EN_IN, PS_ACTIVATE_IN, dissect_current_state)
+begin
+
+ case (stats_current_state) is
+
+ when IDLE =>
+ if (dissect_current_state = IDLE and PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') or (dissect_current_state = CLEANUP) then
+ stats_next_state <= LOAD_SENT;
+ else
+ stats_next_state <= IDLE;
+ end if;
+
+ when LOAD_SENT =>
+ if (STAT_DATA_ACK_IN = '1') then
+ stats_next_state <= LOAD_RECEIVED;
+ else
+ stats_next_state <= LOAD_SENT;
+ end if;
+
+ when LOAD_RECEIVED =>
+ if (STAT_DATA_ACK_IN = '1') then
+ stats_next_state <= CLEANUP;
+ else
+ stats_next_state <= LOAD_RECEIVED;
+ end if;
+
+ when CLEANUP =>
+ stats_next_state <= IDLE;
+
+ end case;
+
+end process STATS_MACHINE;
+
+SELECTOR : process(stats_current_state)
+begin
+
+ case(stats_current_state) is
+
+ when LOAD_SENT =>
+ stat_data_temp <= x"0601" & sent_frames;
+ STAT_ADDR_OUT <= std_logic_vector(to_unsigned(STAT_ADDRESS_BASE, 8));
+
+ when LOAD_RECEIVED =>
+ stat_data_temp <= x"0602" & rec_frames;
+ STAT_ADDR_OUT <= std_logic_vector(to_unsigned(STAT_ADDRESS_BASE + 1, 8));
+
+ when others =>
+ stat_data_temp <= (others => '0');
+ STAT_ADDR_OUT <= (others => '0');
+
+ end case;
+
+end process SELECTOR;
+
+STAT_DATA_OUT(7 downto 0) <= stat_data_temp(31 downto 24);
+STAT_DATA_OUT(15 downto 8) <= stat_data_temp(23 downto 16);
+STAT_DATA_OUT(23 downto 16) <= stat_data_temp(15 downto 8);
+STAT_DATA_OUT(31 downto 24) <= stat_data_temp(7 downto 0);
+
+STAT_DATA_RDY_OUT <= '1' when stats_current_state /= IDLE and stats_current_state /= CLEANUP else '0';
-- **** debug
DEBUG_OUT(3 downto 0) <= state;
--
entity trb_net16_gbe_response_constructor_DHCP is
+generic ( STAT_ADDRESS_BASE : integer := 0
+);
port (
CLK : in std_logic; -- system clock
RESET : in std_logic;
TC_BUSY_IN : in std_logic;
+ STAT_DATA_OUT : out std_logic_vector(31 downto 0);
+ STAT_ADDR_OUT : out std_logic_vector(7 downto 0);
+ STAT_DATA_RDY_OUT : out std_logic;
+ STAT_DATA_ACK_IN : in std_logic;
RECEIVED_FRAMES_OUT : out std_logic_vector(15 downto 0);
SENT_FRAMES_OUT : out std_logic_vector(15 downto 0);
-- END OF INTERFACE
signal construct_current_state, construct_next_state : discover_states;
attribute syn_encoding of construct_current_state: signal is "safe,gray";
+
+type stats_states is (IDLE, LOAD_SENT, LOAD_RECEIVED, LOAD_DISCARDED, CLEANUP);
+signal stats_current_state, stats_next_state : stats_states;
+attribute syn_encoding of stats_current_state : signal is "safe,gray";
+
signal state : std_logic_vector(3 downto 0);
signal rec_frames : std_logic_vector(15 downto 0);
signal sent_frames : std_logic_vector(15 downto 0);
signal discarded_ctr : std_logic_vector(15 downto 0);
+
+signal stat_data_temp : std_logic_vector(31 downto 0);
+
begin
SAVE_SERVER_ADDR_PROC : process(CLK)
begin
if rising_edge(CLK) then
- if (RESET = '1') then
+ if (RESET = '1') or (main_current_state = BOOTING) then
saved_server_mac <= (others => '0');
saved_server_ip <= (others => '0');
elsif (main_current_state = WAITING_FOR_OFFER) and (receive_current_state = SAVE_VALUES and save_ctr = 1) then
when BOOTING =>
state2 <= x"1";
if (DHCP_START_IN = '1') then
- --if (wait_ctr = x"3baa_ca00") then -- wait for 10 sec
- --if (wait_ctr = x"0000_0010") then -- for sim only
main_next_state <= SENDING_DISCOVER;
else
main_next_state <= BOOTING;
state2 <= x"3";
if (receive_current_state = SAVE_VALUES) and (PS_DATA_IN(8) = '1') then
main_next_state <= SENDING_REQUEST;
+ elsif (wait_ctr = x"ffff_ffff") then
+ main_next_state <= BOOTING;
else
main_next_state <= WAITING_FOR_OFFER;
end if;
state2 <= x"5";
if (receive_current_state = SAVE_VALUES) and (PS_DATA_IN(8) = '1') then
main_next_state <= ESTABLISHED;
+ elsif (wait_ctr = x"ffff_ffff") then
+ main_next_state <= BOOTING;
else
main_next_state <= WAITING_FOR_ACK;
end if;
WAIT_CTR_PROC : process(CLK)
begin
if rising_edge(CLK) then
- if (RESET = '1') or (main_current_state = ESTABLISHED) then
+ if (RESET = '1') or (main_current_state = BOOTING or main_current_state = SENDING_DISCOVER or main_current_state = SENDING_REQUEST) then
wait_ctr <= (others => '0');
- elsif (main_current_state = BOOTING) then
+ elsif (main_current_state = WAITING_FOR_ACK or main_current_state = WAITING_FOR_OFFER) then
wait_ctr <= wait_ctr + x"1";
end if;
end if;
RECEIVE_MACHINE_PROC : process(CLK)
begin
if rising_edge(CLK) then
- if (RESET = '1') then
+ if (RESET = '1') or (main_current_state = BOOTING) then
receive_current_state <= IDLE;
else
receive_current_state <= receive_next_state;
state3 <= x"1";
if (PS_ACTIVATE_IN = '1' and PS_WR_EN_IN = '1') then
if (main_current_state = WAITING_FOR_OFFER or main_current_state = WAITING_FOR_ACK) then -- ready to receive dhcp frame
- if (PS_DEST_MAC_ADDRESS_IN = g_MY_MAC) then -- check if i'm the addressee (discards broadcasts also)
+ if (PS_DEST_MAC_ADDRESS_IN = g_MY_MAC) or (PS_DEST_MAC_ADDRESS_IN = x"ffffffffffff") then -- check if i'm the addressee (discards broadcasts also)
receive_next_state <= SAVE_VALUES;
else
receive_next_state <= DISCARD; -- discard if the frame is not for me
SAVE_VALUES_PROC : process(CLK)
begin
if rising_edge(CLK) then
- if (RESET = '1') then
+ if (RESET = '1') or (main_current_state = BOOTING) then
saved_transaction_id <= (others => '0');
saved_proposed_ip <= (others => '0');
saved_dhcp_type <= (others => '0');
CONSTRUCT_MACHINE_PROC : process(CLK)
begin
if rising_edge(CLK) then
- if (RESET = '1') then
+ if (RESET = '1') or (main_current_state = BOOTING) then
construct_current_state <= IDLE;
else
construct_current_state <= construct_next_state;
RECEIVED_FRAMES_OUT <= rec_frames;
SENT_FRAMES_OUT <= sent_frames;
+
+STATS_MACHINE_PROC : process(CLK)
+begin
+ if rising_edge(CLK) then
+ if (RESET = '1') then
+ stats_current_state <= IDLE;
+ else
+ stats_current_state <= stats_next_state;
+ end if;
+ end if;
+end process STATS_MACHINE_PROC;
+
+STATS_MACHINE : process(stats_current_state, STAT_DATA_ACK_IN, PS_DATA_IN, construct_current_state, receive_current_state)
+begin
+
+ case (stats_current_state) is
+
+ when IDLE =>
+ if (receive_current_state = SAVE_VALUES and PS_DATA_IN(8) = '1') or (construct_current_state = CLEANUP) or (receive_current_state = DISCARD and PS_DATA_IN(8) = '1') then
+ stats_next_state <= LOAD_SENT;
+ else
+ stats_next_state <= IDLE;
+ end if;
+
+ when LOAD_SENT =>
+ if (STAT_DATA_ACK_IN = '1') then
+ stats_next_state <= LOAD_RECEIVED;
+ else
+ stats_next_state <= LOAD_SENT;
+ end if;
+
+ when LOAD_RECEIVED =>
+ if (STAT_DATA_ACK_IN = '1') then
+ stats_next_state <= LOAD_DISCARDED;
+ else
+ stats_next_state <= LOAD_RECEIVED;
+ end if;
+
+ when LOAD_DISCARDED =>
+ if (STAT_DATA_ACK_IN = '1') then
+ stats_next_state <= CLEANUP;
+ else
+ stats_next_state <= LOAD_DISCARDED;
+ end if;
+
+ when CLEANUP =>
+ stats_next_state <= IDLE;
+
+ end case;
+
+end process STATS_MACHINE;
+
+SELECTOR : process(stats_current_state)
+begin
+
+ case(stats_current_state) is
+
+ when LOAD_SENT =>
+ stat_data_temp <= x"0101" & sent_frames;
+ STAT_ADDR_OUT <= std_logic_vector(to_unsigned(STAT_ADDRESS_BASE, 8));
+
+ when LOAD_RECEIVED =>
+ stat_data_temp <= x"0102" & rec_frames;
+ STAT_ADDR_OUT <= std_logic_vector(to_unsigned(STAT_ADDRESS_BASE + 1, 8));
+
+ when LOAD_DISCARDED =>
+ stat_data_temp <= x"0103" & discarded_ctr;
+ STAT_ADDR_OUT <= std_logic_vector(to_unsigned(STAT_ADDRESS_BASE + 2, 8));
+
+ when others =>
+ stat_data_temp <= (others => '0');
+ STAT_ADDR_OUT <= (others => '0');
+
+ end case;
+
+end process SELECTOR;
+
+STAT_DATA_OUT(7 downto 0) <= stat_data_temp(31 downto 24);
+STAT_DATA_OUT(15 downto 8) <= stat_data_temp(23 downto 16);
+STAT_DATA_OUT(23 downto 16) <= stat_data_temp(15 downto 8);
+STAT_DATA_OUT(31 downto 24) <= stat_data_temp(7 downto 0);
+
+STAT_DATA_RDY_OUT <= '1' when stats_current_state /= IDLE and stats_current_state /= CLEANUP else '0';
-- ****
--
entity trb_net16_gbe_response_constructor_Ping is
+generic ( STAT_ADDRESS_BASE : integer := 0
+);
port (
CLK : in std_logic; -- system clock
RESET : in std_logic;
TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0);
TC_BUSY_IN : in std_logic;
+ STAT_DATA_OUT : out std_logic_vector(31 downto 0);
+ STAT_ADDR_OUT : out std_logic_vector(7 downto 0);
+ STAT_DATA_RDY_OUT : out std_logic;
+ STAT_DATA_ACK_IN : in std_logic;
RECEIVED_FRAMES_OUT : out std_logic_vector(15 downto 0);
SENT_FRAMES_OUT : out std_logic_vector(15 downto 0);
signal dissect_current_state, dissect_next_state : dissect_states;
attribute syn_encoding of dissect_current_state: signal is "safe,gray";
+type stats_states is (IDLE, LOAD_SENT, LOAD_RECEIVED, CLEANUP);
+signal stats_current_state, stats_next_state : stats_states;
+attribute syn_encoding of stats_current_state : signal is "safe,gray";
signal state : std_logic_vector(3 downto 0);
signal rec_frames : std_logic_vector(15 downto 0);
signal saved_data : std_logic_vector(447 downto 0);
signal saved_headers : std_logic_vector(63 downto 0);
-signal data_ctr : integer range 1 to 66;
-signal data_length : integer range 1 to 66;
+signal data_ctr : integer range 1 to 1500;
+signal data_length : integer range 1 to 1500;
signal tc_data : std_logic_vector(8 downto 0);
signal checksum : std_logic_vector(15 downto 0);
+signal checksum_l, checksum_r : std_logic_vector(19 downto 0);
+signal checksum_ll, checksum_rr : std_logic_vector(15 downto 0);
+signal checksum_lll, checksum_rrr : std_logic_vector(15 downto 0);
+
+signal fifo_wr_en, fifo_rd_en : std_logic;
+signal fifo_q : std_logic_vector(7 downto 0);
+
+
+signal stat_data_temp : std_logic_vector(31 downto 0);
+
begin
DISSECT_MACHINE_PROC : process(CLK)
SAVE_VALUES_PROC : process(CLK)
begin
if rising_edge(CLK) then
- if (RESET = '1') then
+ if (RESET = '1') or (dissect_current_state = IDLE) then
saved_headers <= (others => '0');
saved_data <= (others => '0');
elsif (dissect_current_state = IDLE and PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then
elsif (dissect_current_state = READ_FRAME) then
if (data_ctr < 9) then -- headers
saved_headers(data_ctr * 8 - 1 downto (data_ctr - 1) * 8) <= PS_DATA_IN(7 downto 0);
- else
- saved_data((data_ctr - 8) * 8 - 1 downto (data_ctr - 9) * 8) <= PS_DATA_IN(7 downto 0);
end if;
elsif (dissect_current_state = LOAD_FRAME) then
saved_headers(7 downto 0) <= x"00";
- saved_headers(23 downto 16) <= checksum(15 downto 8);
- saved_headers(31 downto 24) <= checksum(7 downto 0);
+ saved_headers(23 downto 16) <= checksum(7 downto 0);
+ saved_headers(31 downto 24) <= checksum(15 downto 8);
end if;
end if;
end process SAVE_VALUES_PROC;
+fifo : fifo_2048x8
+ PORT map(
+ Reset => RESET,
+ RPReset => RESET,
+ WrClock => CLK,
+ RdClock => CLK,
+ Data => PS_DATA_IN(7 downto 0),
+ WrEn => fifo_wr_en,
+ RdEn => fifo_rd_en,
+ Q => fifo_q,
+ Full => open,
+ Empty => open
+ );
+
+fifo_wr_en <= '1' when (dissect_current_state = READ_FRAME and data_ctr > 8) else '0';
+fifo_rd_en <= '1' when (dissect_current_state = LOAD_FRAME and data_ctr > 8) else '0';
+
CS_PROC : process(CLK)
begin
if rising_edge(CLK) then
- if (RESET = '1') then
- checksum(15 downto 0) <= (others => '0');
+ if (RESET = '1') or (dissect_current_state = IDLE) then
+ checksum_l(19 downto 0) <= (others => '0');
+ checksum_r(19 downto 0) <= (others => '0');
+ checksum_ll(15 downto 0) <= (others => '0');
+ checksum_rr(15 downto 0) <= (others => '0');
+ checksum_lll(15 downto 0) <= (others => '0');
+ checksum_rrr(15 downto 0) <= (others => '0');
elsif (dissect_current_state = READ_FRAME and data_ctr > 4) then
if (std_logic_vector(to_unsigned(data_ctr, 1)) = "0") then
- checksum(7 downto 0) <= checksum(7 downto 0) + PS_DATA_IN(7 downto 0);
+ --checksum(7 downto 0) <= checksum(7 downto 0) + PS_DATA_IN(7 downto 0);
+ checksum_l <= checksum_l + PS_DATA_IN(7 downto 0);
else
- checksum(15 downto 8) <= checksum(15 downto 8) + PS_DATA_IN(7 downto 0);
+ --checksum(15 downto 8) <= checksum(15 downto 8) + PS_DATA_IN(7 downto 0);
+ checksum_r <= checksum_r + PS_DATA_IN(7 downto 0);
end if;
+ elsif (dissect_current_state = WAIT_FOR_LOAD and TC_BUSY_IN = '0') then
+ checksum_ll <= x"0000" + checksum_l(7 downto 0) + checksum_r(19 downto 8);
+ checksum_rr <= x"0000" + checksum_r(7 downto 0) + checksum_l(19 downto 8);
+ elsif (dissect_current_state = LOAD_FRAME and data_ctr = 2) then
+ checksum_lll <= x"0000" + checksum_ll(7 downto 0) + checksum_rr(15 downto 8);
+ checksum_rrr <= x"0000" + checksum_rr(7 downto 0) + checksum_ll(15 downto 8);
end if;
end if;
end process CS_PROC;
+checksum(7 downto 0) <= not (checksum_rrr(7 downto 0) + checksum_lll(15 downto 8));
+checksum(15 downto 8) <= not (checksum_lll(7 downto 0) + checksum_rrr(15 downto 8));
TC_DATA_PROC : process(dissect_current_state, data_ctr, saved_headers, saved_data, data_length)
begin
end loop;
else -- data
for i in 0 to 7 loop
- tc_data(i) <= saved_data((data_ctr - 10) * 8 + i);
+ tc_data(i) <= fifo_q(i); --saved_data((data_ctr - 10) * 8 + i);
end loop;
-- mark the last byte
TC_FRAME_SIZE_OUT <= std_logic_vector(to_unsigned(data_length, 16));
TC_FRAME_TYPE_OUT <= x"0008";
---TC_DEST_MAC_OUT <= x"9a680f201300";
---TC_DEST_IP_OUT <= x"00000000";
TC_DEST_UDP_OUT <= x"0000"; -- not used
TC_SRC_MAC_OUT <= g_MY_MAC;
TC_SRC_IP_OUT <= g_MY_IP;
RECEIVED_FRAMES_OUT <= rec_frames;
SENT_FRAMES_OUT <= sent_frames;
+RECEIVED_FRAMES_OUT <= rec_frames;
+SENT_FRAMES_OUT <= sent_frames;
+
+STATS_MACHINE_PROC : process(CLK)
+begin
+ if rising_edge(CLK) then
+ if (RESET = '1') then
+ stats_current_state <= IDLE;
+ else
+ stats_current_state <= stats_next_state;
+ end if;
+ end if;
+end process STATS_MACHINE_PROC;
+
+STATS_MACHINE : process(stats_current_state, PS_WR_EN_IN, PS_ACTIVATE_IN, STAT_DATA_ACK_IN, PS_DATA_IN,dissect_current_state, dissect_current_state)
+begin
+
+ case (stats_current_state) is
+
+ when IDLE =>
+ if (dissect_current_state = IDLE and PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') or (dissect_current_state = CLEANUP) then
+ stats_next_state <= LOAD_SENT;
+ else
+ stats_next_state <= IDLE;
+ end if;
+
+ when LOAD_SENT =>
+ if (STAT_DATA_ACK_IN = '1') then
+ stats_next_state <= LOAD_RECEIVED;
+ else
+ stats_next_state <= LOAD_SENT;
+ end if;
+
+ when LOAD_RECEIVED =>
+ if (STAT_DATA_ACK_IN = '1') then
+ stats_next_state <= CLEANUP;
+ else
+ stats_next_state <= LOAD_RECEIVED;
+ end if;
+
+ when CLEANUP =>
+ stats_next_state <= IDLE;
+
+ end case;
+
+end process STATS_MACHINE;
+
+SELECTOR : process(stats_current_state)
+begin
+
+ case(stats_current_state) is
+
+ when LOAD_SENT =>
+ stat_data_temp <= x"0401" & sent_frames;
+ STAT_ADDR_OUT <= std_logic_vector(to_unsigned(STAT_ADDRESS_BASE, 8));
+
+ when LOAD_RECEIVED =>
+ stat_data_temp <= x"0402" & rec_frames;
+ STAT_ADDR_OUT <= std_logic_vector(to_unsigned(STAT_ADDRESS_BASE + 1, 8));
+
+ when others =>
+ stat_data_temp <= (others => '0');
+ STAT_ADDR_OUT <= (others => '0');
+
+ end case;
+
+end process SELECTOR;
+
+STAT_DATA_OUT(7 downto 0) <= stat_data_temp(31 downto 24);
+STAT_DATA_OUT(15 downto 8) <= stat_data_temp(23 downto 16);
+STAT_DATA_OUT(23 downto 16) <= stat_data_temp(15 downto 8);
+STAT_DATA_OUT(31 downto 24) <= stat_data_temp(7 downto 0);
+
+STAT_DATA_RDY_OUT <= '1' when stats_current_state /= IDLE and stats_current_state /= CLEANUP else '0';
-- **** debug
DEBUG_OUT(3 downto 0) <= state;
--- /dev/null
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE IEEE.std_logic_UNSIGNED.ALL;
+
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+use work.trb_net16_hub_func.all;
+
+use work.trb_net_gbe_components.all;
+use work.trb_net_gbe_protocols.all;
+
+
+entity trb_net16_gbe_response_constructor_SCTRL is
+generic ( STAT_ADDRESS_BASE : integer := 0
+);
+ port (
+ CLK : in std_logic; -- system clock
+ RESET : in std_logic;
+
+ -- INTERFACE
+ PS_DATA_IN : in std_logic_vector(8 downto 0);
+ PS_WR_EN_IN : in std_logic;
+ PS_ACTIVATE_IN : in std_logic;
+ PS_RESPONSE_READY_OUT : out std_logic;
+ PS_BUSY_OUT : out std_logic;
+ PS_SELECTED_IN : in std_logic;
+ PS_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
+ PS_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
+ PS_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
+ PS_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
+ PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0);
+ PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0);
+
+ TC_RD_EN_IN : in std_logic;
+ TC_DATA_OUT : out std_logic_vector(8 downto 0);
+ TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0);
+ TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0);
+ TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0);
+ TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0);
+ TC_DEST_IP_OUT : out std_logic_vector(31 downto 0);
+ TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0);
+ TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0);
+ TC_SRC_IP_OUT : out std_logic_vector(31 downto 0);
+ TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0);
+
+ TC_BUSY_IN : in std_logic;
+
+ STAT_DATA_OUT : out std_logic_vector(31 downto 0);
+ STAT_ADDR_OUT : out std_logic_vector(7 downto 0);
+ STAT_DATA_RDY_OUT : out std_logic;
+ STAT_DATA_ACK_IN : in std_logic;
+
+ RECEIVED_FRAMES_OUT : out std_logic_vector(15 downto 0);
+ SENT_FRAMES_OUT : out std_logic_vector(15 downto 0);
+ -- END OF INTERFACE
+
+ -- protocol specific ports
+ GSC_CLK_IN : in std_logic;
+ GSC_INIT_DATAREADY_OUT : out std_logic;
+ GSC_INIT_DATA_OUT : out std_logic_vector(15 downto 0);
+ GSC_INIT_PACKET_NUM_OUT : out std_logic_vector(2 downto 0);
+ GSC_INIT_READ_IN : in std_logic;
+ GSC_REPLY_DATAREADY_IN : in std_logic;
+ GSC_REPLY_DATA_IN : in std_logic_vector(15 downto 0);
+ GSC_REPLY_PACKET_NUM_IN : in std_logic_vector(2 downto 0);
+ GSC_REPLY_READ_OUT : out std_logic;
+ GSC_BUSY_IN : in std_logic;
+ -- end of protocol specific ports
+
+ -- debug
+ DEBUG_OUT : out std_logic_vector(31 downto 0)
+ );
+end entity trb_net16_gbe_response_constructor_SCTRL;
+
+architecture RTL of trb_net16_gbe_response_constructor_SCTRL is
+
+attribute syn_encoding : string;
+
+type dissect_states is (IDLE, READ_FRAME, WAIT_FOR_HUB, LOAD_TO_HUB, WAIT_FOR_RESPONSE, SAVE_RESPONSE, LOAD_FRAME, WAIT_FOR_LOAD, CLEANUP);
+signal dissect_current_state, dissect_next_state : dissect_states;
+attribute syn_encoding of dissect_current_state: signal is "safe,gray";
+
+type stats_states is (IDLE, LOAD_RECEIVED, LOAD_REPLY, CLEANUP);
+signal stats_current_state, stats_next_state : stats_states;
+attribute syn_encoding of stats_current_state : signal is "safe,gray";
+
+signal saved_target_ip : std_logic_vector(31 downto 0);
+signal data_ctr : integer range 0 to 30;
+signal state : std_logic_vector(3 downto 0);
+
+
+signal stat_data_temp : std_logic_vector(31 downto 0);
+signal rec_frames : std_logic_vector(15 downto 0);
+
+signal rx_fifo_q : std_logic_vector(17 downto 0);
+signal rx_fifo_wr, rx_fifo_rd : std_logic;
+signal tx_eod, rx_eod : std_logic;
+
+signal tx_fifo_q : std_logic_vector(8 downto 0);
+signal tx_fifo_wr, tx_fifo_rd : std_logic;
+signal gsc_reply_read : std_logic;
+signal gsc_init_dataready : std_logic;
+
+signal tx_data_ctr : std_logic_vector(15 downto 0);
+signal tx_loaded_ctr : std_logic_vector(15 downto 0);
+
+signal packet_num : std_logic_vector(2 downto 0);
+
+signal init_ctr, reply_ctr : std_logic_vector(15 downto 0);
+signal rx_empty, tx_empty : std_logic;
+
+signal rx_full, tx_full : std_logic;
+
+
+begin
+
+receive_fifo : fifo_2048x8x16
+ PORT map(
+ Reset => RESET,
+ RPReset => RESET,
+ WrClock => CLK,
+ RdClock => CLK,
+ Data => PS_DATA_IN,
+ WrEn => rx_fifo_wr,
+ RdEn => rx_fifo_rd,
+ Q => rx_fifo_q,
+ Full => rx_full,
+ Empty => rx_empty
+ );
+
+rx_fifo_wr <= '1' when PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1' else '0';
+rx_fifo_rd <= '1' when (gsc_init_dataready = '1' and dissect_current_state = LOAD_TO_HUB) or
+ (gsc_init_dataready = '1' and dissect_current_state = WAIT_FOR_HUB and GSC_INIT_READ_IN = '1') or
+ (dissect_current_state = READ_FRAME and PS_DATA_IN(8) = '1')
+ else '0'; -- preload first word
+
+GSC_INIT_DATA_OUT(7 downto 0) <= rx_fifo_q(16 downto 9);
+GSC_INIT_DATA_OUT(15 downto 8) <= rx_fifo_q(7 downto 0);
+GSC_INIT_PACKET_NUM_OUT <= packet_num;
+gsc_init_dataready <= '1' when (GSC_INIT_READ_IN = '1' and dissect_current_state = LOAD_TO_HUB) or
+ (dissect_current_state = WAIT_FOR_HUB) else '0';
+GSC_INIT_DATAREADY_OUT <= gsc_init_dataready;
+
+transmit_fifo : fifo_1024x16x8
+ PORT map(
+ Reset => RESET,
+ RPReset => RESET,
+ WrClock => CLK,
+ RdClock => CLK,
+ Data(7 downto 0) => GSC_REPLY_DATA_IN(15 downto 8),
+ Data(8) => '0',
+ Data(16 downto 9) => GSC_REPLY_DATA_IN(7 downto 0),
+ Data(17) => '0',
+ WrEn => tx_fifo_wr,
+ RdEn => tx_fifo_rd,
+ Q => tx_fifo_q,
+ Full => tx_full,
+ Empty => tx_empty
+ );
+
+tx_fifo_wr <= '1' when GSC_REPLY_DATAREADY_IN = '1' and gsc_reply_read = '1' else '0';
+tx_fifo_rd <= '1' when TC_RD_EN_IN = '1' and dissect_current_state = LOAD_FRAME else '0';
+
+TC_DATA_OUT(7 downto 0) <= tx_fifo_q(7 downto 0) when dissect_current_state = LOAD_FRAME else (others => '0');
+TC_DATA_OUT(8) <= '1' when tx_loaded_ctr = tx_data_ctr and dissect_current_state = LOAD_FRAME else '0';
+GSC_REPLY_READ_OUT <= gsc_reply_read;
+gsc_reply_read <= '1' when dissect_current_state = WAIT_FOR_RESPONSE or dissect_current_state = SAVE_RESPONSE else '0';
+
+TX_DATA_CTR_PROC : process(CLK)
+begin
+ if rising_edge(CLK) then
+ if (RESET = '1' or dissect_current_state = IDLE) then
+ tx_data_ctr <= (others => '0');
+ elsif (tx_fifo_wr = '1') then
+ tx_data_ctr(15 downto 1) <= tx_data_ctr(15 downto 1) + x"1";
+ end if;
+ end if;
+end process TX_DATA_CTR_PROC;
+
+TX_LOADED_CTR_PROC : process(CLK)
+begin
+ if rising_edge(CLK) then
+ if (RESET = '1' or dissect_current_state = IDLE) then
+ tx_loaded_ctr <= (others => '0');
+ elsif (dissect_current_state = LOAD_FRAME and TC_RD_EN_IN = '1' and PS_SELECTED_IN = '1') then
+ tx_loaded_ctr <= tx_loaded_ctr + x"1";
+ end if;
+ end if;
+end process TX_LOADED_CTR_PROC;
+
+PS_BUSY_OUT <= '0' when (dissect_current_state = IDLE) else '1';
+
+PS_RESPONSE_READY_OUT <= '1' when (dissect_current_state = WAIT_FOR_LOAD or dissect_current_state = LOAD_FRAME or dissect_current_state = CLEANUP) else '0';
+
+TC_FRAME_SIZE_OUT <= tx_data_ctr;
+
+TC_FRAME_TYPE_OUT <= x"0008";
+TC_DEST_MAC_OUT <= PS_SRC_MAC_ADDRESS_IN;
+TC_DEST_IP_OUT <= PS_SRC_IP_ADDRESS_IN;
+TC_DEST_UDP_OUT <= x"a861";
+TC_SRC_MAC_OUT <= g_MY_MAC;
+TC_SRC_IP_OUT <= g_MY_IP;
+TC_SRC_UDP_OUT <= x"a861";
+TC_IP_PROTOCOL_OUT <= X"11";
+
+
+PACKET_NUM_PROC : process(CLK)
+begin
+ if rising_edge(CLK) then
+ if (RESET = '1') or (dissect_current_state = IDLE) then
+ packet_num <= "100";
+ elsif (GSC_INIT_READ_IN = '1' and gsc_init_dataready = '1' and packet_num = "100") then
+ packet_num <= "000";
+ elsif (rx_fifo_rd = '1' and packet_num /= "100") then
+ packet_num <= packet_num + "1";
+ end if;
+ end if;
+end process PACKET_NUM_PROC;
+
+
+DISSECT_MACHINE_PROC : process(CLK)
+begin
+ if rising_edge(CLK) then
+ if (RESET = '1') then
+ dissect_current_state <= IDLE;
+ else
+ dissect_current_state <= dissect_next_state;
+ end if;
+ end if;
+end process DISSECT_MACHINE_PROC;
+
+DISSECT_MACHINE : process(dissect_current_state, PS_WR_EN_IN, PS_ACTIVATE_IN, PS_DATA_IN, TC_BUSY_IN, data_ctr, PS_SELECTED_IN, GSC_INIT_READ_IN, GSC_REPLY_DATAREADY_IN, tx_loaded_ctr, tx_data_ctr, rx_fifo_q, GSC_BUSY_IN)
+begin
+ case dissect_current_state is
+
+ when IDLE =>
+ state <= x"1";
+ if (PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then
+ dissect_next_state <= READ_FRAME;
+ else
+ dissect_next_state <= IDLE;
+ end if;
+
+ when READ_FRAME =>
+ state <= x"2";
+ if (PS_DATA_IN(8) = '1') then
+ dissect_next_state <= WAIT_FOR_HUB;
+ else
+ dissect_next_state <= READ_FRAME;
+ end if;
+
+ when WAIT_FOR_HUB =>
+ state <= x"3";
+ if (GSC_INIT_READ_IN = '1') then
+ dissect_next_state <= LOAD_TO_HUB;
+ else
+ dissect_next_state <= WAIT_FOR_HUB;
+ end if;
+
+ when LOAD_TO_HUB =>
+ state <= x"4";
+ if (rx_fifo_q(17) = '1') then
+ dissect_next_state <= WAIT_FOR_RESPONSE;
+ else
+ dissect_next_state <= LOAD_TO_HUB;
+ end if;
+
+ when WAIT_FOR_RESPONSE =>
+ state <= x"5";
+ if (GSC_REPLY_DATAREADY_IN = '1') then
+ dissect_next_state <= SAVE_RESPONSE;
+ else
+ dissect_next_state <= WAIT_FOR_RESPONSE;
+ end if;
+
+ when SAVE_RESPONSE =>
+ state <= x"6";
+ if (GSC_REPLY_DATAREADY_IN = '0' and GSC_BUSY_IN = '0') then
+ dissect_next_state <= WAIT_FOR_LOAD;
+ else
+ dissect_next_state <= SAVE_RESPONSE;
+ end if;
+
+ when WAIT_FOR_LOAD =>
+ state <= x"7";
+ if (TC_BUSY_IN = '0' and PS_SELECTED_IN = '1') then
+ dissect_next_state <= LOAD_FRAME;
+ else
+ dissect_next_state <= WAIT_FOR_LOAD;
+ end if;
+
+ when LOAD_FRAME =>
+ state <= x"8";
+ if (tx_loaded_ctr = tx_data_ctr) then
+ dissect_next_state <= CLEANUP;
+ else
+ dissect_next_state <= LOAD_FRAME;
+ end if;
+
+ when CLEANUP =>
+ state <= x"9";
+ dissect_next_state <= IDLE;
+
+ end case;
+end process DISSECT_MACHINE;
+
+
+
+-- statistics
+REC_FRAMES_PROC : process(CLK)
+begin
+ if rising_edge(CLK) then
+ if (RESET = '1') then
+ rec_frames <= (others => '0');
+ elsif (dissect_current_state = IDLE and PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then
+ rec_frames <= rec_frames + x"1";
+ end if;
+ end if;
+end process REC_FRAMES_PROC;
+
+REPLY_CTR_PROC : process(CLK)
+begin
+ if rising_edge(CLK) then
+ if (RESET = '1') then
+ reply_ctr <= (others => '0');
+ elsif (dissect_current_state = LOAD_FRAME and tx_loaded_ctr = tx_data_ctr) then
+ reply_ctr <= reply_ctr + x"1";
+ end if;
+ end if;
+end process REPLY_CTR_PROC;
+
+
+STATS_MACHINE_PROC : process(CLK)
+begin
+ if rising_edge(CLK) then
+ if (RESET = '1') then
+ stats_current_state <= IDLE;
+ else
+ stats_current_state <= stats_next_state;
+ end if;
+ end if;
+end process STATS_MACHINE_PROC;
+
+STATS_MACHINE : process(stats_current_state, PS_WR_EN_IN, PS_ACTIVATE_IN, dissect_current_state, tx_loaded_ctr, tx_data_ctr)
+begin
+
+ case (stats_current_state) is
+
+ when IDLE =>
+ if ((dissect_current_state = IDLE and PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') or (dissect_current_state = LOAD_FRAME and tx_loaded_ctr = tx_data_ctr)) then
+ stats_next_state <= LOAD_RECEIVED;
+ else
+ stats_next_state <= IDLE;
+ end if;
+
+ when LOAD_RECEIVED =>
+ if (STAT_DATA_ACK_IN = '1') then
+ stats_next_state <= LOAD_REPLY;
+ else
+ stats_next_state <= LOAD_RECEIVED;
+ end if;
+
+ when LOAD_REPLY =>
+ if (STAT_DATA_ACK_IN = '1') then
+ stats_next_state <= CLEANUP;
+ else
+ stats_next_state <= LOAD_REPLY;
+ end if;
+
+ when CLEANUP =>
+ stats_next_state <= IDLE;
+
+ end case;
+
+end process STATS_MACHINE;
+
+SELECTOR : process(stats_current_state)
+begin
+
+ case(stats_current_state) is
+
+ when LOAD_RECEIVED =>
+ stat_data_temp <= x"0502" & rec_frames;
+ STAT_ADDR_OUT <= std_logic_vector(to_unsigned(STAT_ADDRESS_BASE, 8));
+
+ when LOAD_REPLY =>
+ stat_data_temp <= x"0503" & reply_ctr;
+ STAT_ADDR_OUT <= std_logic_vector(to_unsigned(STAT_ADDRESS_BASE + 1, 8));
+
+ when others =>
+ stat_data_temp <= (others => '0');
+ STAT_ADDR_OUT <= (others => '0');
+
+ end case;
+
+end process SELECTOR;
+
+STAT_DATA_OUT(7 downto 0) <= stat_data_temp(31 downto 24);
+STAT_DATA_OUT(15 downto 8) <= stat_data_temp(23 downto 16);
+STAT_DATA_OUT(23 downto 16) <= stat_data_temp(15 downto 8);
+STAT_DATA_OUT(31 downto 24) <= stat_data_temp(7 downto 0);
+
+STAT_DATA_RDY_OUT <= '1' when stats_current_state /= IDLE and stats_current_state /= CLEANUP else '0';
+
+-- end of statistics
+
+end architecture RTL;
--- /dev/null
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 17:10:12 11/18/2011
+-- Design Name:
+-- Module Name: trb_net16_gbe_response_constructor_Stat - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE IEEE.std_logic_UNSIGNED.ALL;
+
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+use work.trb_net16_hub_func.all;
+
+use work.trb_net_gbe_components.all;
+use work.trb_net_gbe_protocols.all;
+
+entity trb_net16_gbe_response_constructor_Stat is
+generic ( STAT_ADDRESS_BASE : integer := 0
+);
+port (
+ CLK : in std_logic; -- system clock
+ RESET : in std_logic;
+
+-- INTERFACE
+ PS_DATA_IN : in std_logic_vector(8 downto 0);
+ PS_WR_EN_IN : in std_logic;
+ PS_ACTIVATE_IN : in std_logic;
+ PS_RESPONSE_READY_OUT : out std_logic;
+ PS_BUSY_OUT : out std_logic;
+ PS_SELECTED_IN : in std_logic;
+ PS_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
+ PS_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
+ PS_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
+ PS_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
+ PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0);
+ PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0);
+
+ TC_RD_EN_IN : in std_logic;
+ TC_DATA_OUT : out std_logic_vector(8 downto 0);
+ TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0);
+ TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0);
+ TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0);
+ TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0);
+ TC_DEST_IP_OUT : out std_logic_vector(31 downto 0);
+ TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0);
+ TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0);
+ TC_SRC_IP_OUT : out std_logic_vector(31 downto 0);
+ TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0);
+
+ TC_BUSY_IN : in std_logic;
+
+ STAT_DATA_OUT : out std_logic_vector(31 downto 0);
+ STAT_ADDR_OUT : out std_logic_vector(7 downto 0);
+ STAT_DATA_RDY_OUT : out std_logic;
+ STAT_DATA_ACK_IN : in std_logic;
+
+ RECEIVED_FRAMES_OUT : out std_logic_vector(15 downto 0);
+ SENT_FRAMES_OUT : out std_logic_vector(15 downto 0);
+-- END OF INTERFACE
+
+ STAT_DATA_IN : in std_logic_vector((c_MAX_PROTOCOLS + 1) * 32 - 1 downto 0);
+ STAT_ADDR_IN : in std_logic_vector((c_MAX_PROTOCOLS + 1) * 8 - 1 downto 0);
+ STAT_DATA_RDY_IN : in std_logic_vector((c_MAX_PROTOCOLS + 1) - 1 downto 0);
+ STAT_DATA_ACK_OUT : out std_logic_vector((c_MAX_PROTOCOLS + 1) - 1 downto 0);
+
+-- debug
+ DEBUG_OUT : out std_logic_vector(31 downto 0)
+);
+end trb_net16_gbe_response_constructor_Stat;
+
+architecture Behavioral of trb_net16_gbe_response_constructor_Stat is
+
+attribute syn_encoding : string;
+
+type construct_states is (IDLE, WAIT_FOR_LOAD, LOAD_DATA, TERMINATION, CLEANUP);
+signal construct_current_state, construct_next_state : construct_states;
+attribute syn_encoding of construct_current_state: signal is "safe,gray";
+
+signal timer : unsigned(28 downto 0);
+signal state : std_logic_vector(3 downto 0);
+signal load_ctr : integer range 0 to 255;
+signal tc_data : std_logic_vector(8 downto 0);
+signal tc_data_t : std_logic_vector(7 downto 0);
+signal timer_lock : std_logic;
+
+signal mem_din : std_logic_vector(31 downto 0);
+signal mem_dout, mem_wr_addr : std_logic_vector(7 downto 0);
+signal mem_rd_addr : std_logic_vector(9 downto 0);
+signal mem_wr_en : std_logic;
+signal selected : std_logic_vector(c_MAX_PROTOCOLS downto 0);
+
+signal pause : integer range 0 to 28;
+
+signal stat_data_temp : std_logic_vector(31 downto 0);
+
+begin
+pause <= 10 when g_SIMULATE = 1 else 28;
+
+
+mem : statts_mem
+ PORT map(
+ WrClock => CLK,
+ Reset => RESET,
+ WrClockEn => '1',
+ WE => mem_wr_en,
+ WrAddress => mem_wr_addr,
+ Data => mem_din,
+ RdClock => CLK,
+ RdAddress => mem_rd_addr,
+ Q => mem_dout,
+ RdClockEn => '1'
+ );
+
+mem_wr_en <= or_all(selected);
+STAT_DATA_ACK_OUT <= selected;
+
+SELECTOR_PROC : process(CLK)
+ variable found : boolean := false;
+begin
+ if rising_edge(CLK) then
+
+ selected <= (others => '0');
+
+ if (RESET = '1') then
+ mem_wr_addr <= (others => '0');
+ mem_din <= (others => '0');
+ found := false;
+ else
+ if (or_all(STAT_DATA_RDY_IN) = '1') then
+ for i in 0 to c_MAX_PROTOCOLS loop
+ if (STAT_DATA_RDY_IN(i) = '1') then
+ mem_wr_addr <= STAT_ADDR_IN((i + 1) * 8 - 1 downto i * 8);
+ mem_din <= STAT_DATA_IN((i + 1) * 32 - 1 downto i * 32);
+ selected(i) <= '1';
+ found := true;
+ elsif (i = c_MAX_PROTOCOLS) and (STAT_DATA_RDY_IN(i) = '0') and (found = false) then
+ found := false;
+ end if;
+ end loop;
+ else
+ mem_wr_addr <= (others => '0');
+ mem_din <= (others => '0');
+ found := false;
+ end if;
+ end if;
+
+ end if;
+end process SELECTOR_PROC;
+
+
+
+
+
+TIMER_PROC : process(CLK)
+begin
+ if rising_edge(CLK) then
+ if (RESET = '1') then
+ timer <= (others => '0');
+ timer_lock <= '0';
+ elsif (timer(pause) = '0') then
+ timer_lock <= '0';
+ timer <= timer + 1;
+ elsif (timer(pause) = '1') then
+ timer_lock <= '1';
+ timer <= timer + 1;
+ else
+ timer <= timer + 1;
+ end if;
+ end if;
+end process TIMER_PROC;
+
+-- **** MESSAGES CONSTRUCTING PART
+
+CONSTRUCT_MACHINE_PROC : process(CLK)
+begin
+ if rising_edge(CLK) then
+ if (RESET = '1') then
+ construct_current_state <= IDLE;
+ else
+ construct_current_state <= construct_next_state;
+ end if;
+ end if;
+end process CONSTRUCT_MACHINE_PROC;
+
+CONSTRUCT_MACHINE : process(construct_current_state, timer_lock, TC_BUSY_IN, PS_SELECTED_IN, timer, load_ctr)
+begin
+ case construct_current_state is
+
+ when IDLE =>
+ state <= x"1";
+ if (timer(pause) = '1' and timer_lock = '0') then
+ construct_next_state <= WAIT_FOR_LOAD;
+ else
+ construct_next_state <= IDLE;
+ end if;
+
+ when WAIT_FOR_LOAD =>
+ state <= x"4";
+ if (TC_BUSY_IN = '0' and PS_SELECTED_IN = '1') then
+ construct_next_state <= LOAD_DATA;
+ else
+ construct_next_state <= WAIT_FOR_LOAD;
+ end if;
+
+ when LOAD_DATA =>
+ state <= x"2";
+ if (load_ctr = 255) then
+ construct_next_state <= TERMINATION;
+ else
+ construct_next_state <= LOAD_DATA;
+ end if;
+
+ when TERMINATION =>
+ state <= x"e";
+ construct_next_state <= CLEANUP;
+
+ when CLEANUP =>
+ state <= x"9";
+ construct_next_state <= IDLE;
+
+ end case;
+end process CONSTRUCT_MACHINE;
+
+LOAD_CTR_PROC : process(CLK)
+begin
+ if rising_edge(CLK) then
+ if (RESET = '1') or (construct_current_state = IDLE) then
+ load_ctr <= 1;
+ elsif (TC_RD_EN_IN = '1') and (PS_SELECTED_IN = '1') then
+ load_ctr <= load_ctr + 1;
+ end if;
+ end if;
+end process LOAD_CTR_PROC;
+
+mem_rd_addr <= std_logic_vector(to_unsigned(load_ctr, 10));
+
+TC_DATA_PROC : process(construct_current_state, tc_data_t)
+begin
+
+ tc_data(8) <= '0';
+
+ case (construct_current_state) is
+
+ when LOAD_DATA =>
+ for i in 0 to 7 loop
+ tc_data(i) <= mem_dout(i);
+ end loop;
+
+ when TERMINATION =>
+ tc_data(7 downto 0) <= x"ff";
+ tc_data(8) <= '1';
+
+ when others => tc_data(7 downto 0) <= x"00";
+
+ end case;
+
+end process;
+
+TC_DATA_SYNC : process(CLK)
+begin
+ if rising_edge(CLK) then
+ TC_DATA_OUT <= tc_data;
+ end if;
+end process TC_DATA_SYNC;
+
+
+PS_BUSY_OUT <= '0' when (construct_current_state = IDLE) else '1';
+PS_RESPONSE_READY_OUT <= '0' when (construct_current_state = IDLE) else '1';
+
+TC_FRAME_SIZE_OUT <= x"0100";
+TC_FRAME_TYPE_OUT <= x"0008"; -- frame type: ip
+
+TC_DEST_MAC_OUT <= x"ffffffffffff";
+TC_DEST_IP_OUT <= x"ff00a8c0";
+TC_DEST_UDP_OUT <= x"51c3";
+TC_SRC_MAC_OUT <= g_MY_MAC;
+TC_SRC_IP_OUT <= g_MY_IP;
+TC_SRC_UDP_OUT <= x"51c3";
+TC_IP_PROTOCOL_OUT <= x"11"; -- udp
+
+end Behavioral;
+
DBG_FC2_IN : in std_logic_vector(31 downto 0);
DBG_FT1_IN : in std_logic_vector(31 downto 0);
DBG_FT2_IN : in std_logic_vector(31 downto 0);
- DBG_FR_IN : in std_logic_vector(95 downto 0);
+ DBG_FR_IN : in std_logic_vector(63 downto 0);
DBG_RC_IN : in std_logic_vector(63 downto 0);
DBG_MC_IN : in std_logic_vector(63 downto 0);
DBG_TC_IN : in std_logic_vector(31 downto 0);
max_packet <= x"0000_0fd0"; --x"0000_fde8"; -- 65k --x"0000_fde8"; -- tester
min_packet <= x"0000_0007"; -- gk 20.07.10
max_frame <= x"0578";
- use_gbe <= '1'; --'1'; -- gk 27.08.10 -- blocks the transmission until gbe gets configured
+ use_gbe <= '0'; --'1'; -- gk 27.08.10 -- blocks the transmission until gbe gets configured
use_trbnet <= '0';
use_multievents <= '0';
reset_values <= '0';
attribute syn_sharing : string;\r
attribute syn_sharing of trb_net16_med_ecp_sfp_gbe_8b : architecture is "off";\r
\r
+--component serdes_gbe_0ch is\r
+component serdes_ch4 is\r
+ --GENERIC (USER_CONFIG_FILE : String := "serdes_gbe_0ch.txt");\r
+GENERIC (USER_CONFIG_FILE : String := "serdes_ch4.txt");\r
+ port (\r
+------------------\r
+-- CH0 --\r
+ hdinp_ch3, hdinn_ch3 : in std_logic;\r
+ hdoutp_ch3, hdoutn_ch3 : out std_logic;\r
+ rxiclk_ch3 : in std_logic;\r
+ txiclk_ch3 : in std_logic;\r
+ rx_full_clk_ch3 : out std_logic;\r
+ rx_half_clk_ch3 : out std_logic;\r
+ tx_full_clk_ch3 : out std_logic;\r
+ tx_half_clk_ch3 : out std_logic;\r
+ fpga_rxrefclk_ch3 : in std_logic;\r
+ txdata_ch3 : in std_logic_vector (7 downto 0);\r
+ tx_k_ch3 : in std_logic;\r
+ xmit_ch3 : in std_logic;\r
+ tx_disp_correct_ch3 : in std_logic;\r
+ rxdata_ch3 : out std_logic_vector (7 downto 0);\r
+ rx_k_ch3 : out std_logic;\r
+ rx_disp_err_ch3 : out std_logic;\r
+ rx_cv_err_ch3 : out std_logic;\r
+ rx_serdes_rst_ch3_c : in std_logic;\r
+ sb_felb_ch3_c : in std_logic;\r
+ sb_felb_rst_ch3_c : in std_logic;\r
+ tx_pcs_rst_ch3_c : in std_logic;\r
+ tx_pwrup_ch3_c : in std_logic;\r
+ rx_pcs_rst_ch3_c : in std_logic;\r
+ rx_pwrup_ch3_c : in std_logic;\r
+ rx_los_low_ch3_s : out std_logic;\r
+ lsm_status_ch3_s : out std_logic;\r
+ rx_cdr_lol_ch3_s : out std_logic;\r
+-- CH1 --\r
+-- CH2 --\r
+-- CH3 --\r
+---- Miscillaneous ports\r
+ fpga_txrefclk : in std_logic;\r
+ tx_serdes_rst_c : in std_logic;\r
+ tx_pll_lol_qd_s : out std_logic;\r
+ rst_qd_c : in std_logic;\r
+ serdes_rst_qd_c : in std_logic);\r
+\r
+end component;\r
+\r
component serdes_gbe_0_extclock_8b is\r
GENERIC (USER_CONFIG_FILE : String := "serdes_gbe_0_extclock_8b.txt");\r
port( refclkp : in std_logic;\r
\r
end component;\r
\r
+-- component sgmii_gbe_pcs34\r
+-- port( rst_n : in std_logic;\r
+-- signal_detect : in std_logic;\r
+-- gbe_mode : in std_logic;\r
+-- sgmii_mode : in std_logic;\r
+-- operational_rate : in std_logic_vector(1 downto 0);\r
+-- debug_link_timer_short : in std_logic;\r
+-- rx_compensation_err : out std_logic;\r
+-- tx_clk_125 : in std_logic; \r
+-- tx_clock_enable_source : out std_logic;\r
+-- tx_clock_enable_sink : in std_logic; \r
+-- tx_d : in std_logic_vector(7 downto 0); \r
+-- tx_en : in std_logic; \r
+-- tx_er : in std_logic; \r
+-- rx_clk_125 : in std_logic; \r
+-- rx_clock_enable_source : out std_logic;\r
+-- rx_clock_enable_sink : in std_logic; \r
+-- rx_d : out std_logic_vector(7 downto 0); \r
+-- rx_dv : out std_logic; \r
+-- rx_er : out std_logic; \r
+-- col : out std_logic; \r
+-- crs : out std_logic; \r
+-- tx_data : out std_logic_vector(7 downto 0); \r
+-- tx_kcntl : out std_logic; \r
+-- tx_disparity_cntl : out std_logic; \r
+-- serdes_recovered_clk : in std_logic; \r
+-- rx_data : in std_logic_vector(7 downto 0); \r
+-- rx_even : in std_logic; \r
+-- rx_kcntl : in std_logic; \r
+-- rx_disp_err : in std_logic; \r
+-- rx_cv_err : in std_logic; \r
+-- rx_err_decode_mode : in std_logic; \r
+-- mr_an_complete : out std_logic; \r
+-- mr_page_rx : out std_logic; \r
+-- mr_lp_adv_ability : out std_logic_vector(15 downto 0); \r
+-- mr_main_reset : in std_logic; \r
+-- mr_an_enable : in std_logic; \r
+-- mr_restart_an : in std_logic; \r
+-- mr_adv_ability : in std_logic_vector(15 downto 0) \r
+-- );\r
+-- end component;\r
+\r
component sgmii_gbe_pcs34\r
port( rst_n : in std_logic;\r
signal_detect : in std_logic;\r
sgmii_mode : in std_logic;\r
operational_rate : in std_logic_vector(1 downto 0);\r
debug_link_timer_short : in std_logic;\r
+\r
+ force_isolate : in std_logic;\r
+ force_loopback : in std_logic;\r
+ force_unidir : in std_logic;\r
+\r
rx_compensation_err : out std_logic;\r
+\r
+ ctc_drop_flag : out std_logic;\r
+ ctc_add_flag : out std_logic;\r
+ an_link_ok : out std_logic;\r
+\r
tx_clk_125 : in std_logic; \r
tx_clock_enable_source : out std_logic;\r
tx_clock_enable_sink : in std_logic; \r
tx_data : out std_logic_vector(7 downto 0); \r
tx_kcntl : out std_logic; \r
tx_disparity_cntl : out std_logic; \r
+\r
+ xmit_autoneg : out std_logic;\r
+\r
serdes_recovered_clk : in std_logic; \r
rx_data : in std_logic_vector(7 downto 0); \r
rx_even : in std_logic; \r
);\r
end component;\r
\r
+component reset_controller_pcs port (\r
+ rst_n : in std_logic;\r
+ clk : in std_logic;\r
+ tx_plol : in std_logic; \r
+ rx_cdr_lol : in std_logic; \r
+ quad_rst_out : out std_logic; \r
+ tx_pcs_rst_out : out std_logic; \r
+ rx_pcs_rst_out : out std_logic\r
+ );\r
+end component;\r
+component reset_controller_cdr port (\r
+ rst_n : in std_logic;\r
+ clk : in std_logic;\r
+ cdr_lol : in std_logic; \r
+ cdr_rst_out : out std_logic\r
+ );\r
+end component;\r
+\r
+component rate_resolution port (\r
+ gbe_mode : in std_logic;\r
+ sgmii_mode : in std_logic;\r
+ an_enable : in std_logic; \r
+ advertised_rate : in std_logic_vector(1 downto 0);\r
+ link_partner_rate : in std_logic_vector(1 downto 0);\r
+ non_an_rate : in std_logic_vector(1 downto 0);\r
+ operational_rate : out std_logic_vector(1 downto 0) \r
+ );\r
+end component;\r
+\r
+component register_interface_hb port (\r
+ rst_n : in std_logic;\r
+ hclk : in std_logic;\r
+ gbe_mode : in std_logic;\r
+ sgmii_mode : in std_logic;\r
+ hcs_n : in std_logic;\r
+ hwrite_n : in std_logic;\r
+ haddr : in std_logic_vector(3 downto 0);\r
+ hdatain : in std_logic_vector(7 downto 0);\r
+ hdataout : out std_logic_vector(7 downto 0); \r
+ hready_n : out std_logic;\r
+ mr_an_complete : in std_logic; \r
+ mr_page_rx : in std_logic; \r
+ mr_lp_adv_ability : in std_logic_vector(15 downto 0); \r
+ mr_main_reset : out std_logic; \r
+ mr_an_enable : out std_logic; \r
+ mr_restart_an : out std_logic; \r
+ mr_adv_ability : out std_logic_vector(15 downto 0) \r
+ );\r
+end component;\r
+\r
+component sgmii33 port (\r
+ rst_n : in std_logic;\r
+ signal_detect : in std_logic;\r
+ gbe_mode : in std_logic;\r
+ sgmii_mode : in std_logic;\r
+ --force_isolate : in std_logic;\r
+ --force_loopback : in std_logic;\r
+ --force_unidir : in std_logic;\r
+ operational_rate : in std_logic_vector(1 downto 0);\r
+ debug_link_timer_short : in std_logic;\r
+ rx_compensation_err : out std_logic;\r
+ --ctc_drop_flag : out std_logic;\r
+ --ctc_add_flag : out std_logic;\r
+ --an_link_ok : out std_logic;\r
+ tx_clk_125 : in std_logic; \r
+ tx_clock_enable_source : out std_logic;\r
+ tx_clock_enable_sink : in std_logic; \r
+ tx_d : in std_logic_vector(7 downto 0); \r
+ tx_en : in std_logic; \r
+ tx_er : in std_logic; \r
+ rx_clk_125 : in std_logic; \r
+ rx_clock_enable_source : out std_logic;\r
+ rx_clock_enable_sink : in std_logic; \r
+ rx_d : out std_logic_vector(7 downto 0); \r
+ rx_dv : out std_logic; \r
+ rx_er : out std_logic; \r
+ col : out std_logic; \r
+ crs : out std_logic; \r
+ tx_data : out std_logic_vector(7 downto 0); \r
+ tx_kcntl : out std_logic; \r
+ tx_disparity_cntl : out std_logic; \r
+ --xmit_autoneg : out std_logic; \r
+ serdes_recovered_clk : in std_logic; \r
+ rx_data : in std_logic_vector(7 downto 0); \r
+ rx_even : in std_logic; \r
+ rx_kcntl : in std_logic; \r
+ rx_disp_err : in std_logic; \r
+ rx_cv_err : in std_logic; \r
+ rx_err_decode_mode : in std_logic; \r
+ mr_an_complete : out std_logic; \r
+ mr_page_rx : out std_logic; \r
+ mr_lp_adv_ability : out std_logic_vector(15 downto 0); \r
+ mr_main_reset : in std_logic; \r
+ mr_an_enable : in std_logic; \r
+ mr_restart_an : in std_logic; \r
+ mr_adv_ability : in std_logic_vector(15 downto 0)\r
+ );\r
+end component;\r
+\r
+\r
signal refclkcore : std_logic;\r
\r
signal sd_link_ok : std_logic;\r
signal sd_rx_cv_error : std_logic;\r
signal sd_rx_clk : std_logic;\r
\r
+signal sd_tx_data_q : std_logic_vector(7 downto 0);\r
+signal sd_tx_kcntl_q : std_logic;\r
+signal sd_tx_correct_disp_q : std_logic;\r
+\r
+signal sd_rx_data_q : std_logic_vector(7 downto 0);\r
+signal sd_rx_kcntl_q : std_logic;\r
+signal sd_rx_disp_error_q : std_logic;\r
+signal sd_rx_cv_error_q : std_logic;\r
+\r
signal pcs_mr_an_complete : std_logic;\r
signal pcs_mr_ability : std_logic_vector(15 downto 0);\r
signal pcs_mr_page_rx : std_logic;\r
signal reset_debug : std_logic_vector(31 downto 0);\r
signal test_clk : std_logic;\r
\r
+signal xmit : std_logic;\r
+signal signal_detected, compensation_err, tx_clk_en, rx_clk_en, rst_n, an_complete : std_logic;\r
+signal tx_pll_lol, rx_cdr_lol, los, tx_pcs_rst, rx_pcs_rst, rx_serdes_rst : std_logic;\r
+\r
+signal operational_rate : std_logic_vector(1 downto 0);\r
+\r
+signal mr_an_enable, mr_restart_an, mr_main_reset, mr_page_rx : std_logic;\r
+signal mr_lp_adv_ability, mr_adv_ability : std_logic_vector(15 downto 0);\r
\r
\r
attribute syn_keep : boolean;\r
attribute syn_preserve : boolean;\r
\r
- attribute syn_keep of sd_tx_clk : signal is true;\r
- attribute syn_preserve of sd_tx_clk : signal is true;\r
+ --attribute syn_keep of sd_tx_clk : signal is true;\r
+ --attribute syn_preserve of sd_tx_clk : signal is true;\r
attribute syn_keep of sd_rx_clk : signal is true;\r
attribute syn_preserve of sd_rx_clk : signal is true;\r
+ \r
+ attribute syn_keep of sd_tx_correct_disp_q, sd_tx_kcntl_q, sd_tx_data_q, sd_rx_data_q, sd_rx_cv_error_q, sd_rx_disp_error_q, sd_rx_kcntl_q : signal is true;\r
+ attribute syn_preserve of sd_tx_correct_disp_q, sd_tx_kcntl_q, sd_tx_data_q, sd_rx_data_q, sd_rx_cv_error_q, sd_rx_disp_error_q, sd_rx_kcntl_q : signal is true;\r
\r
begin\r
\r
-- Reset state machine for SerDes\r
-THE_RESET_STATEMACHINE: trb_net16_lsm_sfp_gbe\r
-port map(\r
- SYSCLK => CLK_125_IN,\r
- RESET => '0', -- really?\r
- CLEAR => RESET, -- from 100MHz PLL, includes async part\r
- -- status signals\r
- SFP_MISSING_IN => SD_PRSNT_N_IN,\r
- SFP_LOS_IN => SD_LOS_IN,\r
- SD_LINK_OK_IN => '1', -- not used\r
- SD_LOS_IN => '0', -- not used\r
- SD_TXCLK_BAD_IN => sd_link_error(2), -- plol\r
- SD_RXCLK_BAD_IN => sd_link_error(1), -- rlol\r
- -- control signals\r
- FULL_RESET_OUT => quad_rst,\r
- LANE_RESET_OUT => lane_rst,\r
- USER_RESET_OUT => user_rst,\r
- -- debug signals\r
- TIMING_CTR_OUT => open,\r
- BSM_OUT => reset_bsm,\r
- DEBUG_OUT => reset_debug\r
-);\r
+-- THE_RESET_STATEMACHINE: trb_net16_lsm_sfp_gbe\r
+-- port map(\r
+-- SYSCLK => CLK_125_IN,\r
+-- RESET => '0', -- really?\r
+-- CLEAR => RESET, -- from 100MHz PLL, includes async part\r
+-- -- status signals\r
+-- SFP_MISSING_IN => SD_PRSNT_N_IN,\r
+-- SFP_LOS_IN => SD_LOS_IN,\r
+-- SD_LINK_OK_IN => '1', -- not used\r
+-- SD_LOS_IN => '0', -- not used\r
+-- SD_TXCLK_BAD_IN => sd_link_error(2), -- plol\r
+-- SD_RXCLK_BAD_IN => sd_link_error(1), -- rlol\r
+-- -- control signals\r
+-- FULL_RESET_OUT => quad_rst,\r
+-- LANE_RESET_OUT => lane_rst,\r
+-- USER_RESET_OUT => user_rst,\r
+-- -- debug signals\r
+-- TIMING_CTR_OUT => open,\r
+-- BSM_OUT => reset_bsm,\r
+-- DEBUG_OUT => reset_debug\r
+-- );\r
\r
-- gk 28.04.10\r
-- SerDes for GbE\r
clk_int : if (USE_125MHZ_EXTCLK = 0) generate\r
\r
- refclkcore <= sd_tx_clk; --CLK_125_IN;\r
+ refclkcore <= CLK_125_IN; --sd_tx_clk; --CLK_125_IN;\r
\r
-- SERDES_GBE : serdes_gbe_0_intclock_8b\r
-- port map(\r
-- ffs_plol => sd_link_error(2)\r
-- );\r
\r
- SERDES_GBE : serdes_gbe_0_intclock_8b_ecp3\r
+ --SERDES_GBE : serdes_gbe_0ch\r
+ SERDES_GBE : serdes_ch4\r
port map(\r
------------------\r
-- CH0 --\r
- hdinp_ch0 => SD_RXD_P_IN,\r
- hdinn_ch0 => SD_RXD_N_IN,\r
- hdoutp_ch0 => SD_TXD_P_OUT,\r
- hdoutn_ch0 => SD_TXD_N_OUT,\r
- rxiclk_ch0 => sd_rx_clk,\r
- txiclk_ch0 => sd_tx_clk,\r
- rx_full_clk_ch0 => sd_rx_clk,\r
- rx_half_clk_ch0 => open,\r
- tx_full_clk_ch0 => sd_tx_clk,\r
- tx_half_clk_ch0 => open,\r
- fpga_rxrefclk_ch0 => CLK_125_IN,\r
- txdata_ch0 => sd_tx_data,\r
- tx_k_ch0 => sd_tx_kcntl,\r
- xmit_ch0 => '0',\r
- tx_disp_correct_ch0 => sd_tx_correct_disp,\r
- rxdata_ch0 => sd_rx_data, \r
- rx_k_ch0 => sd_rx_kcntl,\r
- rx_disp_err_ch0 => sd_rx_disp_error,\r
- rx_cv_err_ch0 => sd_rx_cv_error,\r
- --rx_serdes_rst_ch0_c => lane_rst,\r
- sb_felb_ch0_c => '0',\r
- sb_felb_rst_ch0_c => '0',\r
--- tx_pcs_rst_ch0_c => lane_rst,\r
- tx_pwrup_ch0_c => '1',\r
- --rx_pcs_rst_ch0_c => lane_rst,\r
- rx_pwrup_ch0_c => '1',\r
- rx_los_low_ch0_s => sd_link_error(0),\r
- lsm_status_ch0_s => sd_link_ok,\r
- rx_cdr_lol_ch0_s => sd_link_error(1),\r
+ hdinp_ch3 => SD_RXD_P_IN,\r
+ hdinn_ch3 => SD_RXD_N_IN,\r
+ hdoutp_ch3 => SD_TXD_P_OUT,\r
+ hdoutn_ch3 => SD_TXD_N_OUT,\r
+ rxiclk_ch3 => sd_rx_clk,\r
+ txiclk_ch3 => CLK_125_IN, --sd_tx_clk,\r
+ rx_full_clk_ch3 => sd_rx_clk,\r
+ rx_half_clk_ch3 => open,\r
+ tx_full_clk_ch3 => open, --sd_tx_clk,\r
+ tx_half_clk_ch3 => open,\r
+ fpga_rxrefclk_ch3 => CLK_125_IN,\r
+ txdata_ch3 => sd_tx_data_q,\r
+ tx_k_ch3 => sd_tx_kcntl_q,\r
+ xmit_ch3 => xmit, --'0',\r
+ tx_disp_correct_ch3 => sd_tx_correct_disp_q,\r
+ rxdata_ch3 => sd_rx_data, \r
+ rx_k_ch3 => sd_rx_kcntl,\r
+ rx_disp_err_ch3 => sd_rx_disp_error,\r
+ rx_cv_err_ch3 => sd_rx_cv_error,\r
+ rx_serdes_rst_ch3_c => rx_serdes_rst,\r
+ sb_felb_ch3_c => '0',\r
+ sb_felb_rst_ch3_c => '0',\r
+ tx_pcs_rst_ch3_c => tx_pcs_rst,\r
+ tx_pwrup_ch3_c => '1',\r
+ rx_pcs_rst_ch3_c => rx_pcs_rst,\r
+ rx_pwrup_ch3_c => '1',\r
+ rx_los_low_ch3_s => los,\r
+ lsm_status_ch3_s => signal_detected,\r
+ rx_cdr_lol_ch3_s => rx_cdr_lol,\r
-- CH1 --\r
-- CH2 --\r
-- CH3 --\r
---- Miscillaneous ports\r
fpga_txrefclk => CLK_125_IN,\r
- tx_serdes_rst_c => RESET,\r
- tx_pll_lol_qd_s => sd_link_error(2),\r
- refclk2fpga => open,\r
- rst_n => '1',\r
- serdes_rst_qd_c => quad_rst\r
+ tx_serdes_rst_c => '0',\r
+ tx_pll_lol_qd_s => tx_pll_lol,\r
+ rst_qd_c => quad_rst,\r
+ serdes_rst_qd_c => '0'\r
);\r
\r
\r
end generate clk_int;\r
\r
clk_ext : if (USE_125MHZ_EXTCLK = 1) generate\r
- SERDES_GBE : serdes_gbe_0_extclock_8b \r
+ --SERDES_GBE : serdes_gbe_0_extclock_8b\r
+ SERDES_GBE : serdes_gbe_0_extclock_8b \r
port map( -- SerDes connection to outside world\r
refclkp => SD_REFCLK_P_IN, -- SerDes REFCLK diff. input\r
refclkn => SD_REFCLK_N_IN,\r
);\r
end generate clk_ext;\r
\r
-SD_RX_DATA_PROC: process( sd_rx_clk )\r
-begin\r
- if( rising_edge(sd_rx_clk) ) then\r
- sd_rx_debug(15 downto 12) <= (others => '0');\r
- sd_rx_debug(11) <= sd_rx_disp_error;\r
- sd_rx_debug(10) <= sd_rx_even;\r
- sd_rx_debug(9) <= sd_rx_cv_error;\r
- sd_rx_debug(8) <= sd_rx_kcntl;\r
- sd_rx_debug(7 downto 0) <= sd_rx_data;\r
- end if;\r
-end process SD_RX_DATA_PROC;\r
-\r
-SD_TX_DATA_PROC: process( sd_tx_clk )\r
-begin\r
- if( rising_edge(sd_tx_clk) ) then\r
- sd_tx_debug(15 downto 10) <= (others => '0');\r
- sd_tx_debug(9) <= sd_tx_correct_disp;\r
- sd_tx_debug(8) <= sd_tx_kcntl;\r
- sd_tx_debug(7 downto 0) <= sd_tx_data;\r
- end if;\r
-end process SD_TX_DATA_PROC;\r
+--SD_RX_DATA_PROC: process( sd_rx_clk )\r
+--begin\r
+-- if( rising_edge(sd_rx_clk) ) then\r
+-- sd_rx_debug(15 downto 12) <= (others => '0');\r
+-- sd_rx_debug(11) <= sd_rx_disp_error;\r
+-- sd_rx_debug(10) <= sd_rx_even;\r
+-- sd_rx_debug(9) <= sd_rx_cv_error;\r
+-- sd_rx_debug(8) <= sd_rx_kcntl;\r
+-- sd_rx_debug(7 downto 0) <= sd_rx_data;\r
+-- end if;\r
+--end process SD_RX_DATA_PROC;\r
+--\r
+--SD_TX_DATA_PROC: process( CLK_125_IN) --sd_tx_clk )\r
+--begin\r
+-- if( rising_edge(CLK_125_IN)) then --sd_tx_clk) ) then\r
+-- sd_tx_debug(15 downto 10) <= (others => '0');\r
+-- sd_tx_debug(9) <= sd_tx_correct_disp;\r
+-- sd_tx_debug(8) <= sd_tx_kcntl;\r
+-- sd_tx_debug(7 downto 0) <= sd_tx_data;\r
+-- end if;\r
+--end process SD_TX_DATA_PROC;\r
\r
buf_stat_debug(63 downto 40) <= (others => '0');\r
buf_stat_debug(39 downto 36) <= reset_debug(3 downto 0);\r
buf_stat_debug(11 downto 0) <= sd_rx_debug(11 downto 0);\r
\r
\r
-SGMII_GBE_PCS : sgmii_gbe_pcs34\r
-port map(\r
- rst_n => GSR_N,\r
- signal_detect => sd_link_ok,\r
- gbe_mode => '1',\r
- sgmii_mode => MR_MODE_IN,\r
- operational_rate => "10",\r
- debug_link_timer_short => '0',\r
- rx_compensation_err => pcs_rx_comp_err,\r
- -- MAC interface\r
- tx_clk_125 => refclkcore, -- original clock from SerDes\r
- tx_clock_enable_source => pcs_tx_clk_en,\r
- tx_clock_enable_sink => pcs_tx_clk_en,\r
- tx_d => FT_TXD_IN, -- TX data from MAC\r
- tx_en => FT_TX_EN_IN, -- TX data enable from MAC\r
- tx_er => FT_TX_ER_IN, -- TX error from MAC\r
- rx_clk_125 => refclkcore, -- original clock from SerDes\r
- rx_clock_enable_source => pcs_rx_clk_en,\r
- rx_clock_enable_sink => pcs_rx_clk_en,\r
- rx_d => pcs_rx_d, -- RX data to MAC\r
- rx_dv => pcs_rx_dv, -- RX data enable to MAC\r
- rx_er => pcs_rx_er, -- RX error to MAC\r
- col => FT_COL_OUT,\r
- crs => FT_CRS_OUT,\r
- -- SerDes interface\r
- tx_data => sd_tx_data, -- TX data to SerDes\r
- tx_kcntl => sd_tx_kcntl, -- TX komma control to SerDes\r
- tx_disparity_cntl => sd_tx_correct_disp, -- idle parity state control in IPG (to SerDes)\r
- serdes_recovered_clk => sd_rx_clk, -- 125MHz recovered from receive bit stream\r
- rx_data => sd_rx_data, -- RX data from SerDes\r
- rx_kcntl => sd_rx_kcntl, -- RX komma control from SerDes\r
- rx_err_decode_mode => '0', -- receive error control mode fixed to normal\r
- rx_even => '0', -- unused (receive error control mode = normal, tie to GND)\r
- rx_disp_err => sd_rx_disp_error, -- RX disparity error from SerDes\r
- rx_cv_err => sd_rx_cv_error, -- RX code violation error from SerDes\r
- -- Autonegotiation stuff\r
- mr_an_complete => pcs_mr_an_complete,\r
- mr_page_rx => pcs_mr_page_rx,\r
- mr_lp_adv_ability => pcs_mr_ability,\r
- mr_main_reset => pcs_mr_reset,\r
- mr_an_enable => MR_AN_ENABLE_IN,\r
- mr_restart_an => MR_RESTART_AN_IN,\r
- mr_adv_ability => MR_ADV_ABILITY_IN\r
-);\r
-\r
-SYNC_RX_PROC : process(sd_rx_clk)\r
-begin\r
- if rising_edge(sd_rx_clk) then\r
+--SGMII_GBE_PCS : sgmii33 port map (\r
+-- rst_n => GSR_N,\r
+-- signal_detect => signal_detected,\r
+-- gbe_mode => '1',\r
+-- sgmii_mode => '0',\r
+-- operational_rate => operational_rate,\r
+-- debug_link_timer_short => '0',\r
+-- rx_compensation_err => compensation_err,\r
+-- tx_clk_125 => CLK_125_IN,\r
+-- tx_clock_enable_source => tx_clk_en,\r
+-- tx_clock_enable_sink => tx_clk_en,\r
+-- tx_d => FT_TXD_IN, --pcs_rxd, --pcs_txd,\r
+-- tx_en => FT_TX_EN_IN, --pcs_rx_dv, --pcs_tx_en, \r
+-- tx_er => FT_TX_ER_IN, --pcs_rx_er, --pcs_tx_er, \r
+-- rx_clk_125 => CLK_125_IN,\r
+-- rx_clock_enable_source => rx_clk_en,\r
+-- rx_clock_enable_sink => rx_clk_en, \r
+-- rx_d => pcs_rx_d,\r
+-- rx_dv => pcs_rx_dv,\r
+-- rx_er => pcs_rx_er, \r
+-- col => FT_COL_OUT,\r
+-- crs => FT_CRS_OUT,\r
+-- tx_data => sd_tx_data,\r
+-- tx_kcntl => sd_tx_kcntl,\r
+-- tx_disparity_cntl => sd_tx_correct_disp,\r
+-- serdes_recovered_clk => sd_rx_clk,\r
+-- rx_data => sd_rx_data_q,\r
+-- rx_even => '0',\r
+-- rx_kcntl => sd_rx_kcntl_q,\r
+-- rx_disp_err => sd_rx_disp_error_q,\r
+-- rx_cv_err => sd_rx_cv_error_q,\r
+-- rx_err_decode_mode => '0',\r
+-- mr_an_complete => an_complete,\r
+-- mr_page_rx => mr_page_rx,\r
+-- mr_lp_adv_ability => mr_lp_adv_ability,\r
+-- mr_main_reset => mr_main_reset, --reset_i,\r
+-- mr_an_enable => '1', --'1',\r
+-- mr_restart_an => mr_restart_an,\r
+-- mr_adv_ability => mr_adv_ability --x"0020"\r
+-- );\r
+ \r
+ SYNC_TX_PROC : process(CLK_125_IN)\r
+ begin\r
+ if rising_edge(CLK_125_IN) then\r
+ sd_tx_data_q <= sd_tx_data;\r
+ sd_tx_kcntl_q <= sd_tx_kcntl;\r
+ sd_tx_correct_disp_q <= sd_tx_correct_disp;\r
+ end if;\r
+ end process SYNC_TX_PROC;\r
+ \r
+ SYNC_RX_PROC : process(sd_rx_clk)\r
+ begin\r
+ if rising_edge(sd_rx_clk) then\r
+ sd_rx_data_q <= sd_rx_data;\r
+ sd_rx_kcntl_q <= sd_rx_kcntl;\r
+ sd_rx_disp_error_q <= sd_rx_disp_error;\r
+ sd_rx_cv_error_q <= sd_rx_cv_error;\r
+ end if;\r
+ end process SYNC_RX_PROC;\r
+ \r
+ \r
+\r
+ \r
+ SGMII_GBE_PCS : sgmii_gbe_pcs34\r
+ port map(\r
+ rst_n => GSR_N,\r
+ signal_detect => signal_detected,\r
+ gbe_mode => '1',\r
+ sgmii_mode => '0',\r
+ operational_rate => operational_rate,\r
+ debug_link_timer_short => '0',\r
+ \r
+ force_isolate => '0',\r
+ force_loopback => '0',\r
+ force_unidir => '0',\r
+ \r
+ rx_compensation_err => compensation_err,\r
+ \r
+ ctc_drop_flag => open,\r
+ ctc_add_flag => open,\r
+ an_link_ok => open,\r
+ \r
+ -- MAC interface\r
+ tx_clk_125 => CLK_125_IN, --refclkcore, -- original clock from SerDes\r
+ tx_clock_enable_source => tx_clk_en,\r
+ tx_clock_enable_sink => tx_clk_en,\r
+ tx_d => FT_TXD_IN, -- TX data from MAC\r
+ tx_en => FT_TX_EN_IN, -- TX data enable from MAC\r
+ tx_er => FT_TX_ER_IN, -- TX error from MAC\r
+ rx_clk_125 => CLK_125_IN, --refclkcore, -- original clock from SerDes\r
+ rx_clock_enable_source => rx_clk_en,\r
+ rx_clock_enable_sink => rx_clk_en,\r
+ rx_d => pcs_rx_d, -- RX data to MAC\r
+ rx_dv => pcs_rx_dv, -- RX data enable to MAC\r
+ rx_er => pcs_rx_er, -- RX error to MAC\r
+ col => FT_COL_OUT,\r
+ crs => FT_CRS_OUT,\r
+ -- SerDes interface\r
+ tx_data => sd_tx_data, -- TX data to SerDes\r
+ tx_kcntl => sd_tx_kcntl, -- TX komma control to SerDes\r
+ tx_disparity_cntl => sd_tx_correct_disp, -- idle parity state control in IPG (to SerDes)\r
+ \r
+ xmit_autoneg => xmit,\r
+ \r
+ serdes_recovered_clk => sd_rx_clk, -- 125MHz recovered from receive bit stream\r
+ rx_data => sd_rx_data_q, -- RX data from SerDes\r
+ rx_kcntl => sd_rx_kcntl_q, -- RX komma control from SerDes\r
+ rx_err_decode_mode => '0', -- receive error control mode fixed to normal\r
+ rx_even => '0', -- unused (receive error control mode = normal, tie to GND)\r
+ rx_disp_err => sd_rx_disp_error_q, -- RX disparity error from SerDes\r
+ rx_cv_err => sd_rx_cv_error_q, -- RX code violation error from SerDes\r
+ -- Autonegotiation stuff\r
+ mr_an_complete => an_complete,\r
+ mr_page_rx => mr_page_rx,\r
+ mr_lp_adv_ability => mr_lp_adv_ability,\r
+ mr_main_reset => mr_main_reset,\r
+ mr_an_enable => '1',\r
+ mr_restart_an => mr_restart_an,\r
+ mr_adv_ability => mr_adv_ability\r
+ );\r
+\r
+rst_n <= not RESET;\r
+\r
+--SYNC_RX_PROC : process(sd_rx_clk)\r
+--begin\r
+-- if rising_edge(sd_rx_clk) then\r
FT_RXD_OUT <= pcs_rx_d;\r
FT_RX_EN_OUT <= pcs_rx_dv;\r
FT_RX_ER_OUT <= pcs_rx_er;\r
- end if;\r
-end process SYNC_RX_PROC;\r
+-- end if;\r
+--end process SYNC_RX_PROC;\r
+\r
+u0_reset_controller_pcs : reset_controller_pcs port map(\r
+ rst_n => rst_n,\r
+ clk => CLK_125_IN,\r
+ tx_plol => tx_pll_lol,\r
+ rx_cdr_lol => rx_cdr_lol,\r
+ quad_rst_out => quad_rst,\r
+ tx_pcs_rst_out => tx_pcs_rst,\r
+ rx_pcs_rst_out => rx_pcs_rst\r
+);\r
+\r
+u0_reset_controller_cdr : reset_controller_cdr port map(\r
+ rst_n => rst_n,\r
+ clk => CLK_125_IN,\r
+ cdr_lol => rx_cdr_lol,\r
+ cdr_rst_out => rx_serdes_rst\r
+);\r
+\r
+u0_rate_resolution : rate_resolution port map(\r
+ gbe_mode => '1',\r
+ sgmii_mode => '0',\r
+ an_enable => '1',\r
+ advertised_rate => mr_adv_ability(11 downto 10),\r
+ link_partner_rate => mr_lp_adv_ability(11 downto 10),\r
+ non_an_rate => "10", -- 1Gbps is rate when auto-negotiation disabled\r
+ \r
+ operational_rate => operational_rate\r
+);\r
+\r
+u0_ri : register_interface_hb port map(\r
+ -- Control Signals\r
+ rst_n => rst_n,\r
+ hclk => CLK_125_IN,\r
+ gbe_mode => '1',\r
+ sgmii_mode => '0',\r
+ \r
+ -- Host Bus\r
+ hcs_n => '1',\r
+ hwrite_n => '1',\r
+ haddr => (others => '0'),\r
+ hdatain => (others => '0'),\r
+ \r
+ hdataout => open,\r
+ hready_n => open,\r
+\r
+ -- Register Outputs\r
+ mr_an_enable => mr_an_enable,\r
+ mr_restart_an => mr_restart_an,\r
+ mr_main_reset => mr_main_reset,\r
+ mr_adv_ability => mr_adv_ability,\r
+\r
+ -- Register Inputs\r
+ mr_an_complete => an_complete,\r
+ mr_page_rx => mr_page_rx,\r
+ mr_lp_adv_ability => mr_lp_adv_ability\r
+ );\r
+\r
+\r
\r
pcs_mr_reset <= MR_RESET_IN or RESET or user_rst;\r
\r
-FT_TX_CLK_EN_OUT <= pcs_tx_clk_en; -- to MAC\r
-FT_RX_CLK_EN_OUT <= pcs_rx_clk_en; -- to MAC\r
+FT_TX_CLK_EN_OUT <= tx_clk_en; -- to MAC\r
+FT_RX_CLK_EN_OUT <= rx_clk_en; -- to MAC\r
\r
MR_AN_LP_ABILITY_OUT <= pcs_mr_ability;\r
-MR_AN_COMPLETE_OUT <= pcs_mr_an_complete;\r
+MR_AN_COMPLETE_OUT <= an_complete;\r
MR_AN_PAGE_RX_OUT <= pcs_mr_page_rx;\r
\r
-- Clock games\r
-CLK_125_OUT <= sd_tx_clk;\r
+CLK_125_OUT <= CLK_125_IN; --sd_tx_clk;\r
CLK_125_RX_OUT <= sd_rx_clk;\r
\r
-- Fakes\r
package trb_net_gbe_components is
+
component trb_net16_gbe_buf is
-generic(
+generic(
DO_SIMULATION : integer range 0 to 1 := 1;
USE_125MHZ_EXTCLK : integer range 0 to 1 := 1
);
port(
CLK : in std_logic;
TEST_CLK : in std_logic; -- only for simulation!
- CLK_125_IN : in std_logic; -- gk 28.04.01 used only in internal 125MHz clock mode
+ CLK_125_IN : in std_logic; -- gk 28.04.01 used only in internal 125MHz clock mode
RESET : in std_logic;
GSR_N : in std_logic;
-- Debug
SFP_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
SFP_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
SFP_TXDIS_OUT : out std_logic; -- SFP disable
+
+ -- interface between main_controller and hub logic
+ MC_UNIQUE_ID_IN : in std_logic_vector(63 downto 0);
+ GSC_CLK_IN : in std_logic;
+ GSC_INIT_DATAREADY_OUT : out std_logic;
+ GSC_INIT_DATA_OUT : out std_logic_vector(15 downto 0);
+ GSC_INIT_PACKET_NUM_OUT : out std_logic_vector(2 downto 0);
+ GSC_INIT_READ_IN : in std_logic;
+ GSC_REPLY_DATAREADY_IN : in std_logic;
+ GSC_REPLY_DATA_IN : in std_logic_vector(15 downto 0);
+ GSC_REPLY_PACKET_NUM_IN : in std_logic_vector(2 downto 0);
+ GSC_REPLY_READ_OUT : out std_logic;
+ GSC_BUSY_IN : in std_logic;
-- for simulation of receiving part only
MAC_RX_EOF_IN : in std_logic;
MAC_RXD_IN : in std_logic_vector(7 downto 0);
MAC_RX_EN_IN : in std_logic;
+
-- debug ports
ANALYZER_DEBUG_OUT : out std_logic_vector(63 downto 0)
);
end component;
+
component trb_net16_gbe_protocol_prioritizer is
port (
CLK : in std_logic;
-- misc signals for response constructors
DHCP_START_IN : in std_logic;
DHCP_DONE_OUT : out std_logic;
+
+ GSC_CLK_IN : in std_logic;
+ GSC_INIT_DATAREADY_OUT : out std_logic;
+ GSC_INIT_DATA_OUT : out std_logic_vector(15 downto 0);
+ GSC_INIT_PACKET_NUM_OUT : out std_logic_vector(2 downto 0);
+ GSC_INIT_READ_IN : in std_logic;
+ GSC_REPLY_DATAREADY_IN : in std_logic;
+ GSC_REPLY_DATA_IN : in std_logic_vector(15 downto 0);
+ GSC_REPLY_PACKET_NUM_IN : in std_logic_vector(2 downto 0);
+ GSC_REPLY_READ_OUT : out std_logic;
+ GSC_BUSY_IN : in std_logic;
+
+ -- input for statistics from outside
+ STAT_DATA_IN : in std_logic_vector(31 downto 0);
+ STAT_ADDR_IN : in std_logic_vector(7 downto 0);
+ STAT_DATA_RDY_IN : in std_logic;
+ STAT_DATA_ACK_OUT : out std_logic;
DEBUG_OUT : out std_logic_vector(63 downto 0)
);
PCS_AN_COMPLETE_IN : in std_logic;
-- signals to/from hub
-
+ MC_UNIQUE_ID_IN : in std_logic_vector(63 downto 0);
+
+ GSC_CLK_IN : in std_logic;
+ GSC_INIT_DATAREADY_OUT : out std_logic;
+ GSC_INIT_DATA_OUT : out std_logic_vector(15 downto 0);
+ GSC_INIT_PACKET_NUM_OUT : out std_logic_vector(2 downto 0);
+ GSC_INIT_READ_IN : in std_logic;
+ GSC_REPLY_DATAREADY_IN : in std_logic;
+ GSC_REPLY_DATA_IN : in std_logic_vector(15 downto 0);
+ GSC_REPLY_PACKET_NUM_IN : in std_logic_vector(2 downto 0);
+ GSC_REPLY_READ_OUT : out std_logic;
+ GSC_BUSY_IN : in std_logic;
+
-- signal to/from Host interface of TriSpeed MAC
TSM_HADDR_OUT : out std_logic_vector(7 downto 0);
TSM_HDATA_OUT : out std_logic_vector(7 downto 0);
TSM_HREAD_N_OUT : out std_logic;
TSM_HREADY_N_IN : in std_logic;
TSM_HDATA_EN_N_IN : in std_logic;
+ TSM_RX_STAT_VEC_IN : in std_logic_vector(31 downto 0);
+ TSM_RX_STAT_EN_IN : in std_logic;
SELECT_REC_FRAMES_OUT : out std_logic_vector(c_MAX_PROTOCOLS * 16 - 1 downto 0);
);
end component;
+component fifo_2048x8 is
+port(
+ Data : in std_logic_vector(7 downto 0);
+ WrClock : in std_logic;
+ RdClock : in std_logic;
+ WrEn : in std_logic;
+ RdEn : in std_logic;
+ Reset : in std_logic;
+ RPReset : in std_logic;
+ Q : out std_logic_vector(7 downto 0);
+ Empty : out std_logic;
+ Full : out std_logic
+);
+end component;
+
component fifo_4096x32 is
port(
Data : in std_logic_vector(31 downto 0);
);
end component;
-component serdes_gbe_0_intclock_8b_ecp3 is
- GENERIC (USER_CONFIG_FILE : String := "serdes_gbe_0_intclock_8b_ecp3.txt");
- port (
-------------------
--- CH0 --
- hdinp_ch0, hdinn_ch0 : in std_logic;
- hdoutp_ch0, hdoutn_ch0 : out std_logic;
- rxiclk_ch0 : in std_logic;
- txiclk_ch0 : in std_logic;
- rx_full_clk_ch0 : out std_logic;
- rx_half_clk_ch0 : out std_logic;
- tx_full_clk_ch0 : out std_logic;
- tx_half_clk_ch0 : out std_logic;
- fpga_rxrefclk_ch0 : in std_logic;
- txdata_ch0 : in std_logic_vector (7 downto 0);
- tx_k_ch0 : in std_logic;
- xmit_ch0 : in std_logic;
- tx_disp_correct_ch0 : in std_logic;
- rxdata_ch0 : out std_logic_vector (7 downto 0);
- rx_k_ch0 : out std_logic;
- rx_disp_err_ch0 : out std_logic;
- rx_cv_err_ch0 : out std_logic;
- sb_felb_ch0_c : in std_logic;
- sb_felb_rst_ch0_c : in std_logic;
- tx_pwrup_ch0_c : in std_logic;
- rx_pwrup_ch0_c : in std_logic;
- rx_los_low_ch0_s : out std_logic;
- lsm_status_ch0_s : out std_logic;
- rx_cdr_lol_ch0_s : out std_logic;
--- CH1 --
--- CH2 --
--- CH3 --
----- Miscillaneous ports
- fpga_txrefclk : in std_logic;
- tx_serdes_rst_c : in std_logic;
- tx_pll_lol_qd_s : out std_logic;
- refclk2fpga : out std_logic;
- rst_n : in std_logic;
- serdes_rst_qd_c : in std_logic);
+component fifo_1024x16x8 is
+port(
+ Data : in std_logic_vector(17 downto 0);
+ WrClock : in std_logic;
+ RdClock : in std_logic;
+ WrEn : in std_logic;
+ RdEn : in std_logic;
+ Reset : in std_logic;
+ RPReset : in std_logic;
+ Q : out std_logic_vector(8 downto 0);
+ Empty : out std_logic;
+ Full : out std_logic
+);
+end component;
+
+component fifo_2048x8x16 is
+port(
+ Data : in std_logic_vector(8 downto 0);
+ WrClock : in std_logic;
+ RdClock : in std_logic;
+ WrEn : in std_logic;
+ RdEn : in std_logic;
+ Reset : in std_logic;
+ RPReset : in std_logic;
+ Q : out std_logic_vector(17 downto 0);
+ Empty : out std_logic;
+ Full : out std_logic
+);
+end component;
+component statts_mem is
+ port (
+ WrAddress: in std_logic_vector(7 downto 0);
+ RdAddress: in std_logic_vector(9 downto 0);
+ Data: in std_logic_vector(31 downto 0);
+ WE: in std_logic;
+ RdClock: in std_logic;
+ RdClockEn: in std_logic;
+ Reset: in std_logic;
+ WrClock: in std_logic;
+ WrClockEn: in std_logic;
+ Q: out std_logic_vector(7 downto 0));
end component;
end package;
\ No newline at end of file
package trb_net_gbe_protocols is
+signal g_SIMULATE : integer range 0 to 1 := 0;
+
-- g_MY_IP is being set by DHCP Response Constructor
signal g_MY_IP : std_logic_vector(31 downto 0);
-- g_MY_MAC is being set by Main Controller
signal g_MY_MAC : std_logic_vector(47 downto 0);
-constant c_MAX_FRAME_TYPES : integer range 1 to 16 := 3;
+constant c_MAX_FRAME_TYPES : integer range 1 to 16 := 2;
constant c_MAX_PROTOCOLS : integer range 1 to 16 := 5;
-constant c_MAX_IP_PROTOCOLS : integer range 1 to 16 := 4;
-constant c_MAX_UDP_PROTOCOLS : integer range 1 to 16 := 2;
+constant c_MAX_IP_PROTOCOLS : integer range 1 to 16 := 2;
+constant c_MAX_UDP_PROTOCOLS : integer range 1 to 16 := 3;
type frame_types_a is array(c_MAX_FRAME_TYPES - 1 downto 0) of std_logic_vector(15 downto 0);
-constant FRAME_TYPES : frame_types_a := (x"0800", x"0806", x"08AA");
--- IPv4, ARP, Test
+constant FRAME_TYPES : frame_types_a := (x"0800", x"0806");
+-- IPv4, ARP
type ip_protos_a is array(c_MAX_IP_PROTOCOLS - 1 downto 0) of std_logic_vector(7 downto 0);
-constant IP_PROTOCOLS : ip_protos_a := (x"11", x"01", x"dd", x"ee");
--- UDP, ICMP, test1, test2
+constant IP_PROTOCOLS : ip_protos_a := (x"11", x"01");
+-- UDP, ICMP
-- this are the destination ports of the incoming packet
type udp_protos_a is array(c_MAX_UDP_PROTOCOLS - 1 downto 0) of std_logic_vector(15 downto 0);
-constant UDP_PROTOCOLS : udp_protos_a := (x"0044", x"7120");
--- DHCP client, dummy
+constant UDP_PROTOCOLS : udp_protos_a := (x"0044", x"61a8", x"7530");
+-- DHCP client, SCTRL, STATs
component trb_net16_gbe_response_constructor_Forward is
port (
end component;
component trb_net16_gbe_response_constructor_ARP is
+generic ( STAT_ADDRESS_BASE : integer := 0
+);
port (
CLK : in std_logic; -- system clock
RESET : in std_logic;
TC_SRC_IP_OUT : out std_logic_vector(31 downto 0);
TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0);
TC_BUSY_IN : in std_logic;
+
+ STAT_DATA_OUT : out std_logic_vector(31 downto 0);
+ STAT_ADDR_OUT : out std_logic_vector(7 downto 0);
+ STAT_DATA_RDY_OUT : out std_logic;
+ STAT_DATA_ACK_IN : in std_logic;
RECEIVED_FRAMES_OUT : out std_logic_vector(15 downto 0);
SENT_FRAMES_OUT : out std_logic_vector(15 downto 0);
end component;
component trb_net16_gbe_response_constructor_DHCP is
+generic ( STAT_ADDRESS_BASE : integer := 0
+);
port (
CLK : in std_logic; -- system clock
RESET : in std_logic;
TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0);
TC_BUSY_IN : in std_logic;
+ STAT_DATA_OUT : out std_logic_vector(31 downto 0);
+ STAT_ADDR_OUT : out std_logic_vector(7 downto 0);
+ STAT_DATA_RDY_OUT : out std_logic;
+ STAT_DATA_ACK_IN : in std_logic;
+
RECEIVED_FRAMES_OUT : out std_logic_vector(15 downto 0);
SENT_FRAMES_OUT : out std_logic_vector(15 downto 0);
-- END OF INTERFACE
end component;
component trb_net16_gbe_response_constructor_Ping is
+generic ( STAT_ADDRESS_BASE : integer := 0
+);
port (
CLK : in std_logic; -- system clock
RESET : in std_logic;
TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0);
TC_BUSY_IN : in std_logic;
+
+ STAT_DATA_OUT : out std_logic_vector(31 downto 0);
+ STAT_ADDR_OUT : out std_logic_vector(7 downto 0);
+ STAT_DATA_RDY_OUT : out std_logic;
+ STAT_DATA_ACK_IN : in std_logic;
RECEIVED_FRAMES_OUT : out std_logic_vector(15 downto 0);
SENT_FRAMES_OUT : out std_logic_vector(15 downto 0);
);
end component;
+component trb_net16_gbe_response_constructor_SCTRL is
+generic ( STAT_ADDRESS_BASE : integer := 0
+);
+ port (
+ CLK : in std_logic; -- system clock
+ RESET : in std_logic;
+
+ -- INTERFACE
+ PS_DATA_IN : in std_logic_vector(8 downto 0);
+ PS_WR_EN_IN : in std_logic;
+ PS_ACTIVATE_IN : in std_logic;
+ PS_RESPONSE_READY_OUT : out std_logic;
+ PS_BUSY_OUT : out std_logic;
+ PS_SELECTED_IN : in std_logic;
+ PS_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
+ PS_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
+ PS_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
+ PS_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
+ PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0);
+ PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0);
+
+ TC_RD_EN_IN : in std_logic;
+ TC_DATA_OUT : out std_logic_vector(8 downto 0);
+ TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0);
+ TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0);
+ TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0);
+ TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0);
+ TC_DEST_IP_OUT : out std_logic_vector(31 downto 0);
+ TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0);
+ TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0);
+ TC_SRC_IP_OUT : out std_logic_vector(31 downto 0);
+ TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0);
+
+ TC_BUSY_IN : in std_logic;
+
+ STAT_DATA_OUT : out std_logic_vector(31 downto 0);
+ STAT_ADDR_OUT : out std_logic_vector(7 downto 0);
+ STAT_DATA_RDY_OUT : out std_logic;
+ STAT_DATA_ACK_IN : in std_logic;
+
+ RECEIVED_FRAMES_OUT : out std_logic_vector(15 downto 0);
+ SENT_FRAMES_OUT : out std_logic_vector(15 downto 0);
+ -- END OF INTERFACE
+
+ -- protocol specific ports
+ GSC_CLK_IN : in std_logic;
+ GSC_INIT_DATAREADY_OUT : out std_logic;
+ GSC_INIT_DATA_OUT : out std_logic_vector(15 downto 0);
+ GSC_INIT_PACKET_NUM_OUT : out std_logic_vector(2 downto 0);
+ GSC_INIT_READ_IN : in std_logic;
+ GSC_REPLY_DATAREADY_IN : in std_logic;
+ GSC_REPLY_DATA_IN : in std_logic_vector(15 downto 0);
+ GSC_REPLY_PACKET_NUM_IN : in std_logic_vector(2 downto 0);
+ GSC_REPLY_READ_OUT : out std_logic;
+ GSC_BUSY_IN : in std_logic;
+ -- end of protocol specific ports
+
+ -- debug
+ DEBUG_OUT : out std_logic_vector(31 downto 0)
+ );
+end component;
+
+component trb_net16_gbe_response_constructor_Stat is
+generic ( STAT_ADDRESS_BASE : integer := 0
+);
+port (
+ CLK : in std_logic; -- system clock
+ RESET : in std_logic;
+
+-- INTERFACE
+ PS_DATA_IN : in std_logic_vector(8 downto 0);
+ PS_WR_EN_IN : in std_logic;
+ PS_ACTIVATE_IN : in std_logic;
+ PS_RESPONSE_READY_OUT : out std_logic;
+ PS_BUSY_OUT : out std_logic;
+ PS_SELECTED_IN : in std_logic;
+ PS_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
+ PS_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
+ PS_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
+ PS_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
+ PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0);
+ PS_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0);
+
+ TC_RD_EN_IN : in std_logic;
+ TC_DATA_OUT : out std_logic_vector(8 downto 0);
+ TC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0);
+ TC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0);
+ TC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0);
+ TC_DEST_MAC_OUT : out std_logic_vector(47 downto 0);
+ TC_DEST_IP_OUT : out std_logic_vector(31 downto 0);
+ TC_DEST_UDP_OUT : out std_logic_vector(15 downto 0);
+ TC_SRC_MAC_OUT : out std_logic_vector(47 downto 0);
+ TC_SRC_IP_OUT : out std_logic_vector(31 downto 0);
+ TC_SRC_UDP_OUT : out std_logic_vector(15 downto 0);
+
+ TC_BUSY_IN : in std_logic;
+
+ STAT_DATA_OUT : out std_logic_vector(31 downto 0);
+ STAT_ADDR_OUT : out std_logic_vector(7 downto 0);
+ STAT_DATA_RDY_OUT : out std_logic;
+ STAT_DATA_ACK_IN : in std_logic;
+
+ RECEIVED_FRAMES_OUT : out std_logic_vector(15 downto 0);
+ SENT_FRAMES_OUT : out std_logic_vector(15 downto 0);
+-- END OF INTERFACE
+
+ STAT_DATA_IN : in std_logic_vector((c_MAX_PROTOCOLS + 1) * 32 - 1 downto 0);
+ STAT_ADDR_IN : in std_logic_vector((c_MAX_PROTOCOLS + 1) * 8 - 1 downto 0);
+ STAT_DATA_RDY_IN : in std_logic_vector((c_MAX_PROTOCOLS + 1) - 1 downto 0);
+ STAT_DATA_ACK_OUT : out std_logic_vector((c_MAX_PROTOCOLS + 1) - 1 downto 0);
+
+-- debug
+ DEBUG_OUT : out std_logic_vector(31 downto 0)
+);
+end component;
+
end package;
jspc29 / trbnet.git / commitdiff