--- /dev/null
+-- this is a dummy apl, just sending data into an active api
+
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.std_logic_ARITH.ALL;
+USE IEEE.std_logic_UNSIGNED.ALL;
+
+use work.trb_net_std.all;
+
+
+entity trb_net16_dummy_apl is
+ generic (
+ TARGET_ADDRESS : std_logic_vector (15 downto 0) := x"ffff";
+ PREFILL_LENGTH : integer := 0;
+ TRANSFER_LENGTH : integer := 0 -- length of dummy data
+ -- might not work with transfer_length > api_fifo
+ -- because of incorrect handling of fifo_full_in!
+ -- shorttransfer is not working too
+ );
+ port(
+ -- Misc
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ -- APL Transmitter port
+ APL_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word "application to network"
+ APL_PACKET_NUM_OUT: out std_logic_vector (1 downto 0);
+ APL_WRITE_OUT: out std_logic; -- Data word is valid and should be transmitted
+ APL_FIFO_FULL_IN: in std_logic; -- Stop transfer, the fifo is full
+ APL_SHORT_TRANSFER_OUT: out std_logic; --
+ APL_DTYPE_OUT: out std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr
+ APL_ERROR_PATTERN_OUT: out std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr
+ APL_SEND_OUT: out std_logic; -- Release sending of the data
+ APL_TARGET_ADDRESS_OUT: out std_logic_vector (15 downto 0); -- Address of
+ -- the target (only for active APIs)
+ -- Receiver port
+ APL_DATA_IN: in std_logic_vector (15 downto 0); -- Data word "network to application"
+ APL_PACKET_NUM_IN:in std_logic_vector (1 downto 0);
+ APL_TYP_IN: in std_logic_vector (2 downto 0); -- Which kind of data word: DAT, HDR or TRM
+ APL_DATAREADY_IN: in std_logic; -- Data word is valid and might be read out
+ APL_READ_OUT: out std_logic; -- Read data word
+ -- APL Control port
+ APL_RUN_IN: in std_logic; -- Data transfer is running
+-- APL_MY_ADDRESS_OUT: in std_logic_vector (15 downto 0); -- My own address (temporary solution!!!)
+ APL_SEQNR_IN: in std_logic_vector (7 downto 0)
+ );
+end entity;
+
+architecture trb_net16_dummy_apl_arch of trb_net16_dummy_apl is
+
+ type SENDER_STATE is (IDLE, WRITING, RUNNING, WAITING, MY_ERROR);
+ signal current_state, next_state : SENDER_STATE;
+ signal next_counter, reg_counter : std_logic_vector(15 downto 0);
+ signal buf_APL_DATA_OUT, next_APL_DATA_OUT : std_logic_vector(15 downto 0);
+ signal buf_APL_PACKET_NUM_OUT, next_APL_PACKET_NUM_OUT : std_logic_vector(1 downto 0);
+ signal buf_APL_WRITE_OUT, next_APL_WRITE_OUT : std_logic;
+ signal buf_APL_SEND_OUT, next_APL_SEND_OUT : std_logic;
+ signal next_packet_counter, packet_counter : std_logic_vector(1 downto 0);
+
+begin
+ APL_READ_OUT <= '1'; --just read, do not check
+ APL_DTYPE_OUT <= x"1";
+ APL_ERROR_PATTERN_OUT <= x"12345678";
+ APL_TARGET_ADDRESS_OUT <= TARGET_ADDRESS;
+ --APL_DATA_OUT <= reg_counter;
+
+ CHECK_1:if TRANSFER_LENGTH >0 generate
+ APL_SHORT_TRANSFER_OUT <= '0';
+ end generate;
+ CHECK_2:if TRANSFER_LENGTH =0 generate
+ APL_SHORT_TRANSFER_OUT <= '1';
+ end generate;
+
+
+ SENDER_CTRL: process (current_state, APL_FIFO_FULL_IN, reg_counter, APL_RUN_IN, RESET)
+ begin -- process
+ next_APL_SEND_OUT <= '0';
+ next_state <= MY_ERROR;
+ next_counter <= reg_counter;
+ next_APL_PACKET_NUM_OUT <= packet_counter;
+ next_APL_WRITE_OUT <= '0';
+-------------------------------------------------------------------------
+-- IDLE
+-------------------------------------------------------------------------
+ if current_state = IDLE then
+ if APL_FIFO_FULL_IN = '1' or reg_counter = PREFILL_LENGTH then
+ next_state <= RUNNING;
+ else
+ next_state <= WRITING;
+ end if;
+-------------------------------------------------------------------------
+-- WRITING
+-------------------------------------------------------------------------
+ elsif current_state = WRITING then
+ next_state <= WRITING;
+ if packet_counter = "01" then
+ next_APL_WRITE_OUT <= '1';
+ next_APL_SEND_OUT <= '1';
+ next_APL_DATA_OUT <= (1 => '1', others => '0');
+ next_packet_counter <= "10";
+ elsif packet_counter = "10" then
+ next_APL_WRITE_OUT <= '1';
+ next_APL_SEND_OUT <= '1';
+ next_APL_DATA_OUT <= (0 => '1', others => '0');
+ next_packet_counter <= "11";
+ else
+ next_APL_WRITE_OUT <= '1';
+ next_APL_SEND_OUT <= '1';
+ next_APL_DATA_OUT <= reg_counter;
+ next_state <= IDLE;
+ next_packet_counter <= "01";
+ next_counter <= reg_counter +1;
+ end if;
+-----------------------------------------------------------------------
+-- RUNNING
+-----------------------------------------------------------------------
+ elsif current_state = RUNNING then
+ next_APL_SEND_OUT <= '1';
+ if reg_counter = TRANSFER_LENGTH then
+ next_state <= WAITING;
+ else
+ next_state <= RUNNING;
+ if APL_FIFO_FULL_IN = '0' then
+ next_counter <= reg_counter +1;
+ next_APL_WRITE_OUT <= '1';
+ end if;
+ end if;
+-----------------------------------------------------------------------
+-- WAITING
+-----------------------------------------------------------------------
+ elsif current_state = WAITING then
+ if APL_RUN_IN = '1' or buf_APL_SEND_OUT = '1' then
+ next_state <= WAITING;
+ else
+ next_state <= IDLE;
+ next_counter <= (others => '0');
+ end if;
+ end if; -- end state switch
+ if RESET = '1' then
+ next_APL_WRITE_OUT <= '0';
+ end if;
+ end process;
+
+APL_DATA_OUT(15 downto 0) <= buf_APL_DATA_OUT;
+APL_PACKET_NUM_OUT <= buf_APL_PACKET_NUM_OUT;
+APL_WRITE_OUT <= buf_APL_WRITE_OUT;
+APL_SEND_OUT <= buf_APL_SEND_OUT;
+
+ CLK_REG: process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ current_state <= IDLE;
+ reg_counter <= (others => '0');
+ buf_APL_DATA_OUT <= (others => '0');
+ buf_APL_PACKET_NUM_OUT <= "00";
+ buf_APL_WRITE_OUT <= '0';
+ buf_APL_SEND_OUT <= '0';
+ elsif CLK_EN = '1' then
+ reg_counter <= next_counter;
+ current_state <= next_state;
+ buf_APL_DATA_OUT <= next_APL_DATA_OUT;
+ buf_APL_PACKET_NUM_OUT <= next_APL_PACKET_NUM_OUT;
+ buf_APL_WRITE_OUT <= next_APL_WRITE_OUT;
+ buf_APL_SEND_OUT <= next_APL_SEND_OUT;
+ end if;
+ end if;
+ end process;
+
+end entity;
--- /dev/null
+-- connection between the TRBNET and any application
+-- for a description see HADES wiki
+-- http://hades-wiki.gsi.de/cgi-bin/view/DaqSlowControl/TrbNetAPI
+
+
+--the packet numbers to the api are
+--Bit 48 - 32 : 01
+--Bit 31 - 16 : 10
+--Bit 15 - 00 : 11
+--packet number 00 is added by the api to the medium.
+--the packets must be transmitted in the given order
+--if you prefer an other sequence for your internal logic, consider using the inverted numbers
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+use work.trb_net_std.all;
+
+
+entity trb_net16_active_api is
+
+ generic (
+ --FIFO size is given in 2^(n+1) 64Bit-packets i.e. 2^(n+3) 16bit packets
+ FIFO_TO_INT_DEPTH : integer := 0; -- direction to medium
+ FIFO_TO_APL_DEPTH : integer := 0; -- direction to application
+ FIFO_TERM_BUFFER_DEPTH : integer := 0 -- fifo for auto-answering master path
+ -- if set to 0, no buffer is used
+ );
+
+ port(
+ -- Misc
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+
+ -- APL Transmitter port
+ APL_DATA_IN : in std_logic_vector (15 downto 0); -- Data word "application to network"
+ APL_PACKET_NUM_IN : in std_logic_vector (1 downto 0);
+ APL_WRITE_IN : in std_logic; -- Data word is valid and should be transmitted
+ APL_FIFO_FULL_OUT : out std_logic; -- Stop transfer, the fifo is full
+ APL_SHORT_TRANSFER_IN : in std_logic; --
+ APL_DTYPE_IN : in std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr
+ APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr
+ APL_SEND_IN : in std_logic; -- Release sending of the data
+ APL_TARGET_ADDRESS_IN : in std_logic_vector (15 downto 0); -- Address of
+ -- the target (only for active APIs)
+
+ -- Receiver port
+ APL_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word "network to application"
+ APL_PACKET_NUM_OUT : out std_logic_vector (1 downto 0);
+ APL_TYP_OUT : out std_logic_vector (2 downto 0); -- Which kind of data word: DAT, HDR or TRM
+ APL_DATAREADY_OUT : out std_logic; -- Data word is valid and might be read out
+ APL_READ_IN : in std_logic; -- Read data word
+
+ -- APL Control port
+ APL_RUN_OUT : out std_logic; -- Data transfer is running
+ APL_MY_ADDRESS_IN : in std_logic_vector (15 downto 0); -- My own address (temporary solution!!!)
+ APL_SEQNR_OUT : out std_logic_vector (7 downto 0);
+
+ -- Internal direction port
+ -- the ports with master or slave in their name are to be mapped by the active api
+ -- to the init respectivly the reply path and vice versa in the passive api.
+ -- lets define: the "master" path is the path that I send data on.
+ INT_INIT_DATAREADY_OUT : out std_logic;
+ INT_INIT_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word
+ INT_INIT_PACKET_NUM_OUT : out std_logic_vector (1 downto 0);
+ INT_INIT_READ_IN : in std_logic;
+
+ INT_INIT_DATAREADY_IN : in std_logic;
+ INT_INIT_DATA_IN : in std_logic_vector (15 downto 0); -- Data word
+ INT_INIT_PACKET_NUM_IN : in std_logic_vector (1 downto 0);
+ INT_INIT_READ_OUT : out std_logic;
+
+
+ INT_REPLY_HEADER_IN : in std_logic; -- Concentrator kindly asks to resend the last
+ -- header (only for the reply path)
+ INT_REPLY_DATAREADY_OUT : out std_logic;
+ INT_REPLY_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word
+ INT_REPLY_PACKET_NUM_OUT : out std_logic_vector (1 downto 0);
+ INT_REPLY_READ_IN : in std_logic;
+
+ INT_REPLY_DATAREADY_IN : in std_logic;
+ INT_REPLY_DATA_IN : in std_logic_vector (15 downto 0); -- Data word
+ INT_REPLY_PACKET_NUM_IN : in std_logic_vector (1 downto 0);
+ INT_REPLY_READ_OUT : out std_logic;
+
+ -- Status and control port
+ STAT_FIFO_TO_INT : out std_logic_vector(31 downto 0);
+ STAT_FIFO_TO_APL : out std_logic_vector(31 downto 0)
+ );
+end entity;
+
+architecture trb_net16_active_api_arch of trb_net16_active_api is
+
+ component trb_net16_base_api is
+ generic (
+ API_TYPE : integer := 0; -- type of api: 0 passive, 1 active
+ --FIFO size is given in 2^(n+1) 64Bit-packets i.e. 2^(n+3) 16bit packets
+ FIFO_TO_INT_DEPTH : integer := 0; -- direction to medium
+ FIFO_TO_APL_DEPTH : integer := 0; -- direction to application
+ FIFO_TERM_BUFFER_DEPTH : integer := 0); -- fifo for auto-answering master path
+ -- if set to 0, no buffer is used
+ port(
+ -- Misc
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+
+ -- APL Transmitter port
+ APL_DATA_IN : in std_logic_vector (15 downto 0); -- Data word "application to network"
+ APL_PACKET_NUM_IN : in std_logic_vector (1 downto 0);
+ APL_WRITE_IN : in std_logic; -- Data word is valid and should be transmitted
+ APL_FIFO_FULL_OUT : out std_logic; -- Stop transfer, the fifo is full
+ APL_SHORT_TRANSFER_IN : in std_logic; --
+ APL_DTYPE_IN : in std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr
+ APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr
+ APL_SEND_IN : in std_logic; -- Release sending of the data
+ APL_TARGET_ADDRESS_IN : in std_logic_vector (15 downto 0); -- Address of
+ -- the target (only for active APIs)
+
+ -- Receiver port
+ APL_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word "network to application"
+ APL_PACKET_NUM_OUT : out std_logic_vector (1 downto 0);
+ APL_TYP_OUT : out std_logic_vector (2 downto 0); -- Which kind of data word: DAT, HDR or TRM
+ APL_DATAREADY_OUT : out std_logic; -- Data word is valid and might be read out
+ APL_READ_IN : in std_logic; -- Read data word
+
+ -- APL Control port
+ APL_RUN_OUT : out std_logic; -- Data transfer is running
+ APL_MY_ADDRESS_IN : in std_logic_vector (15 downto 0); -- My own address (temporary solution!!!)
+ APL_SEQNR_OUT : out std_logic_vector (7 downto 0);
+
+ -- Internal direction port
+ -- the ports with master or slave in their name are to be mapped by the active api
+ -- to the init respectivly the reply path and vice versa in the passive api.
+ -- lets define: the "master" path is the path that I send data on.
+ INT_MASTER_DATAREADY_OUT : out std_logic;
+ INT_MASTER_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word
+ INT_MASTER_PACKET_NUM_OUT : out std_logic_vector (1 downto 0);
+ INT_MASTER_READ_IN : in std_logic;
+
+ INT_MASTER_DATAREADY_IN : in std_logic;
+ INT_MASTER_DATA_IN : in std_logic_vector (15 downto 0); -- Data word
+ INT_MASTER_PACKET_NUM_IN : in std_logic_vector (1 downto 0);
+ INT_MASTER_READ_OUT : out std_logic;
+
+
+ INT_SLAVE_HEADER_IN : in std_logic; -- Concentrator kindly asks to resend the last
+ -- header (only for the reply path)
+ INT_SLAVE_DATAREADY_OUT : out std_logic;
+ INT_SLAVE_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word
+ INT_SLAVE_PACKET_NUM_OUT : out std_logic_vector (1 downto 0);
+ INT_SLAVE_READ_IN : in std_logic;
+
+ INT_SLAVE_DATAREADY_IN : in std_logic;
+ INT_SLAVE_DATA_IN : in std_logic_vector (15 downto 0); -- Data word
+ INT_SLAVE_PACKET_NUM_IN : in std_logic_vector (1 downto 0);
+ INT_SLAVE_READ_OUT : out std_logic;
+
+ -- Status and control port
+ STAT_FIFO_TO_INT : out std_logic_vector(31 downto 0);
+ STAT_FIFO_TO_APL : out std_logic_vector(31 downto 0)
+ );
+ end component;
+
+begin
+
+ BASE_API: trb_net16_base_api
+ generic map (
+ API_TYPE => 1,
+ FIFO_TO_INT_DEPTH => FIFO_TO_INT_DEPTH,
+ FIFO_TO_APL_DEPTH => FIFO_TO_APL_DEPTH,
+ FIFO_TERM_BUFFER_DEPTH => FIFO_TERM_BUFFER_DEPTH
+ )
+ port map (
+ CLK => CLK,
+ CLK_EN => CLK_EN,
+ RESET => RESET,
+
+ APL_DATA_IN => APL_DATA_IN,
+ APL_PACKET_NUM_IN => APL_PACKET_NUM_IN,
+ APL_WRITE_IN => APL_WRITE_IN,
+ APL_FIFO_FULL_OUT => APL_FIFO_FULL_OUT,
+ APL_SHORT_TRANSFER_IN => APL_SHORT_TRANSFER_IN,
+ APL_DTYPE_IN => APL_DTYPE_IN,
+ APL_ERROR_PATTERN_IN => APL_ERROR_PATTERN_IN,
+ APL_SEND_IN => APL_SEND_IN,
+ APL_TARGET_ADDRESS_IN => APL_TARGET_ADDRESS_IN,
+ APL_DATA_OUT => APL_DATA_OUT,
+ APL_PACKET_NUM_OUT => APL_PACKET_NUM_OUT,
+ APL_TYP_OUT => APL_TYP_OUT,
+ APL_DATAREADY_OUT => APL_DATAREADY_OUT,
+ APL_READ_IN => APL_READ_IN,
+
+ -- APL Control port
+ APL_RUN_OUT => APL_RUN_OUT,
+ APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN,
+ APL_SEQNR_OUT => APL_SEQNR_OUT,
+
+ -- Internal direction port
+ INT_MASTER_DATAREADY_OUT => INT_INIT_DATAREADY_OUT,
+ INT_MASTER_DATA_OUT => INT_INIT_DATA_OUT,
+ INT_MASTER_PACKET_NUM_OUT => INT_INIT_PACKET_NUM_OUT,
+ INT_MASTER_READ_IN => INT_INIT_READ_IN,
+
+ INT_MASTER_DATAREADY_IN => INT_INIT_DATAREADY_IN,
+ INT_MASTER_DATA_IN => INT_INIT_DATA_IN,
+ INT_MASTER_PACKET_NUM_IN => INT_INIT_PACKET_NUM_IN,
+ INT_MASTER_READ_OUT => INT_INIT_READ_OUT,
+
+ INT_SLAVE_HEADER_IN => INT_REPLY_HEADER_IN,
+
+ INT_SLAVE_DATAREADY_OUT => INT_REPLY_DATAREADY_OUT,
+ INT_SLAVE_DATA_OUT => INT_REPLY_DATA_OUT,
+ INT_SLAVE_READ_IN => INT_REPLY_READ_IN,
+
+ INT_SLAVE_DATAREADY_IN => INT_REPLY_DATAREADY_IN,
+ INT_SLAVE_DATA_IN => INT_REPLY_DATA_IN,
+ INT_SLAVE_READ_OUT => INT_REPLY_READ_OUT,
+ -- Status and control port
+ STAT_FIFO_TO_INT => STAT_FIFO_TO_INT,
+ STAT_FIFO_TO_APL => STAT_FIFO_TO_APL
+ -- not needed now, but later
+ );
+
+end architecture;
--- /dev/null
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.std_logic_ARITH.ALL;
+USE IEEE.std_logic_UNSIGNED.ALL;
+
+use work.trb_net_std.all;
+
+
+entity trb_net16_base_api is
+
+ generic (API_TYPE : integer := 0; -- type of api: 0 passive, 1 active
+ --FIFO size is given in 2^(n+1) 64Bit-packets i.e. 2^(n+3) 16bit packets
+ FIFO_TO_INT_DEPTH : integer := 0; -- direction to medium
+ FIFO_TO_APL_DEPTH : integer := 0; -- direction to application
+ FIFO_TERM_BUFFER_DEPTH : integer := 0); -- fifo for auto-answering master path
+ -- if set to 0, no buffer is used
+
+ port(
+ -- Misc
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+
+ -- APL Transmitter port
+ APL_DATA_IN : in std_logic_vector (15 downto 0); -- Data word "application to network"
+ APL_PACKET_NUM_IN : in std_logic_vector (1 downto 0);
+ APL_WRITE_IN : in std_logic; -- Data word is valid and should be transmitted
+ APL_FIFO_FULL_OUT : out std_logic; -- Stop transfer, the fifo is full
+ APL_SHORT_TRANSFER_IN : in std_logic; --
+ APL_DTYPE_IN : in std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr
+ APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr
+ APL_SEND_IN : in std_logic; -- Release sending of the data
+ APL_TARGET_ADDRESS_IN : in std_logic_vector (15 downto 0); -- Address of
+ -- the target (only for active APIs)
+
+ -- Receiver port
+ APL_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word "network to application"
+ APL_PACKET_NUM_OUT : out std_logic_vector (1 downto 0);
+ APL_TYP_OUT : out std_logic_vector (2 downto 0); -- Which kind of data word: DAT, HDR or TRM
+ APL_DATAREADY_OUT : out std_logic; -- Data word is valid and might be read out
+ APL_READ_IN : in std_logic; -- Read data word
+
+ -- APL Control port
+ APL_RUN_OUT : out std_logic; -- Data transfer is running
+ APL_MY_ADDRESS_IN : in std_logic_vector (15 downto 0); -- My own address (temporary solution!!!)
+ APL_SEQNR_OUT : out std_logic_vector (7 downto 0);
+
+ -- Internal direction port
+ -- the ports with master or slave in their name are to be mapped by the active api
+ -- to the init respectivly the reply path and vice versa in the passive api.
+ -- lets define: the "master" path is the path that I send data on.
+ INT_MASTER_DATAREADY_OUT : out std_logic;
+ INT_MASTER_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word
+ INT_MASTER_PACKET_NUM_OUT : out std_logic_vector (1 downto 0);
+ INT_MASTER_READ_IN : in std_logic;
+
+ INT_MASTER_DATAREADY_IN : in std_logic;
+ INT_MASTER_DATA_IN : in std_logic_vector (15 downto 0); -- Data word
+ INT_MASTER_PACKET_NUM_IN : in std_logic_vector (1 downto 0);
+ INT_MASTER_READ_OUT : out std_logic;
+
+
+ INT_SLAVE_HEADER_IN : in std_logic; -- Concentrator kindly asks to resend the last
+ -- header (only for the reply path)
+ INT_SLAVE_DATAREADY_OUT : out std_logic;
+ INT_SLAVE_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word
+ INT_SLAVE_PACKET_NUM_OUT : out std_logic_vector (1 downto 0);
+ INT_SLAVE_READ_IN : in std_logic;
+
+ INT_SLAVE_DATAREADY_IN : in std_logic;
+ INT_SLAVE_DATA_IN : in std_logic_vector (15 downto 0); -- Data word
+ INT_SLAVE_PACKET_NUM_IN : in std_logic_vector (1 downto 0);
+ INT_SLAVE_READ_OUT : out std_logic;
+
+ -- Status and control port
+ STAT_FIFO_TO_INT : out std_logic_vector(31 downto 0);
+ STAT_FIFO_TO_APL : out std_logic_vector(31 downto 0)
+ );
+end entity;
+
+
+
+architecture trb_net16_base_api_arch of trb_net16_base_api is
+
+begin
+
+end architecture;
\ No newline at end of file
--- /dev/null
+-- http://hades-wiki.gsi.de/cgi-bin/view/DaqSlowControl/TrbNetFifo
+
+library ieee;
+
+use ieee.std_logic_1164.all;
+USE ieee.std_logic_signed.ALL;
+USE ieee.std_logic_arith.ALL;
+
+
+entity trb_net16_dummy_fifo is
+ generic (
+ DATA_WIDTH : integer := 16; -- FIFO word width
+ NUM_WIDTH : integer := 2;
+ DEPTH : integer := 4 -- Depth of the FIFO, 2^(n+1)
+ );
+ port (
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ DATA_IN : in std_logic_vector(DATA_WIDTH - 1 downto 0); -- Input data
+ PACKET_NUM_IN : in std_logic_vector(NUM_WIDTH - 1 downto 0); -- Input data
+ WRITE_ENABLE_IN : in std_logic;
+ DATA_OUT : out std_logic_vector(DATA_WIDTH - 1 downto 0); -- Output data
+ PACKET_NUM_OUT : out std_logic_vector(NUM_WIDTH - 1 downto 0); -- Input data
+ READ_ENABLE_IN : in std_logic;
+ FULL_OUT : out std_logic; -- Full Flag
+ EMPTY_OUT : out std_logic;
+ DEPTH_OUT : out std_logic_vector(7 downto 0)
+ );
+end entity;
+
+
+architecture arch_trb_net16_dummy_fifo of trb_net16_dummy_fifo is
+begin
+
+end architecture;
+
--- /dev/null
+-- http://hades-wiki.gsi.de/cgi-bin/view/DaqSlowControl/TrbNetFifo
+
+-- The only difference of fifo16 to the original fifo is the division
+-- into a data and a num port - no change in logic, just for easier use.
+
+library ieee;
+
+use ieee.std_logic_1164.all;
+USE ieee.std_logic_signed.ALL;
+USE ieee.std_logic_arith.ALL;
+
+
+
+entity trb_net16_fifo is
+ generic (
+ DATA_WIDTH : integer := 16; -- FIFO word width
+ NUM_WIDTH : integer := 2;
+ DEPTH : integer := 4 -- Depth of the FIFO, 2^(n+1)
+ );
+ port (
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ DATA_IN : in std_logic_vector(DATA_WIDTH - 1 downto 0); -- Input data
+ PACKET_NUM_IN : in std_logic_vector(NUM_WIDTH - 1 downto 0); -- Input data
+ WRITE_ENABLE_IN : in std_logic;
+ DATA_OUT : out std_logic_vector(DATA_WIDTH - 1 downto 0); -- Output data
+ PACKET_NUM_OUT : out std_logic_vector(NUM_WIDTH - 1 downto 0); -- Input data
+ READ_ENABLE_IN : in std_logic;
+ FULL_OUT : out std_logic; -- Full Flag
+ EMPTY_OUT : out std_logic;
+ DEPTH_OUT : out std_logic_vector(7 downto 0)
+ );
+end entity;
+
+
+
--- /dev/null
+-- for a description see HADES wiki
+-- http://hades-wiki.gsi.de/cgi-bin/view/DaqSlowControl/TrbNetIBUF
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.std_logic_ARITH.ALL;
+USE IEEE.std_logic_UNSIGNED.ALL;
+
+use work.trb_net_std.all;
+
+entity trb_net16_ibuf is
+ generic (
+ --FIFO size is given in 2^(n+1) 64Bit-packets i.e. 2^(n+3) 16bit packets
+ DEPTH : integer := 3
+ );
+ port(
+ -- Misc
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ -- Media direction port
+ MED_DATAREADY_IN: in std_logic; -- Data word is offered by the Media (the IOBUF MUST read)
+ MED_DATA_IN: in std_logic_vector (15 downto 0); -- Data word
+ MED_PACKET_NUM_IN :out std_logic_vector(1 downto 0);
+ MED_READ_OUT: out std_logic; -- buffer reads a word from media
+ MED_ERROR_IN: in std_logic_vector (2 downto 0); -- Status bits
+ -- Internal direction port
+ INT_HEADER_IN: in std_logic; -- Concentrator kindly asks to resend the last header
+ INT_DATAREADY_OUT: out std_logic;
+ INT_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word
+ INT_PACKET_NUM_IN: in std_logic_vector(1 downto 0);
+ INT_READ_IN: in std_logic;
+ INT_ERROR_OUT: out std_logic_vector (2 downto 0); -- Status bits
+ -- Status and control port
+ STAT_LOCKED: out std_logic_vector (15 downto 0);
+ CTRL_LOCKED: in std_logic_vector (15 downto 0);
+ STAT_BUFFER: out std_logic_vector (31 downto 0)
+ );
+end entity;
+
+architecture trb_net16_ibuf_arch of trb_net16_ibuf is
+
+ component trb_net16_fifo is
+ generic (
+ DATA_WIDTH : integer := 16; -- FIFO word width
+ NUM_WIDTH : integer := 2;
+ DEPTH : integer := 4); -- Depth of the FIFO, 2^(n+1)
+ port (
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ DATA_IN : in std_logic_vector(DATA_WIDTH - 1 downto 0); -- Input data
+ PACKET_NUM_IN : in std_logic_vector(NUM_WIDTH - 1 downto 0); -- Input data
+ WRITE_ENABLE_IN : in std_logic;
+ DATA_OUT : out std_logic_vector(DATA_WIDTH - 1 downto 0); -- Output data
+ PACKET_NUM_OUT : out std_logic_vector(NUM_WIDTH - 1 downto 0); -- Input data
+ READ_ENABLE_IN : in std_logic;
+ FULL_OUT : out std_logic; -- Full Flag
+ EMPTY_OUT : out std_logic;
+ DEPTH_OUT : out std_logic_vector(7 downto 0)
+ );
+ end component;
+
+ component trb_net16_sbuf is
+ generic (
+ DATA_WIDTH : integer := 16;
+ NUM_WIDTH : integer := 2;
+ VERSION : integer := 0
+ );
+ port(
+ -- Misc
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ -- port to combinatorial logic
+ COMB_DATAREADY_IN: in std_logic; --comb logic provides data word
+ COMB_next_READ_OUT: out std_logic; --sbuf can read in NEXT cycle
+ COMB_READ_IN: in std_logic; --comb logic IS reading
+ COMB_DATA_IN: in std_logic_vector (DATA_WIDTH-1 downto 0); -- Data word
+ COMB_PACKET_NUM_IN: in std_logic_vector(NUM_WIDTH-1 downto 0);
+ -- Port to synchronous output.
+ SYN_DATAREADY_OUT: out std_logic;
+ SYN_DATA_OUT: out std_logic_vector (DATA_WIDTH-1 downto 0); -- Data word
+ SYN_PACKET_NUM_OUT: out std_logic_vector(NUM_WIDTH-1 downto 0);
+ SYN_READ_IN: in std_logic;
+ -- Status and control port
+ STAT_BUFFER: out std_logic
+ );
+ end component;
+
+
+begin
+
+end architecture;
+
--- /dev/null
+-- main working horse for the trbnet
+-- for a description see HADES wiki
+-- http://hades-wiki.gsi.de/cgi-bin/view/DaqSlowControl/TrbNetIOBUF
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.std_logic_ARITH.ALL;
+USE IEEE.std_logic_UNSIGNED.ALL;
+
+use work.trb_net_std.all;
+
+--Entity decalaration for clock generator
+entity trb_net16_iobuf is
+ generic (
+ --FIFO size is given in 2^(n+1) 64Bit-packets i.e. 2^(n+3) 16bit packets
+ INIT_DEPTH : integer := 3;
+ REPLY_DEPTH : integer := 3);
+ port(
+ -- Misc
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ -- Media direction port
+ MED_INIT_DATAREADY_OUT: out std_logic; --Data word ready to be read out
+ --by the media (via the TrbNetIOMultiplexer)
+ MED_INIT_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word
+ MED_INIT_PACKET_NUM_OUT:out std_logic_vector (1 downto 0);
+ MED_INIT_READ_IN: in std_logic; -- Media is reading
+
+ MED_INIT_DATAREADY_IN: in std_logic; -- Data word is offered by the Media
+ -- (the IOBUF MUST read)
+ MED_INIT_DATA_IN: in std_logic_vector (15 downto 0); -- Data word
+ MED_INIT_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
+ MED_INIT_READ_OUT: out std_logic; -- buffer reads a word from media
+ MED_INIT_ERROR_IN: in std_logic_vector (2 downto 0); -- Status bits
+
+ MED_REPLY_DATAREADY_OUT: out std_logic; --Data word ready to be read out
+ --by the media (via the TrbNetIOMultiplexer)
+ MED_REPLY_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word
+ MED_REPLY_PACKET_NUM_OUT:out std_logic_vector (1 downto 0);
+ MED_REPLY_READ_IN: in std_logic; -- Media is reading
+
+ MED_REPLY_DATAREADY_IN: in std_logic; -- Data word is offered by the Media
+ -- (the IOBUF MUST read)
+ MED_REPLY_DATA_IN: in std_logic_vector (15 downto 0); -- Data word
+ MED_REPLY_PACKET_NUM_IN :in std_logic_vector (1 downto 0);
+ MED_REPLY_READ_OUT: out std_logic; -- buffer reads a word from media
+ MED_REPLY_ERROR_IN: in std_logic_vector (2 downto 0); -- Status bits
+
+ -- Internal direction port
+
+ INT_INIT_DATAREADY_OUT: out std_logic;
+ INT_INIT_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word
+ INT_INIT_PACKET_NUM_OUT:out std_logic_vector (1 downto 0);
+ INT_INIT_READ_IN: in std_logic;
+
+ INT_INIT_DATAREADY_IN: in std_logic;
+ INT_INIT_DATA_IN: in std_logic_vector (15 downto 0); -- Data word
+ INT_INIT_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
+ INT_INIT_READ_OUT: out std_logic;
+
+ INT_REPLY_HEADER_IN: in std_logic; -- Concentrator kindly asks to resend the last
+ -- header (only for the reply path)
+ INT_REPLY_DATAREADY_OUT: out std_logic;
+ INT_REPLY_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word
+ INT_REPLY_PACKET_NUM_OUT:out std_logic_vector (1 downto 0);
+ INT_REPLY_READ_IN: in std_logic;
+
+ INT_REPLY_DATAREADY_IN: in std_logic;
+ INT_REPLY_DATA_IN: in std_logic_vector (15 downto 0); -- Data word
+ INT_REPLY_PACKET_NUM_IN :in std_logic_vector (1 downto 0);
+ INT_REPLY_READ_OUT: out std_logic;
+
+ -- Status and control port
+ STAT_GEN: out std_logic_vector (31 downto 0); -- General Status
+ STAT_LOCKED: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control
+ STAT_INIT_BUFFER: out std_logic_vector (31 downto 0); -- Status of the handshake and buffer control
+ STAT_REPLY_BUFFER: out std_logic_vector (31 downto 0); -- General Status
+ CTRL_GEN: in std_logic_vector (31 downto 0);
+ CTRL_LOCKED: in std_logic_vector (31 downto 0);
+ STAT_CTRL_INIT_BUFFER: in std_logic_vector (31 downto 0);
+ STAT_CTRL_REPLY_BUFFER: in std_logic_vector (31 downto 0)
+ );
+end entity;
+
+architecture trb_net16_iobuf_arch of trb_net16_iobuf is
+
+ component trb_net16_obuf is
+ generic (
+ DATA_COUNT_WIDTH : integer := 4;
+ );
+ port(
+ -- Misc
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ -- Media direction port
+ MED_DATAREADY_OUT: out std_logic;
+ MED_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word
+ MED_PACKET_NUM_OUT:out std_logic_vector(1 downto 0);
+ MED_READ_IN: in std_logic;
+ -- Internal direction port
+ INT_DATAREADY_IN: in std_logic;
+ INT_DATA_IN: in std_logic_vector (15 downto 0); -- Data word
+ INT_PACKET_NUM_IN: in std_logic_vector(1 downto 0);
+ INT_READ_OUT: out std_logic;
+ -- Status and control port
+ STAT_LOCKED: out std_logic_vector (15 downto 0);
+ CTRL_LOCKED: in std_logic_vector (15 downto 0);
+ STAT_BUFFER: out std_logic_vector (31 downto 0);
+ CTRL_BUFFER: in std_logic_vector (31 downto 0)
+ );
+ end component;
+
+ component trb_net16_ibuf is
+ generic (
+ DEPTH : integer := 3 -- Depth of the FIFO, 2^(n+1)
+ );
+ port(
+ -- Misc
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ -- Media direction port
+ MED_DATAREADY_IN: in std_logic; -- Data word is offered by the Media (the IOBUF MUST read)
+ MED_DATA_IN: in std_logic_vector (15 downto 0); -- Data word
+ MED_PACKET_NUM_IN :out std_logic_vector(1 downto 0);
+ MED_READ_OUT: out std_logic; -- buffer reads a word from media
+ MED_ERROR_IN: in std_logic_vector (2 downto 0); -- Status bits
+ -- Internal direction port
+ INT_HEADER_IN: in std_logic; -- Concentrator kindly asks to resend the last header
+ INT_DATAREADY_OUT: out std_logic;
+ INT_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word
+ INT_PACKET_NUM_IN: in std_logic_vector(1 downto 0);
+ INT_READ_IN: in std_logic;
+ INT_ERROR_OUT: out std_logic_vector (2 downto 0); -- Status bits
+ -- Status and control port
+ STAT_LOCKED: out std_logic_vector (15 downto 0);
+ CTRL_LOCKED: in std_logic_vector (15 downto 0);
+ STAT_BUFFER: out std_logic_vector (31 downto 0)
+ );
+ end component;
+
+
+begin
+
+
+end architecture;
+
--- /dev/null
+-- for a description see HADES wiki
+-- http://hades-wiki.gsi.de/cgi-bin/view/DaqSlowControl/TrbNetOBUF
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+use work.trb_net_std.all;
+
+
+entity trb_net16_obuf is
+ generic (
+ DATA_COUNT_WIDTH : integer := 4;
+ );
+ port(
+ -- Misc
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ -- Media direction port
+ MED_DATAREADY_OUT: out STD_LOGIC;
+ MED_DATA_OUT: out STD_LOGIC_VECTOR (15 downto 0); -- Data word
+ MED_PACKET_NUM_OUT:out STD_LOGIC_VECTOR(1 downto 0);
+ MED_READ_IN: in STD_LOGIC;
+ -- Internal direction port
+ INT_DATAREADY_IN: in STD_LOGIC;
+ INT_DATA_IN: in STD_LOGIC_VECTOR (15 downto 0); -- Data word
+ INT_PACKET_NUM_IN: in STD_LOGIC_VECTOR(1 downto 0);
+ INT_READ_OUT: out STD_LOGIC;
+ -- Status and control port
+ STAT_LOCKED: out STD_LOGIC_VECTOR (15 downto 0);
+ CTRL_LOCKED: in STD_LOGIC_VECTOR (15 downto 0);
+ STAT_BUFFER: out STD_LOGIC_VECTOR (31 downto 0);
+ CTRL_BUFFER: in STD_LOGIC_VECTOR (31 downto 0)
+ );
+end entity;
+
+architecture trb_net16_obuf_arch of trb_net16_obuf is
+
+ component trb_net16_sbuf is
+ generic (
+ DATA_WIDTH : integer := 16;
+ NUM_WIDTH : integer := 2;
+ VERSION : integer := 0
+ );
+ port(
+ -- Misc
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ -- port to combinatorial logic
+ COMB_DATAREADY_IN: in STD_LOGIC; --comb logic provides data word
+ COMB_next_READ_OUT: out STD_LOGIC; --sbuf can read in NEXT cycle
+ COMB_READ_IN: in STD_LOGIC; --comb logic IS reading
+ COMB_DATA_IN: in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word
+ COMB_PACKET_NUM_IN: in STD_LOGIC_VECTOR(NUM_WIDTH-1 downto 0);
+ -- Port to synchronous output.
+ SYN_DATAREADY_OUT: out STD_LOGIC;
+ SYN_DATA_OUT: out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word
+ SYN_PACKET_NUM_OUT: out STD_LOGIC_VECTOR(NUM_WIDTH-1 downto 0);
+ SYN_READ_IN: in STD_LOGIC;
+ -- Status and control port
+ STAT_BUFFER: out STD_LOGIC
+ );
+ end component;
+
+ begin
+
+
+end architecture;
+
--- /dev/null
+-- connection between the TRBNET and any application
+-- for a description see HADES wiki
+-- http://hades-wiki.gsi.de/cgi-bin/view/DaqSlowControl/TrbNetAPI
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+use work.trb_net_std.all;
+
+
+entity trb_net16_passive_api is
+
+ generic (
+ --FIFO size is given in 2^(n+1) 64Bit-packets i.e. 2^(n+3) 16bit packets
+ FIFO_TO_INT_DEPTH : integer := 0; -- direction to medium
+ FIFO_TO_APL_DEPTH : integer := 0; -- direction to application
+ FIFO_TERM_BUFFER_DEPTH : integer := 0 -- fifo for auto-answering master path
+ -- if set to 0, no buffer is used
+ );
+
+ port(
+ -- Misc
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+
+ -- APL Transmitter port
+ APL_DATA_IN : in std_logic_vector (15 downto 0); -- Data word "application to network"
+ APL_PACKET_NUM_IN : in std_logic_vector (1 downto 0);
+ APL_WRITE_IN : in std_logic; -- Data word is valid and should be transmitted
+ APL_FIFO_FULL_OUT : out std_logic; -- Stop transfer, the fifo is full
+ APL_SHORT_TRANSFER_IN : in std_logic; --
+ APL_DTYPE_IN : in std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr
+ APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr
+ APL_SEND_IN : in std_logic; -- Release sending of the data
+ APL_TARGET_ADDRESS_IN : in std_logic_vector (15 downto 0); -- Address of
+ -- the target (only for active APIs)
+
+ -- Receiver port
+ APL_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word "network to application"
+ APL_PACKET_NUM_OUT : out std_logic_vector (1 downto 0);
+ APL_TYP_OUT : out std_logic_vector (2 downto 0); -- Which kind of data word: DAT, HDR or TRM
+ APL_DATAREADY_OUT : out std_logic; -- Data word is valid and might be read out
+ APL_READ_IN : in std_logic; -- Read data word
+
+ -- APL Control port
+ APL_RUN_OUT : out std_logic; -- Data transfer is running
+ APL_MY_ADDRESS_IN : in std_logic_vector (15 downto 0); -- My own address (temporary solution!!!)
+ APL_SEQNR_OUT : out std_logic_vector (7 downto 0);
+
+ -- Internal direction port
+ -- the ports with master or slave in their name are to be mapped by the active api
+ -- to the init respectivly the reply path and vice versa in the passive api.
+ -- lets define: the "master" path is the path that I send data on.
+ INT_INIT_DATAREADY_OUT : out std_logic;
+ INT_INIT_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word
+ INT_INIT_PACKET_NUM_OUT : out std_logic_vector (1 downto 0);
+ INT_INIT_READ_IN : in std_logic;
+
+ INT_INIT_DATAREADY_IN : in std_logic;
+ INT_INIT_DATA_IN : in std_logic_vector (15 downto 0); -- Data word
+ INT_INIT_PACKET_NUM_IN : in std_logic_vector (1 downto 0);
+ INT_INIT_READ_OUT : out std_logic;
+
+
+ INT_REPLY_HEADER_IN : in std_logic; -- Concentrator kindly asks to resend the last
+ -- header (only for the reply path)
+ INT_REPLY_DATAREADY_OUT : out std_logic;
+ INT_REPLY_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word
+ INT_REPLY_PACKET_NUM_OUT : out std_logic_vector (1 downto 0);
+ INT_REPLY_READ_IN : in std_logic;
+
+ INT_REPLY_DATAREADY_IN : in std_logic;
+ INT_REPLY_DATA_IN : in std_logic_vector (15 downto 0); -- Data word
+ INT_REPLY_PACKET_NUM_IN : in std_logic_vector (1 downto 0);
+ INT_REPLY_READ_OUT : out std_logic;
+
+ -- Status and control port
+ STAT_FIFO_TO_INT : out std_logic_vector(31 downto 0);
+ STAT_FIFO_TO_APL : out std_logic_vector(31 downto 0)
+ );
+end entity;
+
+architecture trb_net16_passive_api_arch of trb_net16_passive_api is
+
+ component trb_net16_base_api is
+ generic (
+ API_TYPE : integer := 0; -- type of api: 0 passive, 1 active
+ --FIFO size is given in 2^(n+1) 64Bit-packets i.e. 2^(n+3) 16bit packets
+ FIFO_TO_INT_DEPTH : integer := 0; -- direction to medium
+ FIFO_TO_APL_DEPTH : integer := 0; -- direction to application
+ FIFO_TERM_BUFFER_DEPTH : integer := 0); -- fifo for auto-answering master path
+ -- if set to 0, no buffer is used
+ port(
+ -- Misc
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+
+ -- APL Transmitter port
+ APL_DATA_IN : in std_logic_vector (15 downto 0); -- Data word "application to network"
+ APL_PACKET_NUM_IN : in std_logic_vector (1 downto 0);
+ APL_WRITE_IN : in std_logic; -- Data word is valid and should be transmitted
+ APL_FIFO_FULL_OUT : out std_logic; -- Stop transfer, the fifo is full
+ APL_SHORT_TRANSFER_IN : in std_logic; --
+ APL_DTYPE_IN : in std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr
+ APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr
+ APL_SEND_IN : in std_logic; -- Release sending of the data
+ APL_TARGET_ADDRESS_IN : in std_logic_vector (15 downto 0); -- Address of
+ -- the target (only for active APIs)
+
+ -- Receiver port
+ APL_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word "network to application"
+ APL_PACKET_NUM_OUT : out std_logic_vector (1 downto 0);
+ APL_TYP_OUT : out std_logic_vector (2 downto 0); -- Which kind of data word: DAT, HDR or TRM
+ APL_DATAREADY_OUT : out std_logic; -- Data word is valid and might be read out
+ APL_READ_IN : in std_logic; -- Read data word
+
+ -- APL Control port
+ APL_RUN_OUT : out std_logic; -- Data transfer is running
+ APL_MY_ADDRESS_IN : in std_logic_vector (15 downto 0); -- My own address (temporary solution!!!)
+ APL_SEQNR_OUT : out std_logic_vector (7 downto 0);
+
+ -- Internal direction port
+ -- the ports with master or slave in their name are to be mapped by the active api
+ -- to the init respectivly the reply path and vice versa in the passive api.
+ -- lets define: the "master" path is the path that I send data on.
+ INT_MASTER_DATAREADY_OUT : out std_logic;
+ INT_MASTER_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word
+ INT_MASTER_PACKET_NUM_OUT : out std_logic_vector (1 downto 0);
+ INT_MASTER_READ_IN : in std_logic;
+
+ INT_MASTER_DATAREADY_IN : in std_logic;
+ INT_MASTER_DATA_IN : in std_logic_vector (15 downto 0); -- Data word
+ INT_MASTER_PACKET_NUM_IN : in std_logic_vector (1 downto 0);
+ INT_MASTER_READ_OUT : out std_logic;
+
+
+ INT_SLAVE_HEADER_IN : in std_logic; -- Concentrator kindly asks to resend the last
+ -- header (only for the reply path)
+ INT_SLAVE_DATAREADY_OUT : out std_logic;
+ INT_SLAVE_DATA_OUT : out std_logic_vector (15 downto 0); -- Data word
+ INT_SLAVE_PACKET_NUM_OUT : out std_logic_vector (1 downto 0);
+ INT_SLAVE_READ_IN : in std_logic;
+
+ INT_SLAVE_DATAREADY_IN : in std_logic;
+ INT_SLAVE_DATA_IN : in std_logic_vector (15 downto 0); -- Data word
+ INT_SLAVE_PACKET_NUM_IN : in std_logic_vector (1 downto 0);
+ INT_SLAVE_READ_OUT : out std_logic;
+
+ -- Status and control port
+ STAT_FIFO_TO_INT : out std_logic_vector(31 downto 0);
+ STAT_FIFO_TO_APL : out std_logic_vector(31 downto 0)
+ );
+ end component;
+
+begin
+
+ BASE_API: trb_net16_base_api
+ generic map (
+ API_TYPE => 0,
+ FIFO_TO_INT_DEPTH => FIFO_TO_INT_DEPTH,
+ FIFO_TO_APL_DEPTH => FIFO_TO_APL_DEPTH,
+ FIFO_TERM_BUFFER_DEPTH => FIFO_TERM_BUFFER_DEPTH
+ )
+ port map (
+ CLK => CLK,
+ CLK_EN => CLK_EN,
+ RESET => RESET,
+
+ APL_DATA_IN => APL_DATA_IN,
+ APL_PACKET_NUM_IN => APL_PACKET_NUM_IN,
+ APL_WRITE_IN => APL_WRITE_IN,
+ APL_FIFO_FULL_OUT => APL_FIFO_FULL_OUT,
+ APL_SHORT_TRANSFER_IN => APL_SHORT_TRANSFER_IN,
+ APL_DTYPE_IN => APL_DTYPE_IN,
+ APL_ERROR_PATTERN_IN => APL_ERROR_PATTERN_IN,
+ APL_SEND_IN => APL_SEND_IN,
+ APL_TARGET_ADDRESS_IN => APL_TARGET_ADDRESS_IN,
+ APL_DATA_OUT => APL_DATA_OUT,
+ APL_PACKET_NUM_OUT => APL_PACKET_NUM_OUT,
+ APL_TYP_OUT => APL_TYP_OUT,
+ APL_DATAREADY_OUT => APL_DATAREADY_OUT,
+ APL_READ_IN => APL_READ_IN,
+
+ -- APL Control port
+ APL_RUN_OUT => APL_RUN_OUT,
+ APL_MY_ADDRESS_IN => APL_MY_ADDRESS_IN,
+ APL_SEQNR_OUT => APL_SEQNR_OUT,
+
+ -- Internal direction port
+ INT_MASTER_DATAREADY_OUT => INT_REPLY_DATAREADY_OUT,
+ INT_MASTER_DATA_OUT => INT_REPLY_DATA_OUT,
+ INT_MASTER_PACKET_NUM_OUT => INT_REPLY_PACKET_NUM_OUT,
+ INT_MASTER_READ_IN => INT_REPLY_READ_IN,
+
+ INT_MASTER_DATAREADY_IN => INT_REPLY_DATAREADY_IN,
+ INT_MASTER_DATA_IN => INT_REPLY_DATA_IN,
+ INT_MASTER_PACKET_NUM_IN => INT_REPLY_PACKET_NUM_IN,
+ INT_MASTER_READ_OUT => INT_REPLY_READ_OUT,
+
+ INT_SLAVE_HEADER_IN => INT_INIT_HEADER_IN,
+
+ INT_SLAVE_DATAREADY_OUT => INT_INIT_DATAREADY_OUT,
+ INT_SLAVE_DATA_OUT => INT_INIT_DATA_OUT,
+ INT_SLAVE_READ_IN => INT_INIT_READ_IN,
+
+ INT_SLAVE_DATAREADY_IN => INT_INIT_DATAREADY_IN,
+ INT_SLAVE_DATA_IN => INT_INIT_DATA_IN,
+ INT_SLAVE_READ_OUT => INT_INIT_READ_OUT,
+ -- Status and control port
+ STAT_FIFO_TO_INT => STAT_FIFO_TO_INT,
+ STAT_FIFO_TO_APL => STAT_FIFO_TO_APL
+ -- not needed now, but later
+ );
+
+end architecture;
--- /dev/null
+-------------------------------------------------------------------------------
+-- Single buffer with one more buffer to keep the speed of the datalink
+-- The sbuf can be connected to a combinatorial logic (as an output buffer)
+-- to provide the synchronous logic
+--
+-- 2 versions are provided
+-- VERSION=0 is the fast version, so double buffering is done
+-- VERSION=1 is half data rate: After data has beed written to the sbuf,
+-- the input read signal is stalled until the buffer is empty.
+-- Maybe enough for trigger and slow control channels
+--
+-- The only difference of sbuf16 to the original sbuf is the division
+-- into a data and a num port - no change in logic, just for easier use.
+-------------------------------------------------------------------------------
+
+
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+use work.trb_net_std.all;
+
+entity trb_net16_sbuf is
+ generic (
+ DATA_WIDTH : integer := 16;
+ NUM_WIDTH : integer := 2;
+ VERSION : integer := 0
+ );
+ port(
+ -- Misc
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ -- port to combinatorial logic
+ COMB_DATAREADY_IN : in STD_LOGIC; --comb logic provides data word
+ COMB_next_READ_OUT: out STD_LOGIC; --sbuf can read in NEXT cycle
+ COMB_READ_IN : in STD_LOGIC; --comb logic IS reading
+ COMB_DATA_IN : in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word
+ COMB_PACKET_NUM_IN: in STD_LOGIC_VECTOR(NUM_WIDTH-1 downto 0);
+ -- Port to synchronous output.
+ SYN_DATAREADY_OUT : out STD_LOGIC;
+ SYN_DATA_OUT : out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word
+ SYN_PACKET_NUM_OUT: out STD_LOGIC_VECTOR(NUM_WIDTH-1 downto 0);
+ SYN_READ_IN : in STD_LOGIC;
+ -- Status and control port
+ STAT_BUFFER : out STD_LOGIC
+ );
+end entity;
+
+architecture trb_net16_sbuf_arch of trb_net16_sbuf is
+
+
+begin
+
+end architecture;
+
--- /dev/null
+-- this is just a terminator, which auto-answers requests
+-- for a description see HADES wiki
+-- http://hades-wiki.gsi.de/cgi-bin/view/DaqSlowControl/TrbNetTerm
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.std_logic_ARITH.ALL;
+USE IEEE.std_logic_UNSIGNED.ALL;
+
+use work.trb_net_std.all;
+
+
+entity trb_net16_term is
+ generic (
+ FIFO_TERM_BUFFER_DEPTH : integer := 0 -- fifo for auto-answering of
+ -- the master path, if set to 0
+ -- no buffer is used at all
+ );
+ port(
+ -- Misc
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+
+ INT_DATAREADY_OUT: out std_logic;
+ INT_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word
+ INT_PACKET_NUM_OUT: out std_logic_vector (1 downto 0);
+ INT_READ_IN: in std_logic;
+
+ INT_DATAREADY_IN: in std_logic;
+ INT_DATA_IN: in std_logic_vector (15 downto 0); -- Data word
+ INT_PACKET_NUM_IN: in std_logic_vector (1 downto 0);
+ INT_READ_OUT: out std_logic;
+
+ -- "mini" APL, just to see the triggers coming in
+ APL_DTYPE_OUT: out std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr
+ APL_ERROR_PATTERN_OUT: out std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr
+ APL_SEQNR_OUT: out std_logic_vector (7 downto 0);
+ APL_GOT_TRM: out std_logic;
+
+ APL_HOLD_TRM: in std_logic;
+ APL_DTYPE_IN: in std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr
+ APL_ERROR_PATTERN_IN: in std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr
+ APL_MY_ADDRESS_IN: in std_logic_vector (15 downto 0) -- My own address (temporary solution!!!)
+ -- Status and control port
+ );
+end entity;
+
+architecture trb_net16_term_arch of trb_net16_term is
+
+ component trb_net16_fifo is
+ generic (
+ DATA_WIDTH : integer := 16; -- FIFO word width
+ NUM_WIDTH : integer := 2;
+ DEPTH : integer := 4 -- Depth of the FIFO, 2^(n+1)
+ );
+ port (
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ DATA_IN : in std_logic_vector(DATA_WIDTH - 1 downto 0); -- Input data
+ PACKET_NUM_IN : in std_logic_vector(NUM_WIDTH - 1 downto 0); -- Input data
+ WRITE_ENABLE_IN : in std_logic;
+ DATA_OUT : out std_logic_vector(DATA_WIDTH - 1 downto 0); -- Output data
+ PACKET_NUM_OUT : out std_logic_vector(NUM_WIDTH - 1 downto 0); -- Input data
+ READ_ENABLE_IN : in std_logic;
+ FULL_OUT : out std_logic; -- Full Flag
+ EMPTY_OUT : out std_logic;
+ DEPTH_OUT : out std_logic_vector(7 downto 0)
+ );
+ end component;
+
+begin
+
+end architecture;
--- /dev/null
+-- for a description see HADES wiki
+-- http://hades-wiki.gsi.de/cgi-bin/view/DaqSlowControl/TrbNetIBUF
+-- This has in principle the same output ports, but internally
+-- it keeps only the TRM words
+-- EOB are killed
+-- ACK are regognized
+-- all other words (HDR, DAT) are not stored
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+use work.trb_net_std.all;
+
+
+entity trb_net16_term_ibuf is
+ port(
+ -- Misc
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ -- Media direction port
+ MED_DATAREADY_IN: in std_logic; -- Data word is offered by the Media (the IOBUF MUST read)
+ MED_DATA_IN: in std_logic_vector (15 downto 0); -- Data word
+ MED_PACKET_NUM_IN :out std_logic_vector(1 downto 0);
+ MED_READ_OUT: out std_logic; -- buffer reads a word from media
+ MED_ERROR_IN: in std_logic_vector (2 downto 0); -- Status bits
+ -- Internal direction port
+ INT_HEADER_IN: in std_logic; -- Concentrator kindly asks to resend the last header
+ INT_DATAREADY_OUT: out std_logic;
+ INT_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word
+ INT_PACKET_NUM_IN: in std_logic_vector(1 downto 0);
+ INT_READ_IN: in std_logic;
+ INT_ERROR_OUT: out std_logic_vector (2 downto 0); -- Status bits
+ -- Status and control port
+ STAT_LOCKED: out std_logic_vector (15 downto 0);
+ CTRL_LOCKED: in std_logic_vector (15 downto 0);
+ STAT_BUFFER: out std_logic_vector (31 downto 0)
+ );
+end entity;
+
+architecture trb_net16_term_ibuf_arch of trb_net16_term_ibuf is
+
+ component trb_net16_sbuf is
+ generic (
+ DATA_WIDTH : integer := 16;
+ NUM_WIDTH : integer := 2;
+ VERSION : integer := 0
+ );
+ port(
+ -- Misc
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ -- port to combinatorial logic
+ COMB_DATAREADY_IN : in STD_LOGIC; --comb logic provides data word
+ COMB_next_READ_OUT: out STD_LOGIC; --sbuf can read in NEXT cycle
+ COMB_READ_IN : in STD_LOGIC; --comb logic IS reading
+ COMB_DATA_IN : in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word
+ COMB_PACKET_NUM_IN: in STD_LOGIC_VECTOR(NUM_WIDTH-1 downto 0);
+ -- Port to synchronous output.
+ SYN_DATAREADY_OUT : out STD_LOGIC;
+ SYN_DATA_OUT : out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word
+ SYN_PACKET_NUM_OUT: out STD_LOGIC_VECTOR(NUM_WIDTH-1 downto 0);
+ SYN_READ_IN : in STD_LOGIC;
+ -- Status and control port
+ STAT_BUFFER : out STD_LOGIC
+ );
+ end component;
+
+
+begin
+
+end architecture;
\ No newline at end of file
jspc29 / trbnet.git / commitdiff