| | ++> gbe_response_constructor_DHCP
| | ++> gbe_response_constructor_Ping
| | ++> gbe_response_constructor_SCTRL
- | | +-> gbe_response_constructor_Forward
+ | | ++> gbe_response_constructor_Forward
| +-> gbe_transmit_control
| +-> gbe_frame_constr
| +-> gbe_receive_control +-> gbe_protocol_prioritizer
| | +-> i2c_sendb
| +-> trb_net_i2cwire2 +-> i2c_slim2 +-> i2c_gstart2
| +-> i2c_sendb2
- +-> trb_net16_regio_bus_handler_record +-> ???
+ +-> trb_net16_regio_bus_handler_record
+-> tomcat_tools +-> trb_net16_regio_bus_handler_record
| +-> spi_flash_and_fpga_reload_record +-> trb_net16_regio_bus_handler
| | +-> spi_master +-> spi_slim
| | +-> fifo_9x2k_oreg
| +-> i2c_slim2 +-> i2c_gstart2
| +-> i2c_sendb2
- +-> gbe_med_fifo +-> ???
+ +-> gbe_med_fifo +-> serdes_gbe_4ch_ds
+ | +-> gbe_sci_reader
+ | +-> signal_sync
+ | +-> inserter +-> fifo_inserter
+ | +-> remover +-> fifo_remover
+ | +-> sgmii_gbe_pcs42
+ | +-> tsmac41
+ | +-> gbe_mac_control
+ | +-> gbe_lsm
+ | +-> gbe_rx_rb +-> rb_4k_9
+ | +-> gbe_tx_fifo +-> fifo_4k_9
+-> gbe_tx_reset
+
+
+
+
+======================================================================================================================
+gbe_frame_receiver FIFO usage:
+
+4096x9 -> 8bit -> frame data
+ 1bit -> end of frame bit
+
+512x32 -> 16bit -> fr_frame_size
+ 16bit -> fr_frame_proto (fr_frame_type)
+
+512x72 -> 48bit -> fr_src_mac
+ 16bit -> fr_src_udp
+ 8bit -> UNUSED
+
+512x72 -> 48bit -> fr_dst_mac
+ 16bit -> fr_dst_udp
+ 8bit -> UNUSED
+
+512x72 -> 32bit -> fr_src_ip
+ 32bit -> fr_dst_ip
+ 8bit -> fr_ip_proto
+
+
add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp3/media/serdes_gbe_4ch_ds.vhd"
add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_sci_reader.vhd"
add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_define_RS.vhd"
-add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/main_rx_reset_RS.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/gbe_rx_reset.vhd"
add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/gbe_tx_reset.vhd"
add_file -vhdl -lib work "../../trbnet/gbe_trb/base/inserter.vhd"
add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp3/cores/fifo_remover.vhd"
add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_rx_rb.vhd"
-add_file -vhdl -lib work "../../trbnet/gbe_trb/base/tx_fifo.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_tx_fifo.vhd"
add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_lsm.vhd"
-add_file -vhdl -lib work "../../trbnet/gbe_trb/base/scatter_ports.vhd"
-add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gather_ports.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/base/scatter_ports.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gather_ports.vhd"
add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_sgl_ctrl.vhd"
add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp3/cores/rb_4k_9.vhd"
use work.version.all;
use work.config.all;
use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.trb3_components.all;
+--use work.trb_net_components.all;
use work.version.all;
---use work.trb_net_gbe_components.all;
use work.med_sync_define_RS.all;
-- BUG: backplane handling!!!
-- 8 : fifo_eof
-- 7..0: data
- DBG(31 downto 0) <= debug_pcsd(31 downto 0);
+-- DBG(31 downto 0) <= debug_pcsd(31 downto 0);
DBG(32) <= '0';
DBG(33) <= master_clk;
MAKE_RESET_OUT => reset_via_gbe,
-- debug
STATUS_OUT => status,
- DEBUG_OUT => open
+ DEBUG_OUT => DBG(31 downto 0) --open
);
-------------------------------------------------------------------------------