add tables with error bits to Trb3 docu

diff --git a/trb3/ReadoutAcceleration.tex b/trb3/ReadoutAcceleration.tex
new file mode 100644 (file)
index 0000000..47b61de
--- /dev/null
+++ b/trb3/ReadoutAcceleration.tex
@@ -0,0 +1 @@
+\section{Accelerated Readout}

diff --git a/trb3/main.tex b/trb3/main.tex
index 458656989710fc900bb931637a85731a8b509c7b..98767c9b4628b337684dd1550b4786932a978259 100644 (file)
--- a/trb3/main.tex
+++ b/trb3/main.tex
@@ -154,6 +154,8 @@
     \input{Trb3GeneralRemarks}
   \section{Slow Control Registers}
     \input{sctrladdresses}
+  \section{Status and Error Markers}
+    \input{statusbits}
 \cleardoublepage
 \part{Hardware}
   \section{TRB3 Platform}
@@ -221,6 +223,8 @@
   \input{TriggerModule}      
   \clearpage
   \input{FlashSettings}      
+  \clearpage
+  \input{ReadoutAcceleration}
 
   \clearpage
   \section{GbE Data Read-out}

diff --git a/trb3/statusbits.tex b/trb3/statusbits.tex
new file mode 100644 (file)
index 0000000..b8ff0e5
--- /dev/null
+++ b/trb3/statusbits.tex
@@ -0,0 +1,93 @@
+Every transfer in TrbNet is accompanied by a set of status and error flags. Usually these go unnoticed, but are visible in several places:
+
+\begin{itemize}
+\item In the data stream the last word of each SubEvent shows the combined flags of all front-ends delivering data in this SubEvent. These are the statusbits of the data channel.
+\item \verb!trbcmd! shows these bits decoded with a warning or error label. 
+\end{itemize}
+
+\subsection{Common Error and Status Bits}
+For each transmission there are 32 bits that give a rough overview of the status of the boards and transport error information. The meaning of the upper 16 bit depends on the channel while the lower 16 bit are the same on all channels. Their meaning is given in table \ref{commonerrorbits}. 
+
+\begin{table}[hbp]
+\begin{center}
+\begin{tabularx}{\textwidth}{|c|c|C|}
+\hline
+\textbf{Bits} & \textbf{Name} & \textbf{Description} \\
+\hline\hline
+0 & endpoint reached &  At least one endpoint has been addressed by the transfer. If not set, no endpoint with the given address exists in the network. \\
+1 & collision detected & Used in the (theoretical) case that two active endpoints send data at the same time. The initial transfer this reply belongs to has been lost. \\
+2 & word missing & There was a mismatch between an internal packet counter and the length transported in an EOB packet.\\
+3 & checksum mismatch & There was a mismatch between an internally generated checksum and one received with a EOB or TRM packet. \\
+4 & don't understand & The addressed endpoint does not know how to treat the incoming data. \\
+5 & buffer mismatch & The numbers of sent EOB and received ACK do not match. \\
+6 & answer missing & An endpoint connected to a hub did not send an answer. \\
+7 - 15 & t.b.d & Bits not yet used. Reserved. \\
+\hline
+\end{tabularx}
+\caption{Common Error- and Status information on all channels}
+\label{commonerrorbits}
+\end{center}
+\end{table}
+
+The bits contained in the trigger busy release packet (table \ref{LVL1Errorbits}) are usually not visible to the user.
+
+\begin{table}[hbp]
+\begin{center}
+\begin{tabularx}{\textwidth}{|c|c|C|}
+\hline
+\textbf{Bits} & \textbf{Name} & \textbf{Description} \\
+\hline\hline
+16 & trg. counter mismatch &  The internal trigger number does not match the received trigger number. \\
+17 & timing trg missing & A LVL1 trigger has been received which needs a timing trigger, but no timing trigger was seen.\\
+18 & multiple timing trg & There were two signals on the timing input but only one LVL1 trigger \\
+19 & severe front-end error & The front-end shows a severe error that requires external aid \\
+20 & buffers half full & The event data buffers are filled halfway. \\
+21 & buffers almost full & The event data buffers are almost full. \\
+22 & not configured & Frontend is not configured correctly to handle triggers, an initilization is needed. \\
+23 & frontend error & Parts of the connected frontend are not behaving correctly: no response, not synchronized, token missing... The error is either not permanent or can be handled internally\\
+24 & spike detected & A spike was detected on the timing trigger input. \\
+25 & trigger timeout & The delay between timing trigger and LVL1 trigger was longer than expected \\
+26 - 31 & t.b.d. & Not yet defined \\
+\hline
+\end{tabularx}
+\caption{Error- and Status information contained in the trigger busy release packet}
+\label{LVL1Errorbits}
+\end{center}
+\end{table}
+
+The bits contained in the data stream (table \ref{Errorbits}) are added to the data files on disk.
+
+
+\begin{table}[hbp]
+\begin{center}
+\begin{tabularx}{\textwidth}{|c|c|X|}
+\hline
+\textbf{Bits} & \textbf{Name} & \textbf{Description}\\
+\hline\hline
+16 & evt. number mismatch &  The event number in the data stream does not match the requested event number. \\
+17 & trg. code mismatch & Mismatch in upper 16bit of DHDR word. \\
+18 & wrong length & Length submitted in DHDR does not match real length. \\
+19 & answer missing & a board sent a short transfer instead of DHDR or no answer at all. \\
+20 & not found & requested event number does not match stored event number. \\
+21 & partially not found & parts of the data are missing.\\
+22 & severe problem & serious sync problem detected - intervention needed. \\
+23 & single broken event & event data corrupted, next event most likely not affected. \\
+24 & Ethernet link broken & Ethernet link to send data is down. Data has been lost. \\
+25 & SubEvent buffer full & The buffer to store events in the Ethernet interface is almost full, a stop within the next few events is likely \\
+26 & Ethernet error & The ethernet interface found partially corrupted data and discarded this event. Only partial data has been transmitted to the EB. \\
+27 & timing trigger error & There was a problem related to the timing trigger, e.g. multiple or missing timing triggers, spikes \\
+28 & &  \\
+29 & &  \\
+30 & & \\ 
+31 & & \\
+\hline
+\end{tabularx}
+\caption{Error- and Status information contained in the SubEvent}
+\label{Errorbits}
+\end{center}
+\end{table}
+
+The bits contained in slow control transfers are decoded by \verb!trbcmd! and \verb!libtrbnet!.
+
+
+