# read from SCI can be delayed due to long read strobe
MULTICYCLE FROM ASIC gen_PCSB.THE_MEDIA_PCSB/gen_SERDES.THE_SERDES/PCSD_INST PIN SCIRDATA* 15 ns;
# write strobe can be delayed due to A/D being stable after access
-MULTICYCLE TO ASIC gen_PCSB.THE_MEDIA_PCSB/gen_SERDES.THE_SERDES/PCSD_INST PIN SCIWSTN 15 ns;
+MULTICYCLE TO ASIC gen_PCSB.THE_MEDIA_PCSB/gen_SERDES.THE_SERDES/PCSD_INST PIN SCIWSTN 15 ns;
+
+# placement test for DDMTD measurement circuit (CDT)
+# 090144 (13)
+LOCATE UGROUP "gen_PCSB.THE_PHASERBOX/THE_CLOCKBOX/THE_PING_POINT/clockpoint_group" SITE "R114C55D";
+LOCATE UGROUP "gen_PCSB.THE_PHASERBOX/THE_CLOCKBOX/THE_PONG_POINT/clockpoint_group" SITE "R114C56D";
+PROHIBIT SITE "R114C55C";
+PROHIBIT SITE "R114C56C";
+
+# 081248 (13)
+#LOCATE UGROUP "gen_PCSB.THE_PHASERBOX/THE_CLOCKBOX/THE_PING_POINT/clockpoint_group" SITE "R114C55D";
+#LOCATE UGROUP "gen_PCSB.THE_PHASERBOX/THE_CLOCKBOX/THE_PONG_POINT/clockpoint_group" SITE "R114C56D";
+#PROHIBIT SITE "R114C55C";
+#PROHIBIT SITE "R114C55D";
+#PROHIBIT SITE "R114C56C";
+#PROHIBIT SITE "R114C56D";
+
+# 073114 (37)
+#LOCATE UGROUP "gen_PCSB.THE_PHASERBOX/THE_CLOCKBOX/THE_PING_POINT/clockpoint_group" SITE "R114C31D";
+#LOCATE UGROUP "gen_PCSB.THE_PHASERBOX/THE_CLOCKBOX/THE_PONG_POINT/clockpoint_group" SITE "R114C32D";
+#PROHIBIT SITE "R114C31C";
+#PROHIBIT SITE "R114C32D";
+#PROHIBIT SITE "R114C31C";
+#PROHIBIT SITE "R114C32D";
+
+# 225543 (17)
+#LOCATE UGROUP "gen_PCSB.THE_PHASERBOX/THE_CLOCKBOX/THE_PING_POINT/clockpoint_group" SITE "R74C104D";
+#LOCATE UGROUP "gen_PCSB.THE_PHASERBOX/THE_CLOCKBOX/THE_PONG_POINT/clockpoint_group" SITE "R74C105D";
+#PROHIBIT SITE "R74C104C";
+#PROHIBIT SITE "R74C105C";
+
+# 211537
+#LOCATE UGROUP "gen_PCSB.THE_PHASERBOX/THE_CLOCKBOX/THE_PING_POINT/clockpoint_group" SITE "R103C25D";
+#LOCATE UGROUP "gen_PCSB.THE_PHASERBOX/THE_CLOCKBOX/THE_PONG_POINT/clockpoint_group" SITE "R103C26D";
+#PROHIBIT SITE "R103C25C";
+#PROHIBIT SITE "R103C26C";
+
+# 203201
+#LOCATE UGROUP "gen_PCSB.THE_PHASERBOX/THE_CLOCKBOX/THE_PING_POINT/clockpoint_group" SITE "R14C157D";
+#LOCATE UGROUP "gen_PCSB.THE_PHASERBOX/THE_CLOCKBOX/THE_PONG_POINT/clockpoint_group" SITE "R14C158D";
+#PROHIBIT SITE "R14C157C";
+#PROHIBIT SITE "R14C158C";
+
+# 181730 (13)
+#LOCATE UGROUP "gen_PCSB.THE_PHASERBOX/THE_CLOCKBOX/THE_PING_POINT/clockpoint_group" SITE "R104C33D";
+#LOCATE UGROUP "gen_PCSB.THE_PHASERBOX/THE_CLOCKBOX/THE_PONG_POINT/clockpoint_group" SITE "R104C34D";
+#PROHIBIT SITE "R104C33C";
+#PROHIBIT SITE "R104C34C";
+
+# 165344 (13)
+#LOCATE UGROUP "gen_PCSB.THE_PHASERBOX/THE_CLOCKBOX/THE_PING_POINT/clockpoint_group" SITE "R114C55D";
+#LOCATE UGROUP "gen_PCSB.THE_PHASERBOX/THE_CLOCKBOX/THE_PONG_POINT/clockpoint_group" SITE "R114C56D";
+# 175344 (13)
+#PROHIBIT SITE "R114C55C";
+#PROHIBIT SITE "R114C56C";
###################################################################################################################
###################################################################################################################
signal init_quad : std_logic;
signal link_clock : std_logic;
- signal phaser_data : std_logic_vector(31 downto 0);
signal ping_i : std_logic;
- signal ping_iq : std_logic;
signal ping_q : std_logic;
signal pong_i : std_logic;
- signal pong_iq : std_logic;
signal pong_q : std_logic;
signal pong_clk_i : std_logic;
signal clk_120m : std_logic;
signal clk_sample : std_logic;
- signal ping_stretched_i : std_logic;
signal ping_stretched_q : std_logic;
- signal pong_stretched_i : std_logic;
signal pong_stretched_q : std_logic;
- signal start_ping_i : std_logic;
signal start_ping_q : std_logic;
- signal start_pong_i : std_logic;
signal start_pong_q : std_logic;
- signal fsm_active_int : std_logic;
- signal fsm_ce_int : std_logic;
- signal fsm_rst_int : std_logic;
- signal fsm_clr_done_int : std_logic;
- signal delay_value_int : std_logic_vector(9 downto 0);
- signal delay_valid_int : std_logic;
signal ack_delay : std_logic_vector(2 downto 0);
signal ack_delay_x : std_logic;
signal phaser_start : std_logic;
THE_PHASERBOX: entity phaserbox
port map(
- SAMPLE_CLK => clk_sample,
- RESET => reset_i,
+ SAMPLE_CLK => clk_sample,
+ RESET => reset_i,
-- input signals
- TX_SYNC_IN => ping_i,
- TX_CLK_IN => master_clk_i,
- RX_SYNC_IN => pong_i,
- RX_CLK_IN => pong_clk_i,
- START_DELAY_IN => tx_dlm_i,
- STOP_DELAY_IN => rx_dlm_i,
+ TX_SYNC_IN => ping_i,
+ TX_CLK_IN => master_clk_i,
+ RX_SYNC_IN => pong_i,
+ RX_CLK_IN => pong_clk_i,
+ START_DELAY_IN => tx_dlm_i,
+ STOP_DELAY_IN => rx_dlm_i,
-- histogram
- HISTO_CLK => clk_sys,
- HISTO_START_IN => phaser_start,
- HISTO_DONE_OUT => phaser_data(31),
- HISTO_ADDR_IN => busddmtd_rx.addr(9 downto 0),
- HISTO_DATA_OUT => phaser_data(17 downto 0),
+ HISTO_CLK => clk_sys,
+ HISTO_START_IN => phaser_start,
+ HISTO_DONE_OUT => open,
+ HISTO_ADDR_IN => busddmtd_rx.addr(9 downto 0),
+ HISTO_DATA_OUT => busddmtd_tx.data,
+ HISTO_READ_IN => busddmtd_rx.read,
+ HISTO_WRITE_IN => busddmtd_rx.write,
+ HISTO_ACK_OUT => busddmtd_tx.ack,
+ HISTO_NACK_OUT => busddmtd_tx.nack,
+ HISTO_UNKNOWN_OUT => busddmtd_tx.unknown,
--
- COARSE_DELAY_OUT => coarse_delay_data,
+ COARSE_DELAY_OUT => coarse_delay_data,
--
- DEBUG_OUT => debug_phaser
+ DEBUG_OUT => debug_phaser
);
-
- phaser_data(30 downto 18) <= (others => '0');
-
- -- simple readout
- THE_ACK_DELAY_PROC: process( clk_sys )
- begin
- if( rising_edge(clk_sys) ) then
- ack_delay <= ack_delay(1 downto 0) & ack_delay_x;
- end if;
- end process THE_ACK_DELAY_PROC;
-
- ack_delay_x <= busddmtd_rx.read or busddmtd_rx.write;
-
- busddmtd_tx.data <= phaser_data;
- busddmtd_tx.ack <= ack_delay(2);
- busddmtd_tx.nack <= '0';
- busddmtd_tx.unknown <= '0';
-- Output registers
THE_TX_DLM_OR: OFS1P3DX
jspc29 / trb3sc.git / commitdiff