#project files
add_file -vhdl -lib work "workdir/lattice-diamond/cae_library/synthesis/vhdl/machxo2.vhd"
add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd"
-add_file -vhdl -lib work "../base/trb3_components.vhd"
add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd"
-add_file -vhdl -lib work "../wasa/source/spi_slave.vhd"
+add_file -vhdl -lib work "../source/spi_slave.vhd"
add_file -vhdl -lib work "../../trbnet/trb_net_onewire.vhd"
add_file -vhdl -lib work "version.vhd"
-add_file -vhdl -lib work "../wasa/source/pwm.vhd"
-add_file -vhdl -lib work "../wasa/cores/pll_shifted_clocks.vhd"
-add_file -vhdl -lib work "../wasa/cores/fifo_1kx8.vhd"
-add_file -vhdl -lib work "../wasa/source/ffarray.vhd"
-
-
-add_file -vhdl -lib work "../wasa/cores/oddr16.vhd"
-add_file -vhdl -lib work "../wasa/cores/flash.vhd"
-add_file -vhdl -lib work "../wasa/cores/flashram.vhd"
-add_file -vhdl -lib work "../wasa/cores/pll.vhd"
-add_file -verilog -lib work "../wasa/cores/efb_define_def.v"
-add_file -verilog -lib work "../wasa/cores/UFM_WB.v"
+add_file -vhdl -lib work "../source/pwm.vhd"
+add_file -vhdl -lib work "../cores/pll_shifted_clocks.vhd"
+add_file -vhdl -lib work "../cores/fifo_1kx8.vhd"
+add_file -vhdl -lib work "../source/ffarray.vhd"
+
+
+add_file -vhdl -lib work "../cores/oddr16.vhd"
+add_file -vhdl -lib work "../cores/flash.vhd"
+add_file -vhdl -lib work "../cores/flashram.vhd"
+add_file -vhdl -lib work "../cores/pll.vhd"
+add_file -verilog -lib work "../cores/efb_define_def.v"
+add_file -verilog -lib work "../cores/UFM_WB.v"
add_file -vhdl -lib work "padiwa_amps.vhd"