]> jspc29.x-matter.uni-frankfurt.de Git - trb3.git/commitdiff
New front end porject for the cbmtof detector designed by Jochen Fruehauf - cu
authorCahit <c.ugur@gsi.de>
Thu, 4 Apr 2013 09:23:02 +0000 (11:23 +0200)
committerCahit <c.ugur@gsi.de>
Thu, 4 Apr 2013 09:23:02 +0000 (11:23 +0200)
base/trb3_periph_cbmtof.lpf [new file with mode: 0644]
cbmtof/cbmtof.ldf [new file with mode: 0644]
cbmtof/cbmtof.vhd [new file with mode: 0644]
cbmtof/compile_constraints.pl [new file with mode: 0755]

diff --git a/base/trb3_periph_cbmtof.lpf b/base/trb3_periph_cbmtof.lpf
new file mode 100644 (file)
index 0000000..256483b
--- /dev/null
@@ -0,0 +1,193 @@
+BLOCK RESETPATHS ;
+BLOCK ASYNCPATHS ;
+BLOCK RD_DURING_WR_PATHS ;
+
+#################################################################
+# Clock I/O
+#################################################################
+LOCATE COMP  "CLK_OSC"         SITE "U20";  #oscillator 200
+LOCATE COMP  "CLK_CM_0"                SITE "AC17"; #CM0
+LOCATE COMP  "CLK_CM_1"                SITE "P21";  #CM1
+LOCATE COMP  "CLK_CM_2"                SITE "N23";  #CM2
+LOCATE COMP  "CLK_CM_3"                SITE "N5";   #CM3
+LOCATE COMP  "CLK_CM_4"                SITE "T21";  #CM4
+LOCATE COMP  "CLK_CM_6"                SITE "U6";   #CM6
+LOCATE COMP  "CLK_CM_7"                SITE "Y26";  #CM7
+LOCATE COMP  "CLK_CM_8"                SITE "V17";  #CM8
+LOCATE COMP  "CLK_CM_9"                SITE "V20";  #CM9
+LOCATE COMP  "CLK_EXT"         SITE "C14";  #external
+
+DEFINE PORT GROUP "CLK_group" "CLK_*" ;
+IOBUF GROUP "CLK_group" IO_TYPE=LVDS25 DIFFRESISTOR=100;
+
+
+#################################################################
+# Clock Manager
+#################################################################
+LOCATE COMP  "CLK_MNGR_USER_0"   SITE "M23";
+LOCATE COMP  "CLK_MNGR_USER_1"   SITE "M24";
+LOCATE COMP  "CLK_MNGR_USER_2"   SITE "L24";
+LOCATE COMP  "CLK_MNGR_USER_3"   SITE "K25";
+DEFINE PORT GROUP "CLK_MNGR_group" "CLK_MNGR*" ;
+IOBUF GROUP "CLK_MNGR_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=8;
+
+
+#################################################################
+# DAC & SPI
+#################################################################
+LOCATE COMP  "OR_IN"   SITE "B2";
+IOBUF  PORT  "OR_IN" IO_TYPE=LVCMOS25 PULLMODE=NONE;
+
+LOCATE COMP  "DAC_SCK" SITE "K8";
+LOCATE COMP  "DAC_CS"  SITE "H6";
+LOCATE COMP  "DAC_SDI" SITE "J4";
+LOCATE COMP  "DAC_SDO" SITE "L5";
+LOCATE COMP  "DAC_CLR" SITE "C3";
+
+DEFINE PORT GROUP "DAC_group" "DAC*";
+IOBUF GROUP "DAC_group" IO_TYPE=LVDS25 DIFFRESISTOR=100;
+
+LOCATE COMP  "FLASH_CLK"  SITE "V24";
+LOCATE COMP  "FLASH_CS"   SITE "T25";
+LOCATE COMP  "FLASH_DIN"  SITE "T24";
+LOCATE COMP  "FLASH_DOUT" SITE "V21";
+
+DEFINE PORT GROUP "FLASH_group" "FLASH*" ;
+IOBUF GROUP "FLASH_group" IO_TYPE=LVCMOS25 PULLMODE=NONE;
+
+LOCATE COMP  "PROGRAMN"   SITE "A20";
+IOBUF  PORT "PROGRAMN" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8  ;
+
+
+#################################################################
+# LED
+#################################################################
+
+LOCATE COMP  "LED_CLK_GREEN"    SITE "P23";
+LOCATE COMP  "LED_CLK_RED"      SITE "R22";
+LOCATE COMP  "LED_GREEN"        SITE "K24";
+LOCATE COMP  "LED_ORANGE"       SITE "J24";
+LOCATE COMP  "LED_RED"          SITE "J26";
+LOCATE COMP  "LED_YELLOW"       SITE "K26";
+LOCATE COMP  "LED_SFP_GREEN"    SITE "W17";
+LOCATE COMP  "LED_SFP_RED"      SITE "AB23";
+
+DEFINE PORT GROUP "LED_group" "LED*" ;
+IOBUF GROUP "LED_group" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8;
+
+
+#################################################################
+# INPUT
+#################################################################
+LOCATE COMP  "INPUT_1"   SITE "AD3";
+LOCATE COMP  "INPUT_2"   SITE "AE4";
+LOCATE COMP  "INPUT_3"   SITE "AD4";
+LOCATE COMP  "INPUT_4"   SITE "AD1";
+LOCATE COMP  "INPUT_5"   SITE "AC2";
+LOCATE COMP  "INPUT_6"   SITE "AB3";
+LOCATE COMP  "INPUT_7"   SITE "AA1";
+LOCATE COMP  "INPUT_8"   SITE "AA3";
+LOCATE COMP  "INPUT_9"   SITE "V3";
+LOCATE COMP  "INPUT_10"    SITE "U4";
+LOCATE COMP  "INPUT_11"    SITE "T7";
+LOCATE COMP  "INPUT_12"    SITE "G5";
+LOCATE COMP  "INPUT_13"    SITE "K2";
+LOCATE COMP  "INPUT_14"    SITE "H4";
+LOCATE COMP  "INPUT_15"    SITE "G2";
+LOCATE COMP  "INPUT_16"    SITE "E1";
+LOCATE COMP  "INPUT_17"    SITE "D1";
+LOCATE COMP  "INPUT_18"    SITE "C2";
+LOCATE COMP  "INPUT_19"    SITE "F2";
+LOCATE COMP  "INPUT_20"    SITE "D4";
+LOCATE COMP  "INPUT_21"    SITE "V10";
+LOCATE COMP  "INPUT_22"    SITE "W8";
+LOCATE COMP  "INPUT_23"    SITE "AE2";
+LOCATE COMP  "INPUT_24"    SITE "AA7";
+LOCATE COMP  "INPUT_25"    SITE "Y6";
+LOCATE COMP  "INPUT_26"    SITE "AB5";
+LOCATE COMP  "INPUT_27"    SITE "Y5";
+LOCATE COMP  "INPUT_28"    SITE "Y3";
+LOCATE COMP  "INPUT_29"    SITE "W1";
+LOCATE COMP  "INPUT_30"    SITE "V6";
+LOCATE COMP  "INPUT_31"    SITE "T1";
+LOCATE COMP  "INPUT_32"    SITE "M4";
+
+DEFINE PORT GROUP "INPUT_group" "INPUT*" ;
+IOBUF GROUP "INPUT_group" IO_TYPE=LVDS25 DIFFRESISTOR=100 ;
+
+
+#################################################################
+# SFP
+#################################################################
+LOCATE COMP  "SFP_LOS"    SITE "AE23"; #this was AF23 in cbmrich
+LOCATE COMP  "SFP_TXDIS"  SITE "AD23";
+LOCATE COMP  "SFP_MOD_0"  SITE "AC23";
+LOCATE COMP  "SFP_MOD_1"  SITE "AB20";
+LOCATE COMP  "SFP_MOD_2"  SITE "AB21";
+LOCATE COMP  "SFP_RATE_SEL"  SITE "AF23"; # doesn't exist in cbmrich
+LOCATE COMP  "SFP_TXFAULT"  SITE "AB22"; # doesn't exist in cbmrich
+
+DEFINE PORT GROUP "SFP_group" "SFP*" ;
+IOBUF GROUP "SFP_group" IO_TYPE=LVCMOS25 PULLMODE=UP;
+
+
+#################################################################
+# Other I/O
+#################################################################
+LOCATE COMP  "SPARE_LINE_0"   SITE "E13";
+LOCATE COMP  "SPARE_LINE_1"   SITE "L21";
+LOCATE COMP  "SPARE_LINE_2"   SITE "P5";
+
+DEFINE PORT GROUP "SPARE_LINE_group" "SPARE_LINE*" ;
+IOBUF GROUP "SPARE_LINE_group" IO_TYPE=LVDS25 DIFFRESISTOR=100;
+
+LOCATE COMP  "LVDS_1"   SITE "J23";
+LOCATE COMP  "LVDS_2"   SITE "G26";
+DEFINE PORT GROUP "LVDS_group" "LVDS*" ;
+IOBUF GROUP "LVDS_group" IO_TYPE=LVDS25 DIFFRESISTOR=100;
+
+LOCATE COMP  "TEMPSENS"    SITE "K23";
+IOBUF PORT "TEMPSENS" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8;
+
+
+
+#################################################################
+# Test Connector
+#################################################################
+LOCATE COMP  "TEST_LINE_0"    SITE "A10";
+LOCATE COMP  "TEST_LINE_1"    SITE "C10";
+LOCATE COMP  "TEST_LINE_2"    SITE "G9";
+LOCATE COMP  "TEST_LINE_3"    SITE "E10";
+LOCATE COMP  "TEST_LINE_4"    SITE "D8";
+LOCATE COMP  "TEST_LINE_5"    SITE "A9";
+LOCATE COMP  "TEST_LINE_6"    SITE "C8";
+LOCATE COMP  "TEST_LINE_7"    SITE "C9";
+LOCATE COMP  "TEST_LINE_8"    SITE "A8";
+LOCATE COMP  "TEST_LINE_9"    SITE "B8";
+LOCATE COMP  "TEST_LINE_10"   SITE "C7";
+LOCATE COMP  "TEST_LINE_11"   SITE "C6";
+LOCATE COMP  "TEST_LINE_12"   SITE "B7";
+LOCATE COMP  "TEST_LINE_13"   SITE "B6";
+LOCATE COMP  "TEST_LINE_14"   SITE "A7";
+LOCATE COMP  "TEST_LINE_15"   SITE "A6";
+LOCATE COMP  "TEST_LINE_16"   SITE "A17";
+LOCATE COMP  "TEST_LINE_17"   SITE "A18";
+LOCATE COMP  "TEST_LINE_18"   SITE "A16";
+LOCATE COMP  "TEST_LINE_19"   SITE "C16";
+LOCATE COMP  "TEST_LINE_20"   SITE "A15";
+LOCATE COMP  "TEST_LINE_21"   SITE "C15";
+LOCATE COMP  "TEST_LINE_22"   SITE "A14";
+LOCATE COMP  "TEST_LINE_23"   SITE "C13";
+LOCATE COMP  "TEST_LINE_24"   SITE "A13";
+LOCATE COMP  "TEST_LINE_25"   SITE "B13";
+LOCATE COMP  "TEST_LINE_26"   SITE "B12";
+LOCATE COMP  "TEST_LINE_27"   SITE "C12";
+LOCATE COMP  "TEST_LINE_28"   SITE "A12";
+LOCATE COMP  "TEST_LINE_29"   SITE "C11";
+LOCATE COMP  "TEST_LINE_30"   SITE "A11";
+LOCATE COMP  "TEST_LINE_31"   SITE "B11";
+
+DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ;
+IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=8;
+
+
diff --git a/cbmtof/cbmtof.ldf b/cbmtof/cbmtof.ldf
new file mode 100644 (file)
index 0000000..a6d33e7
--- /dev/null
@@ -0,0 +1,309 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<BaliProject version="2.0" title="cbmtof" device="LFE3-150EA-8FN672C" default_implementation="cbmtof">
+    <Options/>
+    <Implementation title="cbmtof" dir="cbmtof" description="cbmtof" default_strategy="Strategy1">
+        <Options/>
+        <Options/>
+        <Source name="../version.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../../trbnet/trb_net_std.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../../trbnet/trb_net_components.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../base/trb3_components.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../../trbnet/trb_net16_term_buf.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../../trbnet/trb_net_CRC.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../../trbnet/trb_net_CRC8.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../../trbnet/trb_net_onewire.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../../trbnet/basics/rom_16x8.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../../trbnet/basics/ram.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../../trbnet/basics/pulse_sync.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../../trbnet/basics/state_sync.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../../trbnet/basics/ram_16x8_dp.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../../trbnet/basics/ram_16x16_dp.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../../trbnet/trb_net16_addresses.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../../trbnet/basics/ram_dp.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../../trbnet/trb_net16_term.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../../trbnet/trb_net_sbuf.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../../trbnet/trb_net_sbuf5.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../../trbnet/trb_net_sbuf6.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../../trbnet/trb_net16_sbuf.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../../trbnet/trb_net16_regIO.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../../trbnet/trb_net16_regio_bus_handler.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../../trbnet/trb_net_priority_encoder.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../../trbnet/trb_net_dummy_fifo.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../../trbnet/trb_net16_dummy_fifo.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../../trbnet/trb_net16_term_ibuf.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../../trbnet/trb_net_priority_arbiter.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../../trbnet/trb_net_pattern_gen.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../../trbnet/trb_net16_obuf_nodata.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../../trbnet/trb_net16_obuf.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../../trbnet/trb_net16_ibuf.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../../trbnet/trb_net16_api_base.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../../trbnet/trb_net16_iobuf.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../../trbnet/trb_net16_io_multiplexer.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../../trbnet/trb_net16_trigger.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../../trbnet/trb_net16_ipudata.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../../trbnet/trb_net16_endpoint_hades_full.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../../trbnet/basics/signal_sync.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../../trbnet/basics/ram_dp_rw.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../../trbnet/basics/pulse_stretch.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../../trbnet/special/handler_lvl1.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../../trbnet/special/handler_data.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../../trbnet/special/handler_ipu.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../../trbnet/special/handler_trigger_and_data.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../../trbnet/special/trb_net_reset_handler.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../../trbnet/trb_net16_endpoint_hades_full_handler.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../../trbnet/special/fpga_reboot.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../../trbnet/special/spi_ltc2600.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x1k.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../../trbnet/lattice/ecp3/trb_net16_fifo_arch.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16bit_dualport.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../../trbnet/lattice/ecp3/trb_net_fifo_16bit_bram_dualport.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../../trbnet/lattice/ecp3/fifo/fifo_36x256_oreg.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../../trbnet/lattice/ecp3/fifo/fifo_36x512_oreg.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../../trbnet/lattice/ecp3/fifo/fifo_36x1k_oreg.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../../trbnet/lattice/ecp3/fifo/fifo_36x2k_oreg.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../../trbnet/lattice/ecp3/fifo/fifo_36x4k_oreg.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../../trbnet/lattice/ecp3/fifo/fifo_36x8k_oreg.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../../trbnet/lattice/ecp3/fifo/fifo_36x16k_oreg.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../../trbnet/lattice/ecp3/fifo/fifo_36x32k_oreg.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../../trbnet/lattice/ecp3/fifo/fifo_18x256_oreg.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../../trbnet/lattice/ecp3/fifo/fifo_18x512_oreg.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../../trbnet/lattice/ecp3/fifo/fifo_18x1k_oreg.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../../trbnet/lattice/ecp3/fifo/fifo_18x2k_oreg.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../../trbnet/lattice/ecp3/fifo/fifo_19x16_obuf.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16x16_dualport.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../../trbnet/lattice/ecp3/spi_dpram_32_to_8.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../../trbnet/special/spi_slim.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../../trbnet/special/spi_master.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../../trbnet/special/spi_databus_memory.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../../trbnet/optical_link/f_divider.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../../trbnet/media_interfaces/ecp3_sfp/sfp_1_200_int.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../base/cores/pll_in200_out100.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../trb3_periph_padiwa.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../tdc_releases/tdc_v1.3/Adder_304.vhd" type="VHDL" type_short="VHDL" excluded="TRUE">
+            <Options/>
+        </Source>
+        <Source name="../../tdc_releases/tdc_v1.3/bit_sync.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../tdc_releases/tdc_v1.3/BusHandler.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../tdc_releases/tdc_v1.3/Channel_200.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../tdc_releases/tdc_v1.3/Channel.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../tdc_releases/tdc_v1.3/Encoder_304_Bit.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../tdc_releases/tdc_v1.3/fallingEdgeDetect.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../tdc_releases/tdc_v1.3/FIFO_36x128_OutReg_Counter.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../tdc_releases/tdc_v1.3/LogicAnalyser.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../tdc_releases/tdc_v1.3/Readout.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../tdc_releases/tdc_v1.3/Reference_Channel_200.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../tdc_releases/tdc_v1.3/Reference_Channel.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../tdc_releases/tdc_v1.3/risingEdgeDetect.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../tdc_releases/tdc_v1.3/ROM_encoder_3.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../tdc_releases/tdc_v1.3/ROM4_Encoder.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../tdc_releases/tdc_v1.3/ShiftRegisterSISO.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../tdc_releases/tdc_v1.3/TDC.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../tdc_releases/tdc_v1.3/trb3_periph.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../tdc_releases/tdc_v1.3/up_counter.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../workdir/cbmtof.lpf" type="Logic Preference" type_short="LPF">
+            <Options/>
+        </Source>
+    </Implementation>
+    <Strategy name="Strategy1" file="Strategy1.sty"/>
+</BaliProject>
diff --git a/cbmtof/cbmtof.vhd b/cbmtof/cbmtof.vhd
new file mode 100644 (file)
index 0000000..473c261
--- /dev/null
@@ -0,0 +1,886 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+use work.trb3_components.all;
+use work.version.all;
+
+
+
+entity cbmtof is
+  port(
+    --Clocks
+    CLK_OSC : in std_logic;                     --for tdc measurements
+    CLK_CM  : in std_logic_vector(9 downto 0);  --from clock manager
+    CLK_EXT : in std_logic;
+
+    --Serdes
+    --CLK_SERDES_INT_RIGHT : in    std_logic;
+    SERDES_TX : out   std_logic_vector(1 downto 0);
+    SERDES_RX : in    std_logic_vector(1 downto 0);
+    SFP_TXDIS : out   std_logic;
+    SFP_MOD   : inout std_logic_vector(2 downto 0);
+    SFP_LOS   : in    std_logic;
+
+    --Connections
+    SPARE_LINE : inout std_logic_vector(2 downto 0);
+    LVDS       : inout std_logic_vector(2 downto 1);
+    INPUT      : in    std_logic_vector(32 downto 1);
+    OR_IN      : in    std_logic;
+
+    --Flash ROM & Reboot
+    FLASH_CLK  : out std_logic;
+    FLASH_CS   : out std_logic;
+    FLASH_DIN  : out std_logic;
+    FLASH_DOUT : in  std_logic;
+    PROGRAMN   : out std_logic;         --reboot FPGA
+
+    --DAC
+    DAC_SDO : in  std_logic;
+    DAC_SDI : out std_logic;
+    DAC_SCK : out std_logic;
+    DAC_CS  : out std_logic;
+    DAC_CLR : out std_logic;
+
+    --Misc
+    TEMPSENS      : inout std_logic;    --Temperature Sensor
+    LED_GREEN     : out   std_logic;
+    LED_ORANGE    : out   std_logic;
+    LED_RED       : out   std_logic;
+    LED_YELLOW    : out   std_logic;
+    LED_CLK_GREEN : out   std_logic;
+    LED_CLK_RED   : out   std_logic;
+    LED_SFP_GREEN : out   std_logic;
+    LED_SFP_RED   : out   std_logic;
+
+    CLK_MNGR_USER : inout std_logic_vector(3 downto 0);
+
+    --Test Connectors
+    TEST_LINE : out std_logic_vector(31 downto 0)
+    );
+
+
+  attribute syn_useioff                  : boolean;
+  --no IO-FF for LEDs relaxes timing constraints
+  attribute syn_useioff of LED_GREEN     : signal is false;
+  attribute syn_useioff of LED_ORANGE    : signal is false;
+  attribute syn_useioff of LED_RED       : signal is false;
+  attribute syn_useioff of LED_YELLOW    : signal is false;
+  attribute syn_useioff of LED_CLK_GREEN : signal is false;
+  attribute syn_useioff of LED_CLK_RED   : signal is false;
+  attribute syn_useioff of LED_SFP_RED   : signal is false;
+  attribute syn_useioff of LED_SFP_GREEN : signal is false;
+  attribute syn_useioff of TEMPSENS      : signal is false;
+  attribute syn_useioff of PROGRAMN      : signal is false;
+  attribute syn_useioff of INPUT         : signal is false;
+
+  --important signals _with_ IO-FF
+  attribute syn_useioff of DAC_SCK    : signal is true;
+  attribute syn_useioff of DAC_CS     : signal is true;
+  attribute syn_useioff of DAC_SDI    : signal is true;
+  attribute syn_useioff of DAC_SDO    : signal is true;
+  attribute syn_useioff of DAC_CLR    : signal is true;
+  attribute syn_useioff of FLASH_CLK  : signal is true;
+  attribute syn_useioff of FLASH_CS   : signal is true;
+  attribute syn_useioff of FLASH_DIN  : signal is true;
+  attribute syn_useioff of FLASH_DOUT : signal is true;
+  attribute syn_useioff of TEST_LINE  : signal is true;
+  attribute syn_useioff of SPARE_LINE : signal is true;
+  attribute syn_useioff of LVDS       : signal is true;
+  attribute syn_useioff of OR_IN      : signal is true;
+
+end entity;
+
+architecture cbmtof_arch of cbmtof is
+  --Constants
+  constant REGIO_NUM_STAT_REGS : integer := 5;
+  constant REGIO_NUM_CTRL_REGS : integer := 3;
+
+  attribute syn_keep     : boolean;
+  attribute syn_preserve : boolean;
+
+  --Clock / Reset
+  signal clk_100_i                : std_logic;  --clock for main logic, 100 MHz, via Clock Manager and internal PLL
+  signal clk_200_i                : std_logic;  --clock for logic at 200 MHz, via Clock Manager and bypassed PLL
+  signal pll_lock                 : std_logic;  --Internal PLL locked. E.g. used to reset all internal logic.
+  signal clear_i                  : std_logic;
+  signal reset_i                  : std_logic;
+  signal GSR_N                    : std_logic;
+  attribute syn_keep of GSR_N     : signal is true;
+  attribute syn_preserve of GSR_N : signal is true;
+
+  --Media Interface
+  signal med_stat_op        : std_logic_vector (1*16-1 downto 0);
+  signal med_ctrl_op        : std_logic_vector (1*16-1 downto 0);
+  signal med_stat_debug     : std_logic_vector (1*64-1 downto 0);
+  signal med_ctrl_debug     : std_logic_vector (1*64-1 downto 0);
+  signal med_data_out       : std_logic_vector (1*16-1 downto 0);
+  signal med_packet_num_out : std_logic_vector (1*3-1 downto 0);
+  signal med_dataready_out  : std_logic;
+  signal med_read_out       : std_logic;
+  signal med_data_in        : std_logic_vector (1*16-1 downto 0);
+  signal med_packet_num_in  : std_logic_vector (1*3-1 downto 0);
+  signal med_dataready_in   : std_logic;
+  signal med_read_in        : std_logic;
+
+  --LVL1 channel
+  signal timing_trg_received_i  : std_logic;
+  signal trg_data_valid_i       : std_logic;
+  signal trg_timing_valid_i     : std_logic;
+  signal trg_notiming_valid_i   : std_logic;
+  signal trg_invalid_i          : std_logic;
+  signal trg_type_i             : std_logic_vector(3 downto 0);
+  signal trg_number_i           : std_logic_vector(15 downto 0);
+  signal trg_code_i             : std_logic_vector(7 downto 0);
+  signal trg_information_i      : std_logic_vector(23 downto 0);
+  signal trg_int_number_i       : std_logic_vector(15 downto 0);
+  signal trg_multiple_trg_i     : std_logic;
+  signal trg_timeout_detected_i : std_logic;
+  signal trg_spurious_trg_i     : std_logic;
+  signal trg_missing_tmg_trg_i  : std_logic;
+  signal trg_spike_detected_i   : std_logic;
+
+  --Data channel
+  signal fee_trg_release_i    : std_logic;
+  signal fee_trg_statusbits_i : std_logic_vector(31 downto 0);
+  signal fee_data_i           : std_logic_vector(31 downto 0);
+  signal fee_data_write_i     : std_logic;
+  signal fee_data_finished_i  : std_logic;
+  signal fee_almost_full_i    : std_logic;
+
+  --Slow Control channel
+  signal common_stat_reg        : std_logic_vector(std_COMSTATREG*32-1 downto 0);
+  signal common_ctrl_reg        : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
+  signal stat_reg               : std_logic_vector(32*2**REGIO_NUM_STAT_REGS-1 downto 0);
+  signal ctrl_reg               : std_logic_vector(32*2**REGIO_NUM_CTRL_REGS-1 downto 0);
+  signal common_stat_reg_strobe : std_logic_vector(std_COMSTATREG-1 downto 0);
+  signal common_ctrl_reg_strobe : std_logic_vector(std_COMCTRLREG-1 downto 0);
+  signal stat_reg_strobe        : std_logic_vector(2**REGIO_NUM_STAT_REGS-1 downto 0);
+  signal ctrl_reg_strobe        : std_logic_vector(2**REGIO_NUM_CTRL_REGS-1 downto 0);
+
+  --RegIO
+  signal my_address             : std_logic_vector (15 downto 0);
+  signal regio_addr_out         : std_logic_vector (15 downto 0);
+  signal regio_read_enable_out  : std_logic;
+  signal regio_write_enable_out : std_logic;
+  signal regio_data_out         : std_logic_vector (31 downto 0);
+  signal regio_data_in          : std_logic_vector (31 downto 0);
+  signal regio_dataready_in     : std_logic;
+  signal regio_no_more_data_in  : std_logic;
+  signal regio_write_ack_in     : std_logic;
+  signal regio_unknown_addr_in  : std_logic;
+  signal regio_timeout_out      : std_logic;
+
+  --Timer
+  signal global_time         : std_logic_vector(31 downto 0);
+  signal local_time          : std_logic_vector(7 downto 0);
+  signal time_since_last_trg : std_logic_vector(31 downto 0);
+  signal timer_ticks         : std_logic_vector(1 downto 0);
+
+  --Flash
+  signal spictrl_read_en  : std_logic;
+  signal spictrl_write_en : std_logic;
+  signal spictrl_data_in  : std_logic_vector(31 downto 0);
+  signal spictrl_addr     : std_logic;
+  signal spictrl_data_out : std_logic_vector(31 downto 0);
+  signal spictrl_ack      : std_logic;
+  signal spictrl_busy     : std_logic;
+  signal spimem_read_en   : std_logic;
+  signal spimem_write_en  : std_logic;
+  signal spimem_data_in   : std_logic_vector(31 downto 0);
+  signal spimem_addr      : std_logic_vector(5 downto 0);
+  signal spimem_data_out  : std_logic_vector(31 downto 0);
+  signal spimem_ack       : std_logic;
+
+  signal dac_read_en  : std_logic;
+  signal dac_write_en : std_logic;
+  signal dac_data_in  : std_logic_vector(31 downto 0);
+  signal dac_addr     : std_logic_vector(4 downto 0);
+  signal dac_data_out : std_logic_vector(31 downto 0);
+  signal dac_ack      : std_logic;
+  signal dac_busy     : std_logic;
+
+  signal hitreg_read_en    : std_logic;
+  signal hitreg_write_en   : std_logic;
+  signal hitreg_data_in    : std_logic_vector(31 downto 0);
+  signal hitreg_addr       : std_logic_vector(6 downto 0);
+  signal hitreg_data_out   : std_logic_vector(31 downto 0);
+  signal hitreg_data_ready : std_logic;
+  signal hitreg_invalid    : std_logic;
+
+  signal srb_read_en    : std_logic;
+  signal srb_write_en   : std_logic;
+  signal srb_data_in    : std_logic_vector(31 downto 0);
+  signal srb_addr       : std_logic_vector(6 downto 0);
+  signal srb_data_out   : std_logic_vector(31 downto 0);
+  signal srb_data_ready : std_logic;
+  signal srb_invalid    : std_logic;
+
+  signal lhb_read_en    : std_logic;
+  signal lhb_write_en   : std_logic;
+  signal lhb_data_in    : std_logic_vector(31 downto 0);
+  signal lhb_addr       : std_logic_vector(6 downto 0);
+  signal lhb_data_out   : std_logic_vector(31 downto 0);
+  signal lhb_data_ready : std_logic;
+  signal lhb_invalid    : std_logic;
+
+  signal esb_read_en    : std_logic;
+  signal esb_write_en   : std_logic;
+  signal esb_data_in    : std_logic_vector(31 downto 0);
+  signal esb_addr       : std_logic_vector(6 downto 0);
+  signal esb_data_out   : std_logic_vector(31 downto 0);
+  signal esb_data_ready : std_logic;
+  signal esb_invalid    : std_logic;
+
+  signal efb_read_en    : std_logic;
+  signal efb_write_en   : std_logic;
+  signal efb_addr       : std_logic_vector(6 downto 0);
+  signal efb_data_out   : std_logic_vector(31 downto 0);
+  signal efb_data_ready : std_logic;
+  signal efb_invalid    : std_logic;
+
+  signal tdc_ctrl_read      : std_logic;
+  signal last_tdc_ctrl_read : std_logic;
+  signal tdc_ctrl_write     : std_logic;
+  signal tdc_ctrl_addr      : std_logic_vector(1 downto 0);
+  signal tdc_ctrl_data_in   : std_logic_vector(31 downto 0);
+  signal tdc_ctrl_data_out  : std_logic_vector(31 downto 0);
+  signal tdc_ctrl_reg       : std_logic_vector(5*32-1 downto 0);
+
+  signal spi_bram_addr : std_logic_vector(7 downto 0);
+  signal spi_bram_wr_d : std_logic_vector(7 downto 0);
+  signal spi_bram_rd_d : std_logic_vector(7 downto 0);
+  signal spi_bram_we   : std_logic;
+
+
+  --FPGA Test
+  signal time_counter : unsigned(31 downto 0);
+
+  --TDC
+  signal hit_in_i         : std_logic_vector(64 downto 1);
+  signal logic_analyser_i : std_logic_vector(15 downto 0);
+  
+begin
+---------------------------------------------------------------------------
+-- Reset Generation
+---------------------------------------------------------------------------
+
+  GSR_N <= pll_lock;
+
+  THE_RESET_HANDLER : trb_net_reset_handler
+    generic map(
+      RESET_DELAY => x"FEEE"
+      )
+    port map(
+      CLEAR_IN      => '0',              -- reset input (high active, async)
+      CLEAR_N_IN    => '1',              -- reset input (low active, async)
+      CLK_IN        => clk_200_i,        -- raw master clock, NOT from PLL/DLL!
+      SYSCLK_IN     => clk_100_i,        -- PLL/DLL remastered clock
+      PLL_LOCKED_IN => pll_lock,         -- master PLL lock signal (async)
+      RESET_IN      => '0',              -- general reset signal (SYSCLK)
+      TRB_RESET_IN  => med_stat_op(13),  -- TRBnet reset signal (SYSCLK)
+      CLEAR_OUT     => clear_i,          -- async reset out, USE WITH CARE!
+      RESET_OUT     => reset_i,          -- synchronous reset out (SYSCLK)
+      DEBUG_OUT     => open
+      );  
+
+
+---------------------------------------------------------------------------
+-- Clock Handling
+---------------------------------------------------------------------------
+
+  THE_MAIN_PLL : pll_in200_out100
+    port map(
+      CLK   => CLK_CM(0),
+      CLKOP => clk_100_i,
+      CLKOK => clk_200_i,
+      LOCK  => pll_lock
+      );
+
+
+---------------------------------------------------------------------------
+-- The TrbNet media interface (to other FPGA)
+---------------------------------------------------------------------------
+  THE_MEDIA_UPLINK : trb_net16_med_ecp3_sfp
+    generic map(
+      SERDES_NUM  => 0,                 --number of serdes in quad
+      EXT_CLOCK   => c_NO,              --use internal clock
+      USE_200_MHZ => c_YES,             --run on 200 MHz clock
+      USE_CTC     => c_YES              --CTC required
+      )
+    port map(
+      CLK                => clk_200_i,
+      SYSCLK             => clk_100_i,
+      RESET              => reset_i,
+      CLEAR              => clear_i,
+      CLK_EN             => '1',
+      --Internal Connection
+      MED_DATA_IN        => med_data_out,
+      MED_PACKET_NUM_IN  => med_packet_num_out,
+      MED_DATAREADY_IN   => med_dataready_out,
+      MED_READ_OUT       => med_read_in,
+      MED_DATA_OUT       => med_data_in,
+      MED_PACKET_NUM_OUT => med_packet_num_in,
+      MED_DATAREADY_OUT  => med_dataready_in,
+      MED_READ_IN        => med_read_out,
+      REFCLK2CORE_OUT    => open,
+      --SFP Connection
+      SD_RXD_P_IN        => SERDES_RX(0),
+      SD_RXD_N_IN        => SERDES_RX(1),
+      SD_TXD_P_OUT       => SERDES_TX(0),
+      SD_TXD_N_OUT       => SERDES_TX(1),
+      SD_REFCLK_P_IN     => open,
+      SD_REFCLK_N_IN     => open,
+      SD_PRSNT_N_IN      => SFP_MOD(0),
+      SD_LOS_IN          => SFP_LOS,
+      SD_TXDIS_OUT       => SFP_TXDIS,
+      -- Status and control port
+      STAT_OP            => med_stat_op,
+      CTRL_OP            => med_ctrl_op,
+      STAT_DEBUG         => med_stat_debug,
+      CTRL_DEBUG         => (others => '0')
+      );
+
+---------------------------------------------------------------------------
+-- Endpoint
+---------------------------------------------------------------------------
+  THE_ENDPOINT : trb_net16_endpoint_hades_full_handler
+    generic map(
+      REGIO_NUM_STAT_REGS       => REGIO_NUM_STAT_REGS,  --4,    --16 stat reg
+      REGIO_NUM_CTRL_REGS       => REGIO_NUM_CTRL_REGS,  --3,    --8 cotrol reg
+      ADDRESS_MASK              => x"FFFF",
+      BROADCAST_BITMASK         => x"FF",
+      BROADCAST_SPECIAL_ADDR    => x"50",
+      REGIO_COMPILE_TIME        => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32)),
+      REGIO_HARDWARE_VERSION    => x"92000000",
+      REGIO_INIT_ADDRESS        => x"f300",
+      REGIO_USE_VAR_ENDPOINT_ID => c_YES,
+      CLOCK_FREQUENCY           => 100,
+      TIMING_TRIGGER_RAW        => c_YES,
+      --Configure data handler
+      DATA_INTERFACE_NUMBER     => 1,
+      DATA_BUFFER_DEPTH         => 13,  --13
+      DATA_BUFFER_WIDTH         => 32,
+      DATA_BUFFER_FULL_THRESH   => 2**13-800,
+      TRG_RELEASE_AFTER_DATA    => c_YES,
+      HEADER_BUFFER_DEPTH       => 9,
+      HEADER_BUFFER_FULL_THRESH => 2**9-16
+      )
+    port map(
+      CLK                => clk_100_i,
+      RESET              => reset_i,
+      CLK_EN             => '1',
+      MED_DATAREADY_OUT  => med_dataready_out,  -- open, --
+      MED_DATA_OUT       => med_data_out,  -- open, --
+      MED_PACKET_NUM_OUT => med_packet_num_out,  -- open, --
+      MED_READ_IN        => med_read_in,
+      MED_DATAREADY_IN   => med_dataready_in,
+      MED_DATA_IN        => med_data_in,
+      MED_PACKET_NUM_IN  => med_packet_num_in,
+      MED_READ_OUT       => med_read_out,  -- open, --
+      MED_STAT_OP_IN     => med_stat_op,
+      MED_CTRL_OP_OUT    => med_ctrl_op,
+
+      --Timing trigger in
+      TRG_TIMING_TRG_RECEIVED_IN  => timing_trg_received_i,
+      --LVL1 trigger to FEE
+      LVL1_TRG_DATA_VALID_OUT     => trg_data_valid_i,
+      LVL1_VALID_TIMING_TRG_OUT   => trg_timing_valid_i,
+      LVL1_VALID_NOTIMING_TRG_OUT => trg_notiming_valid_i,
+      LVL1_INVALID_TRG_OUT        => trg_invalid_i,
+
+      LVL1_TRG_TYPE_OUT        => trg_type_i,
+      LVL1_TRG_NUMBER_OUT      => trg_number_i,
+      LVL1_TRG_CODE_OUT        => trg_code_i,
+      LVL1_TRG_INFORMATION_OUT => trg_information_i,
+      LVL1_INT_TRG_NUMBER_OUT  => trg_int_number_i,
+
+      --Information about trigger handler errors
+      TRG_MULTIPLE_TRG_OUT     => trg_multiple_trg_i,
+      TRG_TIMEOUT_DETECTED_OUT => trg_timeout_detected_i,
+      TRG_SPURIOUS_TRG_OUT     => trg_spurious_trg_i,
+      TRG_MISSING_TMG_TRG_OUT  => trg_missing_tmg_trg_i,
+      TRG_SPIKE_DETECTED_OUT   => trg_spike_detected_i,
+
+      --Response from FEE
+      FEE_TRG_RELEASE_IN(0)       => fee_trg_release_i,
+      FEE_TRG_STATUSBITS_IN       => fee_trg_statusbits_i,
+      FEE_DATA_IN                 => fee_data_i,
+      FEE_DATA_WRITE_IN(0)        => fee_data_write_i,
+      FEE_DATA_FINISHED_IN(0)     => fee_data_finished_i,
+      FEE_DATA_ALMOST_FULL_OUT(0) => fee_almost_full_i,
+
+      -- Slow Control Data Port
+      REGIO_COMMON_STAT_REG_IN     => common_stat_reg,  --0x00
+      REGIO_COMMON_CTRL_REG_OUT    => common_ctrl_reg,  --0x20
+      REGIO_COMMON_STAT_STROBE_OUT => common_stat_reg_strobe,
+      REGIO_COMMON_CTRL_STROBE_OUT => common_ctrl_reg_strobe,
+      REGIO_STAT_REG_IN            => stat_reg,         --start 0x80
+      REGIO_CTRL_REG_OUT           => ctrl_reg,         --start 0xc0
+      REGIO_STAT_STROBE_OUT        => stat_reg_strobe,
+      REGIO_CTRL_STROBE_OUT        => ctrl_reg_strobe,
+      REGIO_VAR_ENDPOINT_ID        => (others => '0'),
+
+      BUS_ADDR_OUT         => regio_addr_out,
+      BUS_READ_ENABLE_OUT  => regio_read_enable_out,
+      BUS_WRITE_ENABLE_OUT => regio_write_enable_out,
+      BUS_DATA_OUT         => regio_data_out,
+      BUS_DATA_IN          => regio_data_in,
+      BUS_DATAREADY_IN     => regio_dataready_in,
+      BUS_NO_MORE_DATA_IN  => regio_no_more_data_in,
+      BUS_WRITE_ACK_IN     => regio_write_ack_in,
+      BUS_UNKNOWN_ADDR_IN  => regio_unknown_addr_in,
+      BUS_TIMEOUT_OUT      => regio_timeout_out,
+      ONEWIRE_INOUT        => TEMPSENS,
+      ONEWIRE_MONITOR_OUT  => open,
+
+      TIME_GLOBAL_OUT         => global_time,
+      TIME_LOCAL_OUT          => local_time,
+      TIME_SINCE_LAST_TRG_OUT => time_since_last_trg,
+      TIME_TICKS_OUT          => timer_ticks,
+
+      STAT_DEBUG_IPU              => open,
+      STAT_DEBUG_1                => open,
+      STAT_DEBUG_2                => open,
+      STAT_DEBUG_DATA_HANDLER_OUT => open,
+      STAT_DEBUG_IPU_HANDLER_OUT  => open,
+      STAT_TRIGGER_OUT            => open,
+      CTRL_MPLEX                  => (others => '0'),
+      IOBUF_CTRL_GEN              => (others => '0'),
+      STAT_ONEWIRE                => open,
+      STAT_ADDR_DEBUG             => open,
+      DEBUG_LVL1_HANDLER_OUT      => open
+      );
+
+---------------------------------------------------------------------------
+-- I/O
+---------------------------------------------------------------------------
+  timing_trg_received_i <= SPARE_LINE(0);
+
+---------------------------------------------------------------------------
+-- Bus Handler
+---------------------------------------------------------------------------
+  THE_BUS_HANDLER : trb_net16_regio_bus_handler
+    generic map(
+      PORT_NUMBER    => 7,
+      PORT_ADDRESSES => (0 => x"d000", 1 => x"d100", 2 => x"d400", 3 => x"c000", 4 => x"c100", 5 => x"c200", 6 => x"c300", 7 => x"c400", 8 => x"c800", others => x"0000"),
+      PORT_ADDR_MASK => (0 => 1, 1 => 6, 2 => 5, 3 => 7, 4 => 5, 5 => 7, 6 => 7, others => 0)
+      )
+    port map(
+      CLK   => clk_100_i,
+      RESET => reset_i,
+
+      DAT_ADDR_IN          => regio_addr_out,
+      DAT_DATA_IN          => regio_data_out,
+      DAT_DATA_OUT         => regio_data_in,
+      DAT_READ_ENABLE_IN   => regio_read_enable_out,
+      DAT_WRITE_ENABLE_IN  => regio_write_enable_out,
+      DAT_TIMEOUT_IN       => regio_timeout_out,
+      DAT_DATAREADY_OUT    => regio_dataready_in,
+      DAT_WRITE_ACK_OUT    => regio_write_ack_in,
+      DAT_NO_MORE_DATA_OUT => regio_no_more_data_in,
+      DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_in,
+
+      --Bus Handler (SPI CTRL)
+      BUS_READ_ENABLE_OUT(0)              => spictrl_read_en,
+      BUS_WRITE_ENABLE_OUT(0)             => spictrl_write_en,
+      BUS_DATA_OUT(0*32+31 downto 0*32)   => spictrl_data_in,
+      BUS_ADDR_OUT(0*16)                  => spictrl_addr,
+      BUS_ADDR_OUT(0*16+15 downto 0*16+1) => open,
+      BUS_TIMEOUT_OUT(0)                  => open,
+      BUS_DATA_IN(0*32+31 downto 0*32)    => spictrl_data_out,
+      BUS_DATAREADY_IN(0)                 => spictrl_ack,
+      BUS_WRITE_ACK_IN(0)                 => spictrl_ack,
+      BUS_NO_MORE_DATA_IN(0)              => spictrl_busy,
+      BUS_UNKNOWN_ADDR_IN(0)              => '0',
+      --Bus Handler (SPI Memory)
+      BUS_READ_ENABLE_OUT(1)              => spimem_read_en,
+      BUS_WRITE_ENABLE_OUT(1)             => spimem_write_en,
+      BUS_DATA_OUT(1*32+31 downto 1*32)   => spimem_data_in,
+      BUS_ADDR_OUT(1*16+5 downto 1*16)    => spimem_addr,
+      BUS_ADDR_OUT(1*16+15 downto 1*16+6) => open,
+      BUS_TIMEOUT_OUT(1)                  => open,
+      BUS_DATA_IN(1*32+31 downto 1*32)    => spimem_data_out,
+      BUS_DATAREADY_IN(1)                 => spimem_ack,
+      BUS_WRITE_ACK_IN(1)                 => spimem_ack,
+      BUS_NO_MORE_DATA_IN(1)              => '0',
+      BUS_UNKNOWN_ADDR_IN(1)              => '0',
+      --DAC
+      BUS_READ_ENABLE_OUT(2)              => dac_read_en,
+      BUS_WRITE_ENABLE_OUT(2)             => dac_write_en,
+      BUS_DATA_OUT(2*32+31 downto 2*32)   => dac_data_in,
+      BUS_ADDR_OUT(2*16+4 downto 2*16)    => dac_addr,
+      BUS_ADDR_OUT(2*16+15 downto 2*16+5) => open,
+      BUS_TIMEOUT_OUT(2)                  => open,
+      BUS_DATA_IN(2*32+31 downto 2*32)    => dac_data_out,
+      BUS_DATAREADY_IN(2)                 => dac_ack,
+      BUS_WRITE_ACK_IN(2)                 => dac_ack,
+      BUS_NO_MORE_DATA_IN(2)              => dac_busy,
+      BUS_UNKNOWN_ADDR_IN(2)              => '0',
+      --HitRegisters
+      BUS_READ_ENABLE_OUT(3)              => hitreg_read_en,
+      BUS_WRITE_ENABLE_OUT(3)             => hitreg_write_en,
+      BUS_DATA_OUT(3*32+31 downto 3*32)   => open,
+      BUS_ADDR_OUT(3*16+6 downto 3*16)    => hitreg_addr,
+      BUS_ADDR_OUT(3*16+15 downto 3*16+7) => open,
+      BUS_TIMEOUT_OUT(3)                  => open,
+      BUS_DATA_IN(3*32+31 downto 3*32)    => hitreg_data_out,
+      BUS_DATAREADY_IN(3)                 => hitreg_data_ready,
+      BUS_WRITE_ACK_IN(3)                 => '0',
+      BUS_NO_MORE_DATA_IN(3)              => '0',
+      BUS_UNKNOWN_ADDR_IN(3)              => hitreg_invalid,
+      --Status Registers
+      BUS_READ_ENABLE_OUT(4)              => srb_read_en,
+      BUS_WRITE_ENABLE_OUT(4)             => srb_write_en,
+      BUS_DATA_OUT(4*32+31 downto 4*32)   => open,
+      BUS_ADDR_OUT(4*16+6 downto 4*16)    => srb_addr,
+      BUS_ADDR_OUT(4*16+15 downto 4*16+7) => open,
+      BUS_TIMEOUT_OUT(4)                  => open,
+      BUS_DATA_IN(4*32+31 downto 4*32)    => srb_data_out,
+      BUS_DATAREADY_IN(4)                 => srb_data_ready,
+      BUS_WRITE_ACK_IN(4)                 => '0',
+      BUS_NO_MORE_DATA_IN(4)              => '0',
+      BUS_UNKNOWN_ADDR_IN(4)              => srb_invalid,
+      --Encoder Start Registers
+      BUS_READ_ENABLE_OUT(5)              => esb_read_en,
+      BUS_WRITE_ENABLE_OUT(5)             => esb_write_en,
+      BUS_DATA_OUT(5*32+31 downto 5*32)   => open,
+      BUS_ADDR_OUT(5*16+6 downto 5*16)    => esb_addr,
+      BUS_ADDR_OUT(5*16+15 downto 5*16+7) => open,
+      BUS_TIMEOUT_OUT(5)                  => open,
+      BUS_DATA_IN(5*32+31 downto 5*32)    => esb_data_out,
+      BUS_DATAREADY_IN(5)                 => esb_data_ready,
+      BUS_WRITE_ACK_IN(5)                 => '0',
+      BUS_NO_MORE_DATA_IN(5)              => '0',
+      BUS_UNKNOWN_ADDR_IN(5)              => esb_invalid,
+      --Fifo Write Registers
+      BUS_READ_ENABLE_OUT(6)              => efb_read_en,
+      BUS_WRITE_ENABLE_OUT(6)             => efb_write_en,
+      BUS_DATA_OUT(6*32+31 downto 6*32)   => open,
+      BUS_ADDR_OUT(6*16+6 downto 6*16)    => efb_addr,
+      BUS_ADDR_OUT(6*16+15 downto 6*16+7) => open,
+      BUS_TIMEOUT_OUT(6)                  => open,
+      BUS_DATA_IN(6*32+31 downto 6*32)    => efb_data_out,
+      BUS_DATAREADY_IN(6)                 => efb_data_ready,
+      BUS_WRITE_ACK_IN(6)                 => '0',
+      BUS_NO_MORE_DATA_IN(6)              => '0',
+      BUS_UNKNOWN_ADDR_IN(6)              => efb_invalid,
+      --Lost Hit Registers
+      BUS_READ_ENABLE_OUT(7)              => lhb_read_en,
+      BUS_WRITE_ENABLE_OUT(7)             => lhb_write_en,
+      BUS_DATA_OUT(7*32+31 downto 7*32)   => open,
+      BUS_ADDR_OUT(7*16+6 downto 7*16)    => lhb_addr,
+      BUS_ADDR_OUT(7*16+15 downto 7*16+7) => open,
+      BUS_TIMEOUT_OUT(7)                  => open,
+      BUS_DATA_IN(7*32+31 downto 7*32)    => lhb_data_out,
+      BUS_DATAREADY_IN(7)                 => lhb_data_ready,
+      BUS_WRITE_ACK_IN(7)                 => '0',
+      BUS_NO_MORE_DATA_IN(7)              => '0',
+      BUS_UNKNOWN_ADDR_IN(7)              => lhb_invalid,
+      --TDC config registers
+      BUS_READ_ENABLE_OUT(8)              => tdc_ctrl_read,
+      BUS_WRITE_ENABLE_OUT(8)             => tdc_ctrl_write,
+      BUS_DATA_OUT(8*32+31 downto 8*32)   => tdc_ctrl_data_in,
+      BUS_ADDR_OUT(8*16+1 downto 8*16)    => tdc_ctrl_addr,
+      BUS_ADDR_OUT(8*16+15 downto 8*16+2) => open,
+      BUS_TIMEOUT_OUT(8)                  => open,
+      BUS_DATA_IN(8*32+31 downto 8*32)    => tdc_ctrl_data_out,
+      BUS_DATAREADY_IN(8)                 => last_tdc_ctrl_read,
+      BUS_WRITE_ACK_IN(8)                 => tdc_ctrl_write,
+      BUS_NO_MORE_DATA_IN(8)              => '0',
+      BUS_UNKNOWN_ADDR_IN(8)              => '0',
+
+      STAT_DEBUG => open
+      );
+
+  PROC_TDC_CTRL_REG : process
+    variable pos : integer;
+  begin
+    wait until rising_edge(clk_100_i);
+    pos                := to_integer(unsigned(tdc_ctrl_addr))*32;
+    tdc_ctrl_data_out  <= tdc_ctrl_reg(pos+31 downto pos);
+    last_tdc_ctrl_read <= tdc_ctrl_read;
+    if tdc_ctrl_write = '1' then
+      tdc_ctrl_reg(pos+31 downto pos) <= tdc_ctrl_data_in;
+    end if;
+  end process;
+
+---------------------------------------------------------------------------
+-- SPI / Flash
+---------------------------------------------------------------------------
+
+  THE_SPI_MASTER : spi_master
+    port map(
+      CLK_IN         => clk_100_i,
+      RESET_IN       => reset_i,
+      -- Slave bus
+      BUS_READ_IN    => spictrl_read_en,
+      BUS_WRITE_IN   => spictrl_write_en,
+      BUS_BUSY_OUT   => spictrl_busy,
+      BUS_ACK_OUT    => spictrl_ack,
+      BUS_ADDR_IN(0) => spictrl_addr,
+      BUS_DATA_IN    => spictrl_data_in,
+      BUS_DATA_OUT   => spictrl_data_out,
+      -- SPI connections
+      SPI_CS_OUT     => FLASH_CS,
+      SPI_SDI_IN     => FLASH_DOUT,
+      SPI_SDO_OUT    => FLASH_DIN,
+      SPI_SCK_OUT    => FLASH_CLK,
+      -- BRAM for read/write data
+      BRAM_A_OUT     => spi_bram_addr,
+      BRAM_WR_D_IN   => spi_bram_wr_d,
+      BRAM_RD_D_OUT  => spi_bram_rd_d,
+      BRAM_WE_OUT    => spi_bram_we,
+      -- Status lines
+      STAT           => open
+      );
+
+-- data memory for SPI accesses
+  THE_SPI_MEMORY : spi_databus_memory
+    port map(
+      CLK_IN        => clk_100_i,
+      RESET_IN      => reset_i,
+      -- Slave bus
+      BUS_ADDR_IN   => spimem_addr,
+      BUS_READ_IN   => spimem_read_en,
+      BUS_WRITE_IN  => spimem_write_en,
+      BUS_ACK_OUT   => spimem_ack,
+      BUS_DATA_IN   => spimem_data_in,
+      BUS_DATA_OUT  => spimem_data_out,
+      -- state machine connections
+      BRAM_ADDR_IN  => spi_bram_addr,
+      BRAM_WR_D_OUT => spi_bram_wr_d,
+      BRAM_RD_D_IN  => spi_bram_rd_d,
+      BRAM_WE_IN    => spi_bram_we,
+      -- Status lines
+      STAT          => open
+      );
+
+---------------------------------------------------------------------------
+-- DAC
+---------------------------------------------------------------------------      
+  THE_DAC_SPI : spi_ltc2600
+    port map(
+      CLK_IN        => clk_100_i,
+      RESET_IN      => reset_i,
+      -- Slave bus
+      BUS_ADDR_IN   => dac_addr,
+      BUS_READ_IN   => dac_read_en,
+      BUS_WRITE_IN  => dac_write_en,
+      BUS_ACK_OUT   => dac_ack,
+      BUS_BUSY_OUT  => dac_busy,
+      BUS_DATA_IN   => dac_data_in,
+      BUS_DATA_OUT  => dac_data_out,
+      -- SPI connections
+      SPI_CS_OUT(0) => DAC_CS,
+      SPI_SDI_IN    => DAC_SDO,
+      SPI_SDO_OUT   => DAC_SDI,
+      SPI_SCK_OUT   => DAC_SCK
+      );
+
+---------------------------------------------------------------------------
+-- Reboot FPGA
+---------------------------------------------------------------------------
+  THE_FPGA_REBOOT : fpga_reboot
+    port map(
+      CLK       => clk_100_i,
+      RESET     => reset_i,
+      DO_REBOOT => common_ctrl_reg(15),
+      PROGRAMN  => PROGRAMN
+      );
+
+
+
+---------------------------------------------------------------------------
+-- LED
+---------------------------------------------------------------------------
+  LED_GREEN     <= not time_counter(24);
+  LED_ORANGE    <= not time_counter(25);
+  LED_RED       <= not time_counter(26);
+  LED_YELLOW    <= not time_counter(27);
+  LED_SFP_GREEN <= not med_stat_op(9);
+  LED_SFP_RED   <= not (med_stat_op(10) or med_stat_op(11));
+
+---------------------------------------------------------------------------
+-- Test Connector
+---------------------------------------------------------------------------    
+  TEST_LINE(15 downto 1) <= INPUT(15 downto 1);
+  TEST_LINE(0)           <= SPARE_LINE(0);
+
+
+  LVDS(1) <= or_all(INPUT);
+  LVDS(2) <= SPARE_LINE(0);
+
+---------------------------------------------------------------------------
+-- Test Circuits
+---------------------------------------------------------------------------
+  process
+  begin
+    wait until rising_edge(clk_100_i);
+    time_counter <= time_counter + 1;
+  end process;
+
+-------------------------------------------------------------------------------
+-- TDC
+-------------------------------------------------------------------------------
+  THE_TDC : TDC
+    generic map (
+      CHANNEL_NUMBER => 65,             -- Number of TDC channels
+      CONTROL_REG_NR => 5)              -- Number of control regs
+    port map (
+      RESET                 => reset_i,
+      CLK_TDC               => CLK_OSC,  -- Clock used for the time measurement
+      CLK_READOUT           => clk_100_i,   -- Clock for the readout
+      REFERENCE_TIME        => timing_trg_received_i,  -- Reference time input
+      HIT_IN                => hit_in_i(64 downto 1),  -- Channel start signals
+      TRG_WIN_PRE           => tdc_ctrl_reg(42 downto 32),  -- Pre-Trigger window width
+      TRG_WIN_POST          => tdc_ctrl_reg(58 downto 48),  -- Post-Trigger window width
+      --
+      -- Trigger signals from handler
+      TRG_DATA_VALID_IN     => trg_data_valid_i,  -- trig data valid signal from trbnet
+      VALID_TIMING_TRG_IN   => trg_timing_valid_i,  -- valid timing trigger signal from trbnet
+      VALID_NOTIMING_TRG_IN => trg_notiming_valid_i,  -- valid notiming signal from trbnet
+      INVALID_TRG_IN        => trg_invalid_i,  -- invalid trigger signal from trbnet
+      TMGTRG_TIMEOUT_IN     => trg_timeout_detected_i,  -- timing trigger timeout signal from trbnet
+      SPIKE_DETECTED_IN     => trg_spike_detected_i,
+      MULTI_TMG_TRG_IN      => trg_multiple_trg_i,
+      SPURIOUS_TRG_IN       => trg_spurious_trg_i,
+      --
+      TRG_NUMBER_IN         => trg_number_i,  -- LVL1 trigger information package
+      TRG_CODE_IN           => trg_code_i,  --
+      TRG_INFORMATION_IN    => trg_information_i,   --
+      TRG_TYPE_IN           => trg_type_i,  -- LVL1 trigger information package
+      --
+      --Response to handler
+      TRG_RELEASE_OUT       => fee_trg_release_i,   -- trigger release signal
+      TRG_STATUSBIT_OUT     => fee_trg_statusbits_i,  -- status information of the tdc
+      DATA_OUT              => fee_data_i,  -- tdc data
+      DATA_WRITE_OUT        => fee_data_write_i,  -- data valid signal
+      DATA_FINISHED_OUT     => fee_data_finished_i,  -- readout finished signal
+      --
+      --Hit Counter Bus
+      HCB_READ_EN_IN        => hitreg_read_en,    -- bus read en strobe
+      HCB_WRITE_EN_IN       => hitreg_write_en,   -- bus write en strobe
+      HCB_ADDR_IN           => hitreg_addr,   -- bus address
+      HCB_DATA_OUT          => hitreg_data_out,   -- bus data
+      HCB_DATAREADY_OUT     => hitreg_data_ready,   -- bus data ready strobe
+      HCB_UNKNOWN_ADDR_OUT  => hitreg_invalid,    -- bus invalid addr
+      --Status Registers Bus
+      SRB_READ_EN_IN        => srb_read_en,   -- bus read en strobe
+      SRB_WRITE_EN_IN       => srb_write_en,  -- bus write en strobe
+      SRB_ADDR_IN           => srb_addr,    -- bus address
+      SRB_DATA_OUT          => srb_data_out,  -- bus data
+      SRB_DATAREADY_OUT     => srb_data_ready,    -- bus data ready strobe
+      SRB_UNKNOWN_ADDR_OUT  => srb_invalid,   -- bus invalid addr
+      --Encoder Start Registers Bus
+      ESB_READ_EN_IN        => esb_read_en,   -- bus read en strobe
+      ESB_WRITE_EN_IN       => esb_write_en,  -- bus write en strobe
+      ESB_ADDR_IN           => esb_addr,    -- bus address
+      ESB_DATA_OUT          => esb_data_out,  -- bus data
+      ESB_DATAREADY_OUT     => esb_data_ready,    -- bus data ready strobe
+      ESB_UNKNOWN_ADDR_OUT  => esb_invalid,   -- bus invalid addr
+      --Fifo Write Registers Bus
+      EFB_READ_EN_IN        => efb_read_en,   -- bus read en strobe
+      EFB_WRITE_EN_IN       => efb_write_en,  -- bus write en strobe
+      EFB_ADDR_IN           => efb_addr,    -- bus address
+      EFB_DATA_OUT          => efb_data_out,  -- bus data
+      EFB_DATAREADY_OUT     => efb_data_ready,    -- bus data ready strobe
+      EFB_UNKNOWN_ADDR_OUT  => efb_invalid,   -- bus invalid addr
+      --Lost Hit Registers Bus
+      LHB_READ_EN_IN        => lhb_read_en,   -- bus read en strobe
+      LHB_WRITE_EN_IN       => lhb_write_en,  -- bus write en strobe
+      LHB_ADDR_IN           => lhb_addr,    -- bus address
+      LHB_DATA_OUT          => lhb_data_out,  -- bus data
+      LHB_DATAREADY_OUT     => lhb_data_ready,    -- bus data ready strobe
+      LHB_UNKNOWN_ADDR_OUT  => lhb_invalid,   -- bus invalid addr
+      --
+      LOGIC_ANALYSER_OUT    => logic_analyser_i,
+      CONTROL_REG_IN        => tdc_ctrl_reg);
+
+  --THE_TDC : TDC
+  --  generic map (
+  --    CHANNEL_NUMBER => 5,             -- Number of TDC channels
+  --    CONTROL_REG_NR => 5)
+  --  port map (
+  --    RESET                 => reset_i,
+  --    CLK_TDC               => CLK_OSC,  -- Clock used for the time measurement
+  --    CLK_READOUT           => clk_100_i,   -- Clock for the readout
+  --    REFERENCE_TIME        => timing_trg_received_i,  -- Reference time input
+  --    HIT_IN                => hit_in_i(4 downto 1),  -- Channel start signals
+  --    TRG_WIN_PRE           => ctrl_reg(42 downto 32),  -- Pre-Trigger window width
+  --    TRG_WIN_POST          => ctrl_reg(58 downto 48),  -- Post-Trigger window width
+  --    --
+  --    -- Trigger signals from handler
+  --    TRG_DATA_VALID_IN     => trg_data_valid_i,  -- trig data valid signal from trbnet
+  --    VALID_TIMING_TRG_IN   => trg_timing_valid_i,  -- valid timing trigger signal from trbnet
+  --    VALID_NOTIMING_TRG_IN => trg_notiming_valid_i,  -- valid notiming signal from trbnet
+  --    INVALID_TRG_IN        => trg_invalid_i,  -- invalid trigger signal from trbnet
+  --    TMGTRG_TIMEOUT_IN     => trg_timeout_detected_i,  -- timing trigger timeout signal from trbnet
+  --    SPIKE_DETECTED_IN     => trg_spike_detected_i,
+  --    MULTI_TMG_TRG_IN      => trg_multiple_trg_i,
+  --    SPURIOUS_TRG_IN       => trg_spurious_trg_i,
+  --    --
+  --    TRG_NUMBER_IN         => trg_number_i,  -- LVL1 trigger information package
+  --    TRG_CODE_IN           => trg_code_i,  --
+  --    TRG_INFORMATION_IN    => trg_information_i,   --
+  --    TRG_TYPE_IN           => trg_type_i,  -- LVL1 trigger information package
+  --    --
+  --    --Response to handler
+  --    TRG_RELEASE_OUT       => fee_trg_release_i,   -- trigger release signal
+  --    TRG_STATUSBIT_OUT     => fee_trg_statusbits_i,  -- status information of the tdc
+  --    DATA_OUT              => fee_data_i,  -- tdc data
+  --    DATA_WRITE_OUT        => fee_data_write_i,  -- data valid signal
+  --    DATA_FINISHED_OUT     => fee_data_finished_i,  -- readout finished signal
+  --    --
+  --    --Hit Counter Bus
+  --    HCB_READ_EN_IN        => hitreg_read_en,    -- bus read en strobe
+  --    HCB_WRITE_EN_IN       => hitreg_write_en,   -- bus write en strobe
+  --    HCB_ADDR_IN           => hitreg_addr,   -- bus address
+  --    HCB_DATA_OUT          => hitreg_data_out,   -- bus data
+  --    HCB_DATAREADY_OUT     => hitreg_data_ready,   -- bus data ready strobe
+  --    HCB_UNKNOWN_ADDR_OUT  => hitreg_invalid,    -- bus invalid addr
+  --    --Status Registers Bus
+  --    SRB_READ_EN_IN        => srb_read_en,   -- bus read en strobe
+  --    SRB_WRITE_EN_IN       => srb_write_en,  -- bus write en strobe
+  --    SRB_ADDR_IN           => srb_addr,    -- bus address
+  --    SRB_DATA_OUT          => srb_data_out,  -- bus data
+  --    SRB_DATAREADY_OUT     => srb_data_ready,    -- bus data ready strobe
+  --    SRB_UNKNOWN_ADDR_OUT  => srb_invalid,   -- bus invalid addr
+  --    --Encoder Start Registers Bus
+  --    ESB_READ_EN_IN        => esb_read_en,   -- bus read en strobe
+  --    ESB_WRITE_EN_IN       => esb_write_en,  -- bus write en strobe
+  --    ESB_ADDR_IN           => esb_addr,    -- bus address
+  --    ESB_DATA_OUT          => esb_data_out,  -- bus data
+  --    ESB_DATAREADY_OUT     => esb_data_ready,    -- bus data ready strobe
+  --    ESB_UNKNOWN_ADDR_OUT  => esb_invalid,   -- bus invalid addr
+  --    --Fifo Write Registers Bus
+  --    EFB_READ_EN_IN        => efb_read_en,   -- bus read en strobe
+  --    EFB_WRITE_EN_IN       => efb_write_en,  -- bus write en strobe
+  --    EFB_ADDR_IN           => efb_addr,    -- bus address
+  --    EFB_DATA_OUT          => efb_data_out,  -- bus data
+  --    EFB_DATAREADY_OUT     => efb_data_ready,    -- bus data ready strobe
+  --    EFB_UNKNOWN_ADDR_OUT  => efb_invalid,   -- bus invalid addr
+  --    --Lost Hit Registers Bus
+  --    LHB_READ_EN_IN        => '0',  -- lhb_read_en,   -- bus read en strobe
+  --    LHB_WRITE_EN_IN       => '0',  -- lhb_write_en,  -- bus write en strobe
+  --    LHB_ADDR_IN           => (others => '0'),  -- lhb_addr,    -- bus address
+  --    LHB_DATA_OUT          => open,  -- lhb_data_out,  -- bus data
+  --    LHB_DATAREADY_OUT     => open,  -- lhb_data_ready,    -- bus data ready strobe
+  --    LHB_UNKNOWN_ADDR_OUT  => open,  -- lhb_invalid,   -- bus invalid addr
+  --    --
+  --    LOGIC_ANALYSER_OUT    => open,    --TEST_LINE,
+  --    CONTROL_REG_IN        => ctrl_reg);
+
+
+--  hit_in_i <= INPUT;
+
+  -- to detect rising & falling edges
+  Gen_Hit_In_Signals : for i in 1 to 32 generate
+    hit_in_i(i*2-1) <= INPUT(i);
+    hit_in_i(i*2)   <= not INPUT(i);
+  end generate Gen_Hit_In_Signals;
+
+end architecture;
diff --git a/cbmtof/compile_constraints.pl b/cbmtof/compile_constraints.pl
new file mode 100755 (executable)
index 0000000..a86e782
--- /dev/null
@@ -0,0 +1,13 @@
+#!/usr/bin/perl
+use Data::Dumper;
+use warnings;
+use strict;
+
+my $TOPNAME                      = "cbmtof";  #Name of top-level entity
+
+
+#create full lpf file
+system("cp ../base/trb3_periph_cbmtof.lpf workdir/$TOPNAME.lpf");
+system("cat ../tdc_releases/tdc_v1.3/trbnet_constraints.lpf >> workdir/$TOPNAME.lpf");
+system("cat ../tdc_releases/tdc_v1.3/tdc_constraints.lpf >> workdir/$TOPNAME.lpf");
+