add_file -vhdl -lib "work" "currentRelease/Encoder_304_Bit.vhd"
add_file -vhdl -lib "work" "currentRelease/LogicAnalyser.vhd"
add_file -vhdl -lib "work" "currentRelease/Readout.vhd"
-add_file -vhdl -lib "work" "currentRelease/ROM4_Encoder.vhd"
+#add_file -vhdl -lib "work" "currentRelease/ROM4_Encoder.vhd"
add_file -vhdl -lib "work" "currentRelease/ROM_encoder_3.vhd"
add_file -vhdl -lib "work" "currentRelease/ShiftRegisterSISO.vhd"
add_file -vhdl -lib "work" "currentRelease/TDC.vhd"
add_file -vhdl -lib "work" "currentRelease/up_counter.vhd"
add_file -vhdl -lib "work" "currentRelease/fallingEdgeDetect.vhd"
add_file -vhdl -lib "work" "currentRelease/risingEdgeDetect.vhd"
-add_file -vhdl -lib "work" "currentRelease/hit_inv.vhd"
+add_file -vhdl -lib "work" "currentRelease/hit_mux.vhd"
add_file -vhdl -lib "work" "../base/cores/FIFO_36x128_OutReg.vhd"
add_file -vhdl -lib "work" "../base/cores/FIFO_DC_36x128_OutReg.vhd"
add_file -vhdl -lib "work" "../base/code/input_to_trigger_logic.vhd"
+
add_file -vhdl -lib "work" "trb3_periph_padiwa.vhd"