signal trig_out : std_logic_vector(3 downto 0);
signal trig_din : std_logic_vector(31 downto 0);
signal trig_dout : std_logic_vector(31 downto 0);
- signal trig_write : std_logic := '0';
- signal trig_read : std_logic := '0';
- signal trig_ack : std_logic := '0';
- signal trig_nack : std_logic := '0';
+ signal trig_write : std_logic := '0';
+ signal trig_read : std_logic := '0';
+ signal trig_ack : std_logic := '0';
+ signal trig_nack : std_logic := '0';
signal trig_addr : std_logic_vector(15 downto 0) := (others => '0');
-
+
--TDC
signal hit_in_i : std_logic_vector(64 downto 1);
signal logic_analyser_i : std_logic_vector(15 downto 0);
TIMING_TRIGGER_RAW => c_YES,
--Configure data handler
DATA_INTERFACE_NUMBER => 1,
- DATA_BUFFER_DEPTH => 13, --13
+ DATA_BUFFER_DEPTH => 13, --13
DATA_BUFFER_WIDTH => 32,
- DATA_BUFFER_FULL_THRESH => 2**13-800, --2**13-(maximal 2**12)
+ DATA_BUFFER_FULL_THRESH => 2**13-800, --2**13-(maximal 2**12)
TRG_RELEASE_AFTER_DATA => c_YES,
HEADER_BUFFER_DEPTH => 9,
HEADER_BUFFER_FULL_THRESH => 2**9-16
BUS_WRITE_ACK_IN(9) => trig_ack,
BUS_NO_MORE_DATA_IN(9) => '0',
BUS_UNKNOWN_ADDR_IN(9) => trig_nack,
- STAT_DEBUG => open
+ STAT_DEBUG => open
);
PROC_TDC_CTRL_REG : process
-------------------------------------------------------------------------------
-- SPI
-------------------------------------------------------------------------------
-gen_SPI : if INCLUDE_SPI = 1 generate
- DAC_SPI : spi_ltc2600
- generic map (
- BITS => 14,
- WAITCYCLES => 100)
- port map (
- CLK_IN => clk_100_i,
- RESET_IN => reset_i,
- -- Slave bus
- BUS_READ_IN => spidac_read_en,
- BUS_WRITE_IN => spidac_write_en,
- BUS_BUSY_OUT => spidac_busy,
- BUS_ACK_OUT => spidac_ack,
- BUS_ADDR_IN => spidac_addr,
- BUS_DATA_IN => spidac_data_in,
- BUS_DATA_OUT => spidac_data_out,
- -- SPI connections
- SPI_CS_OUT(0) => DAC_OUT_CS,
- SPI_SDI_IN => DAC_IN_SDI,
- SPI_SDO_OUT => DAC_OUT_SDO,
- SPI_SCK_OUT => DAC_OUT_SCK,
- SPI_CLR_OUT(0) => DAC_OUT_CLR
- );
-end generate;
+ gen_SPI : if INCLUDE_SPI = 1 generate
+ DAC_SPI : spi_ltc2600
+ generic map (
+ BITS => 14,
+ WAITCYCLES => 100)
+ port map (
+ CLK_IN => clk_100_i,
+ RESET_IN => reset_i,
+ -- Slave bus
+ BUS_READ_IN => spidac_read_en,
+ BUS_WRITE_IN => spidac_write_en,
+ BUS_BUSY_OUT => spidac_busy,
+ BUS_ACK_OUT => spidac_ack,
+ BUS_ADDR_IN => spidac_addr,
+ BUS_DATA_IN => spidac_data_in,
+ BUS_DATA_OUT => spidac_data_out,
+ -- SPI connections
+ SPI_CS_OUT(0) => DAC_OUT_CS,
+ SPI_SDI_IN => DAC_IN_SDI,
+ SPI_SDO_OUT => DAC_OUT_SDO,
+ SPI_SCK_OUT => DAC_OUT_SCK,
+ SPI_CLR_OUT(0) => DAC_OUT_CLR
+ );
+ end generate;
-gen_NO_SPI : if INCLUDE_SPI = 0 generate
- DAC_OUT_SDO <= trig_out(0);
- DAC_OUT_SCK <= trig_out(1);
- DAC_OUT_CS <= trig_out(2);
- DAC_OUT_CLR <= trig_out(3);
-end generate;
+ gen_NO_SPI : if INCLUDE_SPI = 0 generate
+ DAC_OUT_SDO <= trig_out(0);
+ DAC_OUT_SCK <= trig_out(1);
+ DAC_OUT_CS <= trig_out(2);
+ DAC_OUT_CLR <= trig_out(3);
+ end generate;
---------------------------------------------------------------------------
-- Trigger logic
---------------------------------------------------------------------------
-gen_TRIGGER_LOGIC : if INCLUDE_TRIGGER_LOGIC = 1 generate
- THE_TRIG_LOGIC : input_to_trigger_logic
- generic map(
- INPUTS => 24,
- OUTPUTS => 4
- )
- port map(
- CLK => clk_100_i,
-
- INPUT => INP(24 downto 1),
- OUTPUT => trig_out,
-
- DATA_IN => trig_din,
- DATA_OUT => trig_dout,
- WRITE_IN => trig_write,
- READ_IN => trig_read,
- ACK_OUT => trig_ack,
- NACK_OUT => trig_nack,
- ADDR_IN => trig_addr
- );
-end generate;
+ gen_TRIGGER_LOGIC : if INCLUDE_TRIGGER_LOGIC = 1 generate
+ THE_TRIG_LOGIC : input_to_trigger_logic
+ generic map(
+ INPUTS => 24,
+ OUTPUTS => 4
+ )
+ port map(
+ CLK => clk_100_i,
+
+ INPUT => INP(24 downto 1),
+ OUTPUT => trig_out,
+
+ DATA_IN => trig_din,
+ DATA_OUT => trig_dout,
+ WRITE_IN => trig_write,
+ READ_IN => trig_read,
+ ACK_OUT => trig_ack,
+ NACK_OUT => trig_nack,
+ ADDR_IN => trig_addr
+ );
+ end generate;
---------------------------------------------------------------------------
-- Reboot FPGA
THE_TDC : TDC
generic map (
- CHANNEL_NUMBER => NUM_TDC_CHANNELS, -- Number of TDC channels
- STATUS_REG_NR => 20, -- Number of status regs
- CONTROL_REG_NR => 6, -- Number of control regs - higher than 8 check tdc_ctrl_addr
- TDC_VERSION => x"160", -- TDC version number
+ CHANNEL_NUMBER => NUM_TDC_CHANNELS, -- Number of TDC channels
+ STATUS_REG_NR => 20, -- Number of status regs
+ CONTROL_REG_NR => 6, -- Number of control regs - higher than 8 check tdc_ctrl_addr
+ TDC_VERSION => x"160", -- TDC version number
DEBUG => c_YES,
SIMULATION => c_NO)
port map (
CONTROL_REG_IN => tdc_ctrl_reg);
-- For single edge measurements
- gen_single : if USE_DOUBLE_EDGE = 0 generate
- hit_in_i <= INP;
+ gen_single : if USE_DOUBLE_EDGE = 0 generate
+ hit_in_i <= INP;
-- hit_in_i <= (others => timing_trg_received_i);
end generate;
-- For ToT Measurements
- gen_double : if USE_DOUBLE_EDGE = 1 generate
+ gen_double : if USE_DOUBLE_EDGE = 1 generate
Gen_Hit_In_Signals : for i in 1 to 32 generate
hit_in_i(i*2-1) <= INP(i-1);
hit_in_i(i*2) <= not INP(i-1);
end if;
end process CalibrationSwitch;
- -- Reference channel
- --The_Reference_Channel : Reference_Channel
- -- generic map (
- -- CHANNEL_ID => 0)
- -- port map (
- -- RESET_200 => reset_tdc,
- -- RESET_100 => reset_rdo,
- -- CLK_200 => CLK_TDC,
- -- CLK_100 => CLK_READOUT,
- -- HIT_IN => REFERENCE_TIME,
- -- READ_EN_IN => rd_en_i(0),
- -- VALID_TMG_TRG_IN => VALID_TIMING_TRG_IN,
- -- SPIKE_DETECTED_IN => SPIKE_DETECTED_IN,
- -- MULTI_TMG_TRG_IN => MULTI_TMG_TRG_IN,
- -- FIFO_DATA_OUT => open, --ch_data_i(0),
- -- FIFO_WCNT_OUT => open, --ch_wcnt_i(0),
- -- FIFO_EMPTY_OUT => open, --ch_empty_i(0),
- -- FIFO_FULL_OUT => open, --ch_full_i(0),
- -- FIFO_ALMOST_FULL_OUT => ch_almost_full_i(0),
- -- COARSE_COUNTER_IN => coarse_cntr(1),
- -- EPOCH_COUNTER_IN => epoch_cntr,
- -- TRIGGER_WINDOW_END_IN => trg_win_end_i,
- -- DATA_FINISHED_IN => data_finished_i,
- -- RUN_MODE => run_mode_i,
- -- TRIGGER_TIME_STAMP_OUT => open, -- not used after tdc_v1.5.2 --trg_time_i,
- -- REF_DEBUG_OUT => ref_debug_i);
- --ch_data_i(0) <= x"F00000000";
- --ch_data_valid_i(0) <= '0';
- --ch_empty_i(0) <= '1';
- --ch_full_i(0) <= '0';
- --ch_almost_empty_i(0) <= '0';
- --ch_almost_full_i(0) <= '0';
-
+ -- Reference Channel to measure the reference time
ReferenceChannel : Channel
generic map (
CHANNEL_ID => 0,
RESET_COUNTERS => reset_counters_i,
CLK_200 => CLK_TDC,
CLK_100 => CLK_READOUT,
- HIT_IN => hit_in_i(0), --REFERENCE_TIME,
+ HIT_IN => hit_in_i(0),
TRIGGER_WIN_END_TDC => trig_win_end_tdc,
TRIGGER_WIN_END_RDO => trig_win_end_rdo,
EPOCH_COUNTER_IN => epoch_cntr,
Channel_200_DEBUG => ch_200_debug_i(0),
Channel_DEBUG => ch_debug_i(0));
+ -- TDC Channels
GEN_Channels : for i in 1 to CHANNEL_NUMBER-1 generate
Channels : Channel
generic map (
-- status_registers_bus_i(21) <= ch_200_debug_i(0);
- TheLostHitBus : BusHandler
- generic map (
- BUS_LENGTH => CHANNEL_NUMBER-1)
- port map (
- RESET => reset_rdo,
- CLK => CLK_READOUT,
- DATA_IN => ch_lost_hit_bus_i,
- READ_EN_IN => LHB_READ_EN_IN,
- WRITE_EN_IN => LHB_WRITE_EN_IN,
- ADDR_IN => LHB_ADDR_IN,
- DATA_OUT => LHB_DATA_OUT,
- DATAREADY_OUT => LHB_DATAREADY_OUT,
- UNKNOWN_ADDR_OUT => LHB_UNKNOWN_ADDR_OUT);
-
- GenLostHitNumber : for i in 1 to CHANNEL_NUMBER-1 generate
- ch_lost_hit_bus_i(i) <= ch_encoder_start_number_i(i)(15 downto 0) & ch_200_debug_i(i)(15 downto 0) when rising_edge(CLK_READOUT);
- end generate GenLostHitNumber;
+ --TheLostHitBus : BusHandler
+ -- generic map (
+ -- BUS_LENGTH => CHANNEL_NUMBER-1)
+ -- port map (
+ -- RESET => reset_rdo,
+ -- CLK => CLK_READOUT,
+ -- DATA_IN => ch_lost_hit_bus_i,
+ -- READ_EN_IN => LHB_READ_EN_IN,
+ -- WRITE_EN_IN => LHB_WRITE_EN_IN,
+ -- ADDR_IN => LHB_ADDR_IN,
+ -- DATA_OUT => LHB_DATA_OUT,
+ -- DATAREADY_OUT => LHB_DATAREADY_OUT,
+ -- UNKNOWN_ADDR_OUT => LHB_UNKNOWN_ADDR_OUT);
+
+ --GenLostHitNumber : for i in 1 to CHANNEL_NUMBER-1 generate
+ -- ch_lost_hit_bus_i(i) <= ch_encoder_start_number_i(i)(15 downto 0) & ch_200_debug_i(i)(15 downto 0) when rising_edge(CLK_READOUT);
+ --end generate GenLostHitNumber;
+
+ LHB_DATA_OUT <= (others => '0');
+ LHB_DATAREADY_OUT <= '0';
+ LHB_UNKNOWN_ADDR_OUT <= '0';
--TheEncoderStartBus : BusHandler
-- generic map (
ESB_DATAREADY_OUT <= '0';
ESB_UNKNOWN_ADDR_OUT <= '0';
- TheEncoderFinishedBus : BusHandler
- generic map (
- BUS_LENGTH => CHANNEL_NUMBER-1)
- port map (
- RESET => reset_rdo,
- CLK => CLK_READOUT,
- DATA_IN => ch_encoder_finished_bus_i,
- READ_EN_IN => EFB_READ_EN_IN,
- WRITE_EN_IN => EFB_WRITE_EN_IN,
- ADDR_IN => EFB_ADDR_IN,
- DATA_OUT => EFB_DATA_OUT,
- DATAREADY_OUT => EFB_DATAREADY_OUT,
- UNKNOWN_ADDR_OUT => EFB_UNKNOWN_ADDR_OUT);
-
- GenFifoWriteNumber : for i in 1 to CHANNEL_NUMBER-1 generate
- --ch_encoder_finished_bus_i(i) <= x"00" & ch_encoder_finished_number_i(i) when rising_edge(CLK_READOUT);
- ch_encoder_finished_bus_i(i) <= ch_fifo_write_number_i(i)(15 downto 0)& ch_encoder_finished_number_i(i)(15 downto 0) when rising_edge(CLK_READOUT);
- end generate GenFifoWriteNumber;
-
- --EFB_DATA_OUT <= (others => '0');
- --EFB_DATAREADY_OUT <= '0';
- --EFB_UNKNOWN_ADDR_OUT <= '0';
+ --TheEncoderFinishedBus : BusHandler
+ -- generic map (
+ -- BUS_LENGTH => CHANNEL_NUMBER-1)
+ -- port map (
+ -- RESET => reset_rdo,
+ -- CLK => CLK_READOUT,
+ -- DATA_IN => ch_encoder_finished_bus_i,
+ -- READ_EN_IN => EFB_READ_EN_IN,
+ -- WRITE_EN_IN => EFB_WRITE_EN_IN,
+ -- ADDR_IN => EFB_ADDR_IN,
+ -- DATA_OUT => EFB_DATA_OUT,
+ -- DATAREADY_OUT => EFB_DATAREADY_OUT,
+ -- UNKNOWN_ADDR_OUT => EFB_UNKNOWN_ADDR_OUT);
+
+ --GenFifoWriteNumber : for i in 1 to CHANNEL_NUMBER-1 generate
+ -- --ch_encoder_finished_bus_i(i) <= x"00" & ch_encoder_finished_number_i(i) when rising_edge(CLK_READOUT);
+ -- ch_encoder_finished_bus_i(i) <= ch_fifo_write_number_i(i)(15 downto 0)& ch_encoder_finished_number_i(i)(15 downto 0) when rising_edge(CLK_READOUT);
+ --end generate GenFifoWriteNumber;
+
+ EFB_DATA_OUT <= (others => '0');
+ EFB_DATAREADY_OUT <= '0';
+ EFB_UNKNOWN_ADDR_OUT <= '0';
-- Logic Analyser
TheLogicAnalyser : LogicAnalyser
jspc29 / trb3.git / commitdiff