add external reset to clock handler

diff --git a/gbe_trb_ecp5/base/clock_reset_handler.vhd b/gbe_trb_ecp5/base/clock_reset_handler.vhd
index ea801cbca307392054fee1388f9c5cccca3315d4..593b8feb3e4a0e4beb562d8db6655f63eeea81a3 100644 (file)
--- a/gbe_trb_ecp5/base/clock_reset_handler.vhd
+++ b/gbe_trb_ecp5/base/clock_reset_handler.vhd
@@ -12,6 +12,7 @@ entity clock_reset_handler is
   port (
     CLOCK_IN        : in  std_logic;  -- oscillator
     GLOBAL_RESET_IN : in  std_logic;
+    RESET_FROM_NET  : in  std_logic := '0'; -- reset via gbe
 
     RESET_OUT       : out std_logic;
     CLEAR_OUT       : out std_logic;
@@ -102,7 +103,7 @@ THE_RESET_HANDLER : trb_net_reset_handler
     SYSCLK_IN       => sys_clk_i,       -- PLL/DLL remastered clock
     PLL_LOCKED_IN   => pll_lock,        -- master PLL lock signal (async)
     RESET_IN        => '0',             -- general reset signal (SYSCLK)
-    TRB_RESET_IN    => '0',             -- TRBnet reset signal (SYSCLK)
+    TRB_RESET_IN    => RESET_FROM_NET,  -- TRBnet reset signal (SYSCLK)
     CLEAR_OUT       => CLEAR_OUT,       -- async reset out, USE WITH CARE!
     RESET_OUT       => reset_i,         -- synchronous reset out (SYSCLK)
     DEBUG_OUT       => debug_reset_handler