signal dl_rx_frame_req : std_logic_vector(0 downto 0);
signal dl_rx_frame_ack : std_logic_vector(0 downto 0);
signal dl_rx_frame_avail : std_logic_vector(0 downto 0);
- signal dl_tx_fifofull : std_logic_vector(0 downto 0);
+-- signal dl_tx_fifofull : std_logic_vector(0 downto 0);
-- 10: frame_start
-- 9 : fifo_wr
signal scatter_cycle_done : std_logic;
signal gather_cycle_done : std_logic;
+ signal sniffer_data : std_logic_vector(7 downto 0);
+ signal sniffer_wr : std_logic;
+ signal sniffer_eof : std_logic;
+ signal sniffer_error : std_logic;
+
begin
---------------------------------------------------------------------------
SD_PRSNT_N_IN => SFP_MOD_0,
SD_LOS_IN => SFP_LOS,
SD_TXDIS_OUT => SFP_TX_DIS,
+ -- internal sniffer port
+ MAC_RX_DATA_OUT => sniffer_data,
+ MAC_RX_WRITE_OUT => sniffer_wr,
+ MAC_RX_EOF_OUT => sniffer_eof,
+ MAC_RX_ERROR_OUT => sniffer_error,
-- Status
PCS_AN_READY_OUT => pcs_an_ready,
LINK_ACTIVE_OUT => link_active,
CLK => clk_sys,
RESET => reset_i,
--
- FIFO_FULL_IN(0 downto 0) => dl_tx_fifofull(0 downto 0),
+-- FIFO_FULL_IN(0 downto 0) => dl_tx_fifofull(0 downto 0),
FIFO_FULL_OUT => ul_rx_fifofull,
FRAME_AVAIL_IN => ul_rx_frame_avail,
FRAME_REQ_OUT => ul_rx_frame_req,
FRAME_ACK_OUT => dl_rx_frame_ack(0),
FRAME_AVAIL_OUT => dl_rx_frame_avail(0),
FRAME_START_OUT => dl_rx_data(0)(10),
- -- FIFO interface TX
- FIFO_FULL_OUT => dl_tx_fifofull(0),
- FIFO_WR_IN => ul_rx_data(9),
- FIFO_DATA_IN => ul_rx_data(8 downto 0),
- FRAME_START_IN => ul_rx_data(10),
+ -- FIFO interface RX (receive frames)
+ MAC_RX_DATA_IN => sniffer_data,
+ MAC_RX_WRITE_IN => sniffer_wr,
+ MAC_RX_EOF_IN => sniffer_eof,
+ MAC_RX_ERROR_IN => sniffer_error,
+-- -- FIFO interface TX
+-- FIFO_FULL_OUT => dl_tx_fifofull(0),
+-- FIFO_WR_IN => ul_rx_data(9),
+-- FIFO_DATA_IN => ul_rx_data(8 downto 0),
+-- FRAME_START_IN => ul_rx_data(10),
--
- PCS_AN_READY_IN => link_active, --pcs_an_ready,
+ PCS_AN_READY_IN => link_active,
LINK_ACTIVE_IN => link_active,
--
-- unique adresses