add packet number

diff --git a/optical_link/flexi_PCS_channel_synch.vhd b/optical_link/flexi_PCS_channel_synch.vhd
index 67f6e6d03d30b45de01ba80d50e97d4156405489..5ac9b4cab655dfc85ada17a44f66dea698079fa0 100644 (file)
--- a/optical_link/flexi_PCS_channel_synch.vhd
+++ b/optical_link/flexi_PCS_channel_synch.vhd
@@ -24,7 +24,8 @@ entity flexi_PCS_channel_synch is
     TX_FORCE_DISP    : out std_logic_vector(1 downto 0);
     DATA_VALID_IN    : in  std_logic;
     DATA_VALID_OUT   : out std_logic;
-    FLEXI_PCS_STATUS : out std_logic_vector(15 downto 0)
+    FLEXI_PCS_STATUS : out std_logic_vector(15 downto 0);
+    MED_PACKET_NUM_OUT : out std_logic_vector(1 downto 0)
     );
 
 end flexi_PCS_channel_synch;
@@ -78,8 +79,19 @@ architecture flexi_PCS_channel_synch of flexi_PCS_channel_synch is
   signal fifo_almost_full : std_logic;
   signal fifo_empty : std_logic;
   signal fifo_almost_empty : std_logic;
-  
+  signal packet_number : std_logic_vector(1 downto 0);
 begin
+  PACKET_NUM: process (CLK, RESET)
+  begin
+    if rising_edge(CLK) then 
+      if RESET = '1' then  
+        packet_number <= "00";
+      elsif RX_K(1) then
+        packet_number <= packet_number + 1;
+      end if;
+    end if;
+  end process PACKET_NUM;
+  MED_PACKET_NUM_OUT <= packet_number;
   TX_FORCE_DISP(0) <= '0';
   SYNCH_PROCESS : process (CLK)
   begin
@@ -204,7 +216,7 @@ begin
         end if;
       when NORMAL_OPERATION =>
         fifo_rst <= '0';
-        fifo_wr_en <= '1';
+        fifo_wr_en <= '1';              
         fifo_rd_en <= '1';
         fsm_debug_register(2 downto 0) <= "100";
         rx_rst_i       <= '0';

diff --git a/optical_link/flexi_PCS_synch.vhd b/optical_link/flexi_PCS_synch.vhd
index b938db466014c0d67bb7abc10dd222242074b0c9..529b6522ab2b83d81c4ac740150f7cbf795133ed 100644 (file)
--- a/optical_link/flexi_PCS_synch.vhd
+++ b/optical_link/flexi_PCS_synch.vhd
@@ -49,7 +49,8 @@ architecture flexi_PCS_synch of flexi_PCS_synch is
       TX_FORCE_DISP    : out std_logic_vector(1 downto 0);
       DATA_VALID_IN    : in  std_logic;
       DATA_VALID_OUT   : out std_logic;
-      FLEXI_PCS_STATUS : out std_logic_vector(15 downto 0));
+      FLEXI_PCS_STATUS : out std_logic_vector(15 downto 0)
+      );
   end component;
 begin
   CHANNEL_GENERATE : for bit_index in 0 to HOW_MANY_CHANNELS-1 generate
@@ -71,8 +72,8 @@ begin
           TX_FORCE_DISP    => TX_FORCE_DISP(bit_index*2+1 downto bit_index*2),
           DATA_VALID_IN    => MED_DATAREADY_IN(bit_index),
           DATA_VALID_OUT   => MED_DATAREADY_OUT(bit_index),
-          FLEXI_PCS_STATUS => FLEXI_PCS_SYNCH_STATUS((bit_index*16+15) downto bit_index*16)
+          FLEXI_PCS_STATUS => FLEXI_PCS_SYNCH_STATUS((bit_index*16+15) downto bit_index*16),
+          MED_PACKET_NUM_OUT => MED_PACKET_NUM_OUT((bit_index*2+1) downto bit_index*2)
           );
   end generate CHANNEL_GENERATE;
-  
 end flexi_PCS_synch;