-------------------------------------------------
-- Serdes
-------------------------------------------------
- gen_pcs3: if SERDES_NUM = 3 generate -- needed for LPF constraints, should be changed
+-- include this for certain designs (placement!)
+-- gen_pcs3: if SERDES_NUM = 3 generate -- needed for LPF constraints, should be changed
THE_SERDES : entity work.serdes_sync_all_RS
port map(
hdinp_ch0 => hdinp(0),
serdes_rst_qd_c => '0', -- was wrong
tx_sync_qd_c => SYNC_TX_PLL_IN
);
- end generate;
+-- end generate;
gen_control : for i in 0 to 3 generate
gen_used_control : if (IS_MODE(i) = c_IS_SLAVE) or (IS_MODE(i) = c_IS_MASTER) generate
STAT_DEBUG(7 downto 4) <= clk_tx_full(3 downto 0);
STAT_DEBUG(63 downto 8) <= (others => '0');
--- DEBUG_OUT <= debug_i(3*32+31 downto 3*32);
- DEBUG_OUT(11 downto 0) <= debug_i(3*32+11 downto 3*32);
- DEBUG_OUT(12) <= debug_tx_control_i(3*32+4);
- DEBUG_OUT(13) <= debug_tx_control_i(3*32+5);
- DEBUG_OUT(14) <= debug_tx_control_i(3*32+30);
- DEBUG_OUT(15) <= debug_tx_control_i(3*32+31);
- DEBUG_OUT(31 downto 16) <= debug_i(3*32+31 downto 3*32+16);
+ DEBUG_OUT <= debug_i(3*32+31 downto 3*32);
+-- DEBUG_OUT(11 downto 0) <= debug_i(3*32+11 downto 3*32);
+-- DEBUG_OUT(12) <= debug_i(3*32+12); --debug_tx_control_i(3*32+4);
+-- DEBUG_OUT(13) <= debug_i(3*32+13); --debug_tx_control_i(3*32+5);
+-- DEBUG_OUT(14) <= debug_i(3*32+14); --debug_tx_control_i(3*32+30);
+-- DEBUG_OUT(15) <= debug_i(3*32+15); --debug_tx_control_i(3*32+31);
+-- DEBUG_OUT(31 downto 16) <= debug_i(3*32+31 downto 3*32+16);
end architecture;
signal NEXT_STATE : statetype; -- next state of lsm\r
\r
signal tx_pcs_rst_ch_c_int : std_logic;\r
- signal rst_qd_c_int : std_logic;\r
signal sync_tx_quad_int : std_logic;\r
signal link_tx_ready_int : std_logic;\r
signal sync_tx_quad_trans : std_logic;\r
STATE_OUT <= x"3";\r
tx_pcs_rst_ch_c_int <= '1';\r
reset_timer <= '1';\r
+ sync_tx_quad_int <= '1';\r
NEXT_STATE <= SYNC_DONE;\r
\r
when SYNC_DONE =>\r
signal reset_i : std_logic;
signal link_rx_ready_i : std_logic;
- signal link_rx_ready_qsys : std_logic;
signal link_half_done_i : std_logic;
signal link_full_done_i : std_logic;
signal is_wap_zero_i : std_logic;
signal debug_tx_control_i : std_logic_vector(31 downto 0);
+ signal rx_lsm_state : std_logic_vector(3 downto 0);
+
+ signal link_rx_ready_qsys : std_logic;
+ signal link_tx_ready_qsys : std_logic;
+ signal link_status : std_logic_vector(3 downto 0);
+ signal link_status_qsys : std_logic_vector(3 downto 0);
+
+-- attribute syn_keep : boolean;
+-- attribute syn_preserve : boolean;
+-- attribute syn_keep of rx_lsm_state : signal is true;
+-- attribute syn_preserve of rx_lsm_state : signal is true;
+-- attribute syn_keep of link_half_done_i : signal is true;
+-- attribute syn_preserve of link_half_done_i : signal is true;
+-- attribute syn_keep of link_full_done_i : signal is true;
+-- attribute syn_preserve of link_full_done_i : signal is true;
+-- attribute syn_keep of word_sync_rx_i : signal is true;
+-- attribute syn_preserve of word_sync_rx_i : signal is true;
+-- attribute syn_keep of word_sync_tx_i : signal is true;
+-- attribute syn_preserve of word_sync_tx_i : signal is true;
begin
CLK_RXI => CLK_RXI,
CLK_SYS => CLK_SYS,
RESET => reset_i,
-
+ --
RX_DATA_OUT => media_med2int_i.data,
RX_PACKET_NUMBER_OUT => media_med2int_i.packet_num,
RX_WRITE_OUT => media_med2int_i.dataready,
-
+ --
RX_DATA_IN => RX_DATA_IN,
RX_K_IN => RX_K_IN,
-
+ --
WORD_SYNC_OUT => word_sync_rx_i,
-
+ --
RX_DLM_OUT => RX_DLM_OUT,
RX_DLM_WORD_OUT => RX_DLM_WORD_OUT,
-
+ --
RX_RST_OUT => RX_RST_OUT,
RX_RST_WORD_OUT => RX_RST_WORD_OUT,
-
+ --
LINK_RX_READY_IN => link_rx_ready_i,
LINK_TX_READY_IN => LINK_TX_READY_IN,
LINK_HALF_DONE_IN => link_half_done_i,
LINK_FULL_DONE_IN => link_full_done_i,
-
+ --
DEBUG_OUT => DEBUG_RX_CONTROL,
STAT_REG_OUT => STAT_RX_CONTROL
);
RX_DATA_IN => RX_DATA_IN,
LINK_HALF_DONE_OUT => link_half_done_i,
LINK_FULL_DONE_OUT => link_full_done_i,
- STATE_OUT => open
+ STATE_OUT => rx_lsm_state --open
);
-- clocks for media interface
- media_med2int_i.clk_half <= CLK_RXHALF;
- media_med2int_i.clk_full <= CLK_RXI;
+ media_med2int_i.clk_half <= CLK_RXHALF; -- goes to clock and reset handler
+ media_med2int_i.clk_full <= CLK_RXI; -- goes to clock and reset handler
-------------------------------------------------
-- TX Data
media_med2int_i.stat_op(11) <= led_tx;
media_med2int_i.stat_op(10) <= led_rx or last_led_rx;
media_med2int_i.stat_op(9) <= '0'; --led_ok
- media_med2int_i.stat_op(8 downto 5) <= (others => '0');
--- media_med2int_i.stat_op(5) <= link_tx_ready_i;
- media_med2int_i.stat_op(4) <= link_rx_ready_i;
- media_med2int_i.stat_op(3 downto 0) <= x"0" when link_half_done_i = '1' and link_full_done_i = '1'
- else x"7";
+ media_med2int_i.stat_op(8 downto 6) <= (others => '0');
+ media_med2int_i.stat_op(5) <= link_tx_ready_qsys;
+ media_med2int_i.stat_op(4) <= link_rx_ready_qsys;
+ media_med2int_i.stat_op(3 downto 0) <= link_status_qsys;
+
+ link_status <= x"0" when ((link_half_done_i = '1') and (link_full_done_i = '1'))
+ else x"7";
+
+ SYNC_MEDIA_SIGS : entity work.signal_sync
+ generic map(
+ WIDTH => 6,
+ DEPTH => 3
+ )
+ port map(
+ RESET => '0',
+ CLK0 => CLK_SYS,
+ CLK1 => CLK_SYS,
+ D_IN(5) => LINK_TX_READY_IN,
+ D_IN(4) => link_rx_ready_i,
+ D_IN(3 downto 0) => link_status,
+ D_OUT(5) => link_tx_ready_qsys,
+ D_OUT(4) => link_rx_ready_qsys,
+ D_OUT(3 downto 0) => link_status_qsys
+ );
-- TEST_LINE signals
- DEBUG_OUT(3 downto 0) <= rx_fsm_state when rising_edge(CLK_REF);
- DEBUG_OUT(4) <= RX_LOS_IN when rising_edge(CLK_REF);
- DEBUG_OUT(5) <= RX_CDR_LOL_IN when rising_edge(CLK_REF);
- DEBUG_OUT(6) <= TX_PLL_LOL_IN when rising_edge(CLK_REF);
- DEBUG_OUT(7) <= LINK_TX_READY_IN when rising_edge(CLK_REF);
- DEBUG_OUT(8) <= link_rx_ready_i when rising_edge(CLK_REF);
- DEBUG_OUT(9) <= is_wap_zero_i when rising_edge(CLK_REF);
- DEBUG_OUT(10) <= link_half_done_i when rising_edge(CLK_REF);
- DEBUG_OUT(11) <= link_full_done_i when rising_edge(CLK_REF);
- DEBUG_OUT(12) <= '0';
- DEBUG_OUT(13) <= '0';
- DEBUG_OUT(14) <= '0';
- DEBUG_OUT(15) <= '0';
--- 16 pin debug connector ends here
- DEBUG_OUT(16) <= word_sync_rx_i;
- DEBUG_OUT(17) <= word_sync_tx_i;
- DEBUG_OUT(31 downto 18) <= (others => '0');
+ DEBUG_OUT(3 downto 0) <= rx_fsm_state;
+ DEBUG_OUT(4) <= RX_LOS_IN;
+ DEBUG_OUT(5) <= RX_CDR_LOL_IN;
+ DEBUG_OUT(6) <= TX_PLL_LOL_IN;
+ DEBUG_OUT(7) <= LINK_TX_READY_IN;
+ DEBUG_OUT(8) <= link_rx_ready_i;
+ DEBUG_OUT(9) <= is_wap_zero_i;
+ DEBUG_OUT(10) <= link_half_done_i;
+ DEBUG_OUT(11) <= link_full_done_i;
+ DEBUG_OUT(15 downto 12) <= debug_tx_control_i(3 downto 0);
+ DEBUG_OUT(19 downto 16) <= rx_lsm_state;
+ DEBUG_OUT(20) <= word_sync_rx_i;
+ DEBUG_OUT(21) <= word_sync_tx_i;
+ DEBUG_OUT(31 downto 22) <= (others => '0');
-- DEBUG_OUT <= (others => '0');
-- Some remarks on the SerDes issue:
signal link_full_done_qrx : std_logic;\r
signal link_full_done_qsys : std_logic;\r
\r
+-- attribute syn_keep : boolean;\r
+-- attribute syn_preserve : boolean; \r
+-- attribute syn_keep of sync_k_i : signal is true;\r
+-- attribute syn_preserve of sync_k_i : signal is true;\r
+\r
begin\r
\r
-- Syncing things\r
\r
constant Tshort : unsigned(31 downto 0) := x"0000000a";\r
-- @200MHz 100ms\r
- constant Tplol : unsigned(31 downto 0) := x"003fffff"; --x"01312d00";\r
- constant Tcdr : unsigned(31 downto 0) := x"003fffff"; --x"01312d00";\r
- constant Tviol : unsigned(31 downto 0) := x"003fffff"; --x"01312d00";\r
+ constant Tplol : unsigned(31 downto 0) := x"01312d00"; --x"003fffff";\r
+ constant Tcdr : unsigned(31 downto 0) := x"01312d00"; --x"003fffff";\r
+ constant Tviol : unsigned(31 downto 0) := x"01312d00"; --x"003fffff";\r
\r
signal pll_lol_s : std_logic;\r
signal cdr_lol_s : std_logic;\r
RX_SERDES_RST_OUT <= '0'; -- needed for RX_LOS to be active\r
RX_PCS_RST_OUT <= '1';\r
LINK_RX_READY_OUT <= '0';\r
- if( (pll_lol_s = '1') or (los_s = '1') or (sd_los_s = '1') ) then\r
+-- if( (pll_lol_s = '1') or (los_s = '1') or (sd_los_s = '1') ) then\r
+ if( (pll_lol_s = '1') or (sd_los_s = '1') ) then\r
cnt <= (others => '0');\r
else\r
if( cnt = Tplol ) then\r
IS_MODE : integer := c_IS_UNUSED\r
);\r
port(\r
- CLK_TXI : in std_logic;\r
+ CLK_TXI : in std_logic;\r
CLK_SYS : in std_logic;\r
RESET : in std_logic; -- async/sync reset\r
-- Media Interface\r
signal load_sop : std_logic;\r
signal load_eop : std_logic;\r
signal toggle_idle : std_logic;\r
+ signal send_steady_idle_int : std_logic;\r
+ signal word_sync_i : std_logic;\r
\r
signal link_tx_ready_qtx : std_logic;\r
signal link_rx_ready_qtx : std_logic;\r
signal link_active_int : std_logic;\r
signal link_active_qtx : std_logic;\r
signal link_active_qsys : std_logic;\r
-\r
- signal send_steady_idle_int : std_logic;\r
+ \r
+-- attribute syn_keep : boolean;\r
+-- attribute syn_preserve : boolean; \r
+-- attribute syn_keep of word_sync_i : signal is true;\r
+-- attribute syn_preserve of word_sync_i : signal is true;\r
\r
begin\r
\r
begin\r
if( (LINK_TX_READY_IN = '0') or (RESET = '1') ) then\r
current_state <= IDLE;\r
- TX_K_OUT <= '1';\r
+ TX_K_OUT <= '1';\r
TX_DATA_OUT <= K_NULL;\r
- WORD_SYNC_OUT <= '0';\r
+ word_sync_i <= '0';\r
+ toggle_idle <= '1';\r
else \r
if( rising_edge(CLK_TXI) ) then\r
- TX_K_OUT <= '0';\r
- WORD_SYNC_OUT <= '0';\r
- debug_sending_dlm <= '0';\r
- debug_sending_rst <= '0';\r
+ TX_K_OUT <= '0';\r
+ word_sync_i <= '0';\r
+ debug_sending_dlm <= '0';\r
+ debug_sending_rst <= '0';\r
case current_state is\r
when SEND_IDLE_L =>\r
TX_DATA_OUT <= K_IDLE;\r
end if;\r
\r
when SEND_IDLE_H =>\r
- WORD_SYNC_OUT <= '1';\r
+ word_sync_i <= '1';\r
if( (send_steady_idle_int = '1') or (toggle_idle = '1') ) then\r
TX_DATA_OUT <= D_IDLE1;\r
toggle_idle <= send_steady_idle_int;\r
current_state <= SEND_DATA_H;\r
\r
when SEND_DATA_H =>\r
- WORD_SYNC_OUT <= '1';\r
- TX_DATA_OUT <= ram_dout(15 downto 8);\r
+ word_sync_i <= '1';\r
+ TX_DATA_OUT <= ram_dout(15 downto 8);\r
\r
when SEND_DLM_L =>\r
TX_DATA_OUT <= K_DLM;\r
debug_sending_dlm <= '1';\r
\r
when SEND_DLM_H =>\r
- WORD_SYNC_OUT <= '1';\r
- TX_DATA_OUT <= send_dlm_word_i;\r
+ word_sync_i <= '1';\r
+ TX_DATA_OUT <= send_dlm_word_i;\r
\r
when SEND_RST_L =>\r
TX_DATA_OUT <= K_RST;\r
-- used to get out of async reset\r
\r
when SEND_RST_H =>\r
- WORD_SYNC_OUT <= '1';\r
- TX_DATA_OUT <= send_rst_word_i;\r
+ word_sync_i <= '1';\r
+ TX_DATA_OUT <= send_rst_word_i;\r
\r
when others =>\r
current_state <= SEND_IDLE_L;\r
DEBUG_OUT(30) <= send_dlm_i;\r
DEBUG_OUT(29) <= debug_sending_rst when rising_edge(CLK_TXI);\r
DEBUG_OUT(28 downto 6) <= (others => '0');\r
- DEBUG_OUT(5) <= send_steady_idle_int;\r
- DEBUG_OUT(4) <= toggle_idle;\r
- DEBUG_OUT(3 downto 0) <= state_bits;\r
+ DEBUG_OUT(5) <= send_steady_idle_int when rising_edge(CLK_TXI);\r
+ DEBUG_OUT(4) <= toggle_idle when rising_edge(CLK_TXI);\r
+ DEBUG_OUT(3 downto 0) <= state_bits when rising_edge(CLK_TXI);\r
\r
process(CLK_SYS)\r
begin\r
end if;\r
end process;\r
\r
-state_bits <= x"0" when current_state = IDLE else\r
- x"1" when current_state = SEND_IDLE_L else\r
- x"2" when current_state = SEND_IDLE_H else\r
- x"3" when current_state = SEND_DATA_L else\r
- x"4" when current_state = SEND_DATA_H else\r
- x"5" when current_state = SEND_DLM_L else\r
- x"6" when current_state = SEND_DLM_H else\r
- x"F";\r
+ state_bits <= x"0" when current_state = IDLE else\r
+ x"1" when current_state = SEND_IDLE_L else\r
+ x"2" when current_state = SEND_IDLE_H else\r
+ x"3" when current_state = SEND_DATA_L else\r
+ x"4" when current_state = SEND_DATA_H else\r
+ x"5" when current_state = SEND_DLM_L else\r
+ x"6" when current_state = SEND_DLM_H else\r
+ x"F";\r
\r
+ WORD_SYNC_OUT <= word_sync_i;\r
+ \r
end architecture;\r
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