added a UART module

diff --git a/lattice/ecp3/fifo/fifo_9x2k_oreg.ipx b/lattice/ecp3/fifo/fifo_9x2k_oreg.ipx
new file mode 100644 (file)
index 0000000..2c03fd5
--- /dev/null
+++ b/lattice/ecp3/fifo/fifo_9x2k_oreg.ipx
@@ -0,0 +1,9 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="fifo_9x2k_oreg" module="FIFO" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2014 07 01 15:37:22.992" version="4.9" type="Module" synthesis="synplify" source_format="VHDL">
+  <Package>
+               <File name="fifo_9x2k_oreg.lpc" type="lpc" modified="2014 07 01 15:37:19.000"/>
+               <File name="fifo_9x2k_oreg.vhd" type="top_level_vhdl" modified="2014 07 01 15:37:19.000"/>
+               <File name="fifo_9x2k_oreg_tmpl.vhd" type="template_vhdl" modified="2014 07 01 15:37:19.000"/>
+               <File name="tb_fifo_9x2k_oreg_tmpl.vhd" type="testbench_vhdl" modified="2014 07 01 15:37:19.000"/>
+  </Package>
+</DiamondModule>

diff --git a/lattice/ecp3/fifo/fifo_9x2k_oreg.lpc b/lattice/ecp3/fifo/fifo_9x2k_oreg.lpc
new file mode 100644 (file)
index 0000000..a50a9ed
--- /dev/null
+++ b/lattice/ecp3/fifo/fifo_9x2k_oreg.lpc
@@ -0,0 +1,45 @@
+[Device]
+Family=latticeecp3
+PartType=LFE3-150EA
+PartName=LFE3-150EA-6FN1156C
+SpeedGrade=6
+Package=FPBGA1156
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=FIFO
+CoreRevision=4.9
+ModuleName=fifo_9x2k_oreg
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=07/01/2014
+Time=15:37:19
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+FIFOImp=EBR Based
+Depth=2048
+Width=9
+regout=1
+CtrlByRdEn=0
+EmpFlg=0
+PeMode=Static - Dual Threshold
+PeAssert=10
+PeDeassert=12
+FullFlg=0
+PfMode=Static - Dual Threshold
+PfAssert=508
+PfDeassert=506
+RDataCount=0
+EnECC=0
+EnFWFT=0

diff --git a/lattice/ecp3/fifo/fifo_9x2k_oreg.vhd b/lattice/ecp3/fifo/fifo_9x2k_oreg.vhd
new file mode 100644 (file)
index 0000000..84125df
--- /dev/null
+++ b/lattice/ecp3/fifo/fifo_9x2k_oreg.vhd
@@ -0,0 +1,732 @@
+-- VHDL netlist generated by SCUBA Diamond_2.2_Production (99)
+-- Module  Version: 4.9
+--/d/jspc29/lattice/diamond/2.2_x64/ispfpga/bin/lin64/scuba -w -n fifo_9x2k_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 2048 -width 9 -depth 2048 -regout -no_enable -pe -1 -pf -1 -e 
+
+-- Tue Jul  1 15:37:19 2014
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp3;
+use ecp3.components.all;
+-- synopsys translate_on
+
+entity fifo_9x2k_oreg is
+    port (
+        Data: in  std_logic_vector(8 downto 0); 
+        Clock: in  std_logic; 
+        WrEn: in  std_logic; 
+        RdEn: in  std_logic; 
+        Reset: in  std_logic; 
+        Q: out  std_logic_vector(8 downto 0); 
+        Empty: out  std_logic; 
+        Full: out  std_logic);
+end fifo_9x2k_oreg;
+
+architecture Structure of fifo_9x2k_oreg is
+
+    -- internal signal declarations
+    signal invout_1: std_logic;
+    signal invout_0: std_logic;
+    signal rden_i_inv: std_logic;
+    signal fcnt_en: std_logic;
+    signal empty_i: std_logic;
+    signal empty_d: std_logic;
+    signal full_i: std_logic;
+    signal full_d: std_logic;
+    signal ifcount_0: std_logic;
+    signal ifcount_1: std_logic;
+    signal bdcnt_bctr_ci: std_logic;
+    signal ifcount_2: std_logic;
+    signal ifcount_3: std_logic;
+    signal co0: std_logic;
+    signal ifcount_4: std_logic;
+    signal ifcount_5: std_logic;
+    signal co1: std_logic;
+    signal ifcount_6: std_logic;
+    signal ifcount_7: std_logic;
+    signal co2: std_logic;
+    signal ifcount_8: std_logic;
+    signal ifcount_9: std_logic;
+    signal co3: std_logic;
+    signal ifcount_10: std_logic;
+    signal ifcount_11: std_logic;
+    signal co5: std_logic;
+    signal cnt_con: std_logic;
+    signal co4: std_logic;
+    signal cmp_ci: std_logic;
+    signal rden_i: std_logic;
+    signal co0_1: std_logic;
+    signal co1_1: std_logic;
+    signal co2_1: std_logic;
+    signal co3_1: std_logic;
+    signal co4_1: std_logic;
+    signal cmp_le_1: std_logic;
+    signal cmp_le_1_c: std_logic;
+    signal cmp_ci_1: std_logic;
+    signal fcount_0: std_logic;
+    signal fcount_1: std_logic;
+    signal co0_2: std_logic;
+    signal fcount_2: std_logic;
+    signal fcount_3: std_logic;
+    signal co1_2: std_logic;
+    signal fcount_4: std_logic;
+    signal fcount_5: std_logic;
+    signal co2_2: std_logic;
+    signal fcount_6: std_logic;
+    signal fcount_7: std_logic;
+    signal co3_2: std_logic;
+    signal fcount_8: std_logic;
+    signal fcount_9: std_logic;
+    signal co4_2: std_logic;
+    signal wren_i: std_logic;
+    signal wren_i_inv: std_logic;
+    signal fcount_10: std_logic;
+    signal fcount_11: std_logic;
+    signal cmp_ge_d1: std_logic;
+    signal cmp_ge_d1_c: std_logic;
+    signal iwcount_0: std_logic;
+    signal iwcount_1: std_logic;
+    signal w_ctr_ci: std_logic;
+    signal wcount_0: std_logic;
+    signal wcount_1: std_logic;
+    signal iwcount_2: std_logic;
+    signal iwcount_3: std_logic;
+    signal co0_3: std_logic;
+    signal wcount_2: std_logic;
+    signal wcount_3: std_logic;
+    signal iwcount_4: std_logic;
+    signal iwcount_5: std_logic;
+    signal co1_3: std_logic;
+    signal wcount_4: std_logic;
+    signal wcount_5: std_logic;
+    signal iwcount_6: std_logic;
+    signal iwcount_7: std_logic;
+    signal co2_3: std_logic;
+    signal wcount_6: std_logic;
+    signal wcount_7: std_logic;
+    signal iwcount_8: std_logic;
+    signal iwcount_9: std_logic;
+    signal co3_3: std_logic;
+    signal wcount_8: std_logic;
+    signal wcount_9: std_logic;
+    signal iwcount_10: std_logic;
+    signal iwcount_11: std_logic;
+    signal co5_1: std_logic;
+    signal co4_3: std_logic;
+    signal wcount_10: std_logic;
+    signal wcount_11: std_logic;
+    signal scuba_vlo: std_logic;
+    signal scuba_vhi: std_logic;
+    signal ircount_0: std_logic;
+    signal ircount_1: std_logic;
+    signal r_ctr_ci: std_logic;
+    signal rcount_0: std_logic;
+    signal rcount_1: std_logic;
+    signal ircount_2: std_logic;
+    signal ircount_3: std_logic;
+    signal co0_4: std_logic;
+    signal rcount_2: std_logic;
+    signal rcount_3: std_logic;
+    signal ircount_4: std_logic;
+    signal ircount_5: std_logic;
+    signal co1_4: std_logic;
+    signal rcount_4: std_logic;
+    signal rcount_5: std_logic;
+    signal ircount_6: std_logic;
+    signal ircount_7: std_logic;
+    signal co2_4: std_logic;
+    signal rcount_6: std_logic;
+    signal rcount_7: std_logic;
+    signal ircount_8: std_logic;
+    signal ircount_9: std_logic;
+    signal co3_4: std_logic;
+    signal rcount_8: std_logic;
+    signal rcount_9: std_logic;
+    signal ircount_10: std_logic;
+    signal ircount_11: std_logic;
+    signal co5_2: std_logic;
+    signal co4_4: std_logic;
+    signal rcount_10: std_logic;
+    signal rcount_11: std_logic;
+
+    -- local component declarations
+    component AGEB2
+        port (A0: in  std_logic; A1: in  std_logic; B0: in  std_logic; 
+            B1: in  std_logic; CI: in  std_logic; GE: out  std_logic);
+    end component;
+    component ALEB2
+        port (A0: in  std_logic; A1: in  std_logic; B0: in  std_logic; 
+            B1: in  std_logic; CI: in  std_logic; LE: out  std_logic);
+    end component;
+    component AND2
+        port (A: in  std_logic; B: in  std_logic; Z: out  std_logic);
+    end component;
+    component CU2
+        port (CI: in  std_logic; PC0: in  std_logic; PC1: in  std_logic; 
+            CO: out  std_logic; NC0: out  std_logic; NC1: out  std_logic);
+    end component;
+    component CB2
+        port (CI: in  std_logic; PC0: in  std_logic; PC1: in  std_logic; 
+            CON: in  std_logic; CO: out  std_logic; NC0: out  std_logic; 
+            NC1: out  std_logic);
+    end component;
+    component FADD2B
+        port (A0: in  std_logic; A1: in  std_logic; B0: in  std_logic; 
+            B1: in  std_logic; CI: in  std_logic; COUT: out  std_logic; 
+            S0: out  std_logic; S1: out  std_logic);
+    end component;
+    component FD1P3DX
+        port (D: in  std_logic; SP: in  std_logic; CK: in  std_logic; 
+            CD: in  std_logic; Q: out  std_logic);
+    end component;
+    component FD1S3BX
+        port (D: in  std_logic; CK: in  std_logic; PD: in  std_logic; 
+            Q: out  std_logic);
+    end component;
+    component FD1S3DX
+        port (D: in  std_logic; CK: in  std_logic; CD: in  std_logic; 
+            Q: out  std_logic);
+    end component;
+    component INV
+        port (A: in  std_logic; Z: out  std_logic);
+    end component;
+    component ROM16X1A
+        generic (INITVAL : in std_logic_vector(15 downto 0));
+        port (AD3: in  std_logic; AD2: in  std_logic; AD1: in  std_logic; 
+            AD0: in  std_logic; DO0: out  std_logic);
+    end component;
+    component VHI
+        port (Z: out  std_logic);
+    end component;
+    component VLO
+        port (Z: out  std_logic);
+    end component;
+    component XOR2
+        port (A: in  std_logic; B: in  std_logic; Z: out  std_logic);
+    end component;
+    component DP16KC
+        generic (GSR : in String; WRITEMODE_B : in String; 
+                WRITEMODE_A : in String; CSDECODE_B : in String; 
+                CSDECODE_A : in String; REGMODE_B : in String; 
+                REGMODE_A : in String; DATA_WIDTH_B : in Integer; 
+                DATA_WIDTH_A : in Integer);
+        port (DIA0: in  std_logic; DIA1: in  std_logic; 
+            DIA2: in  std_logic; DIA3: in  std_logic; 
+            DIA4: in  std_logic; DIA5: in  std_logic; 
+            DIA6: in  std_logic; DIA7: in  std_logic; 
+            DIA8: in  std_logic; DIA9: in  std_logic; 
+            DIA10: in  std_logic; DIA11: in  std_logic; 
+            DIA12: in  std_logic; DIA13: in  std_logic; 
+            DIA14: in  std_logic; DIA15: in  std_logic; 
+            DIA16: in  std_logic; DIA17: in  std_logic; 
+            ADA0: in  std_logic; ADA1: in  std_logic; 
+            ADA2: in  std_logic; ADA3: in  std_logic; 
+            ADA4: in  std_logic; ADA5: in  std_logic; 
+            ADA6: in  std_logic; ADA7: in  std_logic; 
+            ADA8: in  std_logic; ADA9: in  std_logic; 
+            ADA10: in  std_logic; ADA11: in  std_logic; 
+            ADA12: in  std_logic; ADA13: in  std_logic; 
+            CEA: in  std_logic; CLKA: in  std_logic; OCEA: in  std_logic; 
+            WEA: in  std_logic; CSA0: in  std_logic; CSA1: in  std_logic; 
+            CSA2: in  std_logic; RSTA: in  std_logic; 
+            DIB0: in  std_logic; DIB1: in  std_logic; 
+            DIB2: in  std_logic; DIB3: in  std_logic; 
+            DIB4: in  std_logic; DIB5: in  std_logic; 
+            DIB6: in  std_logic; DIB7: in  std_logic; 
+            DIB8: in  std_logic; DIB9: in  std_logic; 
+            DIB10: in  std_logic; DIB11: in  std_logic; 
+            DIB12: in  std_logic; DIB13: in  std_logic; 
+            DIB14: in  std_logic; DIB15: in  std_logic; 
+            DIB16: in  std_logic; DIB17: in  std_logic; 
+            ADB0: in  std_logic; ADB1: in  std_logic; 
+            ADB2: in  std_logic; ADB3: in  std_logic; 
+            ADB4: in  std_logic; ADB5: in  std_logic; 
+            ADB6: in  std_logic; ADB7: in  std_logic; 
+            ADB8: in  std_logic; ADB9: in  std_logic; 
+            ADB10: in  std_logic; ADB11: in  std_logic; 
+            ADB12: in  std_logic; ADB13: in  std_logic; 
+            CEB: in  std_logic; CLKB: in  std_logic; OCEB: in  std_logic; 
+            WEB: in  std_logic; CSB0: in  std_logic; CSB1: in  std_logic; 
+            CSB2: in  std_logic; RSTB: in  std_logic; 
+            DOA0: out  std_logic; DOA1: out  std_logic; 
+            DOA2: out  std_logic; DOA3: out  std_logic; 
+            DOA4: out  std_logic; DOA5: out  std_logic; 
+            DOA6: out  std_logic; DOA7: out  std_logic; 
+            DOA8: out  std_logic; DOA9: out  std_logic; 
+            DOA10: out  std_logic; DOA11: out  std_logic; 
+            DOA12: out  std_logic; DOA13: out  std_logic; 
+            DOA14: out  std_logic; DOA15: out  std_logic; 
+            DOA16: out  std_logic; DOA17: out  std_logic; 
+            DOB0: out  std_logic; DOB1: out  std_logic; 
+            DOB2: out  std_logic; DOB3: out  std_logic; 
+            DOB4: out  std_logic; DOB5: out  std_logic; 
+            DOB6: out  std_logic; DOB7: out  std_logic; 
+            DOB8: out  std_logic; DOB9: out  std_logic; 
+            DOB10: out  std_logic; DOB11: out  std_logic; 
+            DOB12: out  std_logic; DOB13: out  std_logic; 
+            DOB14: out  std_logic; DOB15: out  std_logic; 
+            DOB16: out  std_logic; DOB17: out  std_logic);
+    end component;
+    attribute MEM_LPC_FILE : string; 
+    attribute MEM_INIT_FILE : string; 
+    attribute RESETMODE : string; 
+    attribute GSR : string; 
+    attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "fifo_9x2k_oreg.lpc";
+    attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is "";
+    attribute RESETMODE of pdp_ram_0_0_0 : label is "SYNC";
+    attribute GSR of FF_37 : label is "ENABLED";
+    attribute GSR of FF_36 : label is "ENABLED";
+    attribute GSR of FF_35 : label is "ENABLED";
+    attribute GSR of FF_34 : label is "ENABLED";
+    attribute GSR of FF_33 : label is "ENABLED";
+    attribute GSR of FF_32 : label is "ENABLED";
+    attribute GSR of FF_31 : label is "ENABLED";
+    attribute GSR of FF_30 : label is "ENABLED";
+    attribute GSR of FF_29 : label is "ENABLED";
+    attribute GSR of FF_28 : label is "ENABLED";
+    attribute GSR of FF_27 : label is "ENABLED";
+    attribute GSR of FF_26 : label is "ENABLED";
+    attribute GSR of FF_25 : label is "ENABLED";
+    attribute GSR of FF_24 : label is "ENABLED";
+    attribute GSR of FF_23 : label is "ENABLED";
+    attribute GSR of FF_22 : label is "ENABLED";
+    attribute GSR of FF_21 : label is "ENABLED";
+    attribute GSR of FF_20 : label is "ENABLED";
+    attribute GSR of FF_19 : label is "ENABLED";
+    attribute GSR of FF_18 : label is "ENABLED";
+    attribute GSR of FF_17 : label is "ENABLED";
+    attribute GSR of FF_16 : label is "ENABLED";
+    attribute GSR of FF_15 : label is "ENABLED";
+    attribute GSR of FF_14 : label is "ENABLED";
+    attribute GSR of FF_13 : label is "ENABLED";
+    attribute GSR of FF_12 : label is "ENABLED";
+    attribute GSR of FF_11 : label is "ENABLED";
+    attribute GSR of FF_10 : label is "ENABLED";
+    attribute GSR of FF_9 : label is "ENABLED";
+    attribute GSR of FF_8 : label is "ENABLED";
+    attribute GSR of FF_7 : label is "ENABLED";
+    attribute GSR of FF_6 : label is "ENABLED";
+    attribute GSR of FF_5 : label is "ENABLED";
+    attribute GSR of FF_4 : label is "ENABLED";
+    attribute GSR of FF_3 : label is "ENABLED";
+    attribute GSR of FF_2 : label is "ENABLED";
+    attribute GSR of FF_1 : label is "ENABLED";
+    attribute GSR of FF_0 : label is "ENABLED";
+    attribute syn_keep : boolean;
+    attribute NGD_DRC_MASK : integer;
+    attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+    -- component instantiation statements
+    AND2_t3: AND2
+        port map (A=>WrEn, B=>invout_1, Z=>wren_i);
+
+    INV_3: INV
+        port map (A=>full_i, Z=>invout_1);
+
+    AND2_t2: AND2
+        port map (A=>RdEn, B=>invout_0, Z=>rden_i);
+
+    INV_2: INV
+        port map (A=>empty_i, Z=>invout_0);
+
+    AND2_t1: AND2
+        port map (A=>wren_i, B=>rden_i_inv, Z=>cnt_con);
+
+    XOR2_t0: XOR2
+        port map (A=>wren_i, B=>rden_i, Z=>fcnt_en);
+
+    INV_1: INV
+        port map (A=>rden_i, Z=>rden_i_inv);
+
+    INV_0: INV
+        port map (A=>wren_i, Z=>wren_i_inv);
+
+    LUT4_1: ROM16X1A
+        generic map (initval=> X"3232")
+        port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i, 
+            AD0=>empty_i, DO0=>empty_d);
+
+    LUT4_0: ROM16X1A
+        generic map (initval=> X"3232")
+        port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i, 
+            AD0=>full_i, DO0=>full_d);
+
+    pdp_ram_0_0_0: DP16KC
+        generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", 
+        WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), 
+            DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), 
+            DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, 
+            DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, 
+            DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, 
+            DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, 
+            ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wcount_0, 
+            ADA4=>wcount_1, ADA5=>wcount_2, ADA6=>wcount_3, 
+            ADA7=>wcount_4, ADA8=>wcount_5, ADA9=>wcount_6, 
+            ADA10=>wcount_7, ADA11=>wcount_8, ADA12=>wcount_9, 
+            ADA13=>wcount_10, CEA=>wren_i, CLKA=>Clock, OCEA=>wren_i, 
+            WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo, 
+            CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, 
+            DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, 
+            ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rcount_0, 
+            ADB4=>rcount_1, ADB5=>rcount_2, ADB6=>rcount_3, 
+            ADB7=>rcount_4, ADB8=>rcount_5, ADB9=>rcount_6, 
+            ADB10=>rcount_7, ADB11=>rcount_8, ADB12=>rcount_9, 
+            ADB13=>rcount_10, CEB=>rden_i, CLKB=>Clock, OCEB=>scuba_vhi, 
+            WEB=>scuba_vlo, CSB0=>scuba_vlo, CSB1=>scuba_vlo, 
+            CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, 
+            DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, 
+            DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, 
+            DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, 
+            DOA16=>open, DOA17=>open, DOB0=>Q(0), DOB1=>Q(1), DOB2=>Q(2), 
+            DOB3=>Q(3), DOB4=>Q(4), DOB5=>Q(5), DOB6=>Q(6), DOB7=>Q(7), 
+            DOB8=>Q(8), DOB9=>open, DOB10=>open, DOB11=>open, 
+            DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, 
+            DOB16=>open, DOB17=>open);
+
+    FF_37: FD1P3DX
+        port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_0);
+
+    FF_36: FD1P3DX
+        port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_1);
+
+    FF_35: FD1P3DX
+        port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_2);
+
+    FF_34: FD1P3DX
+        port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_3);
+
+    FF_33: FD1P3DX
+        port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_4);
+
+    FF_32: FD1P3DX
+        port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_5);
+
+    FF_31: FD1P3DX
+        port map (D=>ifcount_6, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_6);
+
+    FF_30: FD1P3DX
+        port map (D=>ifcount_7, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_7);
+
+    FF_29: FD1P3DX
+        port map (D=>ifcount_8, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_8);
+
+    FF_28: FD1P3DX
+        port map (D=>ifcount_9, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_9);
+
+    FF_27: FD1P3DX
+        port map (D=>ifcount_10, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_10);
+
+    FF_26: FD1P3DX
+        port map (D=>ifcount_11, SP=>fcnt_en, CK=>Clock, CD=>Reset, 
+            Q=>fcount_11);
+
+    FF_25: FD1S3BX
+        port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i);
+
+    FF_24: FD1S3DX
+        port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i);
+
+    FF_23: FD1P3DX
+        port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_0);
+
+    FF_22: FD1P3DX
+        port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_1);
+
+    FF_21: FD1P3DX
+        port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_2);
+
+    FF_20: FD1P3DX
+        port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_3);
+
+    FF_19: FD1P3DX
+        port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_4);
+
+    FF_18: FD1P3DX
+        port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_5);
+
+    FF_17: FD1P3DX
+        port map (D=>iwcount_6, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_6);
+
+    FF_16: FD1P3DX
+        port map (D=>iwcount_7, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_7);
+
+    FF_15: FD1P3DX
+        port map (D=>iwcount_8, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_8);
+
+    FF_14: FD1P3DX
+        port map (D=>iwcount_9, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_9);
+
+    FF_13: FD1P3DX
+        port map (D=>iwcount_10, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_10);
+
+    FF_12: FD1P3DX
+        port map (D=>iwcount_11, SP=>wren_i, CK=>Clock, CD=>Reset, 
+            Q=>wcount_11);
+
+    FF_11: FD1P3DX
+        port map (D=>ircount_0, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_0);
+
+    FF_10: FD1P3DX
+        port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_1);
+
+    FF_9: FD1P3DX
+        port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_2);
+
+    FF_8: FD1P3DX
+        port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_3);
+
+    FF_7: FD1P3DX
+        port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_4);
+
+    FF_6: FD1P3DX
+        port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_5);
+
+    FF_5: FD1P3DX
+        port map (D=>ircount_6, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_6);
+
+    FF_4: FD1P3DX
+        port map (D=>ircount_7, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_7);
+
+    FF_3: FD1P3DX
+        port map (D=>ircount_8, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_8);
+
+    FF_2: FD1P3DX
+        port map (D=>ircount_9, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_9);
+
+    FF_1: FD1P3DX
+        port map (D=>ircount_10, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_10);
+
+    FF_0: FD1P3DX
+        port map (D=>ircount_11, SP=>rden_i, CK=>Clock, CD=>Reset, 
+            Q=>rcount_11);
+
+    bdcnt_bctr_cia: FADD2B
+        port map (A0=>scuba_vlo, A1=>cnt_con, B0=>scuba_vlo, B1=>cnt_con, 
+            CI=>scuba_vlo, COUT=>bdcnt_bctr_ci, S0=>open, S1=>open);
+
+    bdcnt_bctr_0: CB2
+        port map (CI=>bdcnt_bctr_ci, PC0=>fcount_0, PC1=>fcount_1, 
+            CON=>cnt_con, CO=>co0, NC0=>ifcount_0, NC1=>ifcount_1);
+
+    bdcnt_bctr_1: CB2
+        port map (CI=>co0, PC0=>fcount_2, PC1=>fcount_3, CON=>cnt_con, 
+            CO=>co1, NC0=>ifcount_2, NC1=>ifcount_3);
+
+    bdcnt_bctr_2: CB2
+        port map (CI=>co1, PC0=>fcount_4, PC1=>fcount_5, CON=>cnt_con, 
+            CO=>co2, NC0=>ifcount_4, NC1=>ifcount_5);
+
+    bdcnt_bctr_3: CB2
+        port map (CI=>co2, PC0=>fcount_6, PC1=>fcount_7, CON=>cnt_con, 
+            CO=>co3, NC0=>ifcount_6, NC1=>ifcount_7);
+
+    bdcnt_bctr_4: CB2
+        port map (CI=>co3, PC0=>fcount_8, PC1=>fcount_9, CON=>cnt_con, 
+            CO=>co4, NC0=>ifcount_8, NC1=>ifcount_9);
+
+    bdcnt_bctr_5: CB2
+        port map (CI=>co4, PC0=>fcount_10, PC1=>fcount_11, CON=>cnt_con, 
+            CO=>co5, NC0=>ifcount_10, NC1=>ifcount_11);
+
+    e_cmp_ci_a: FADD2B
+        port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, 
+            B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, 
+            S1=>open);
+
+    e_cmp_0: ALEB2
+        port map (A0=>fcount_0, A1=>fcount_1, B0=>rden_i, B1=>scuba_vlo, 
+            CI=>cmp_ci, LE=>co0_1);
+
+    e_cmp_1: ALEB2
+        port map (A0=>fcount_2, A1=>fcount_3, B0=>scuba_vlo, 
+            B1=>scuba_vlo, CI=>co0_1, LE=>co1_1);
+
+    e_cmp_2: ALEB2
+        port map (A0=>fcount_4, A1=>fcount_5, B0=>scuba_vlo, 
+            B1=>scuba_vlo, CI=>co1_1, LE=>co2_1);
+
+    e_cmp_3: ALEB2
+        port map (A0=>fcount_6, A1=>fcount_7, B0=>scuba_vlo, 
+            B1=>scuba_vlo, CI=>co2_1, LE=>co3_1);
+
+    e_cmp_4: ALEB2
+        port map (A0=>fcount_8, A1=>fcount_9, B0=>scuba_vlo, 
+            B1=>scuba_vlo, CI=>co3_1, LE=>co4_1);
+
+    e_cmp_5: ALEB2
+        port map (A0=>fcount_10, A1=>fcount_11, B0=>scuba_vlo, 
+            B1=>scuba_vlo, CI=>co4_1, LE=>cmp_le_1_c);
+
+    a0: FADD2B
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, CI=>cmp_le_1_c, COUT=>open, S0=>cmp_le_1, 
+            S1=>open);
+
+    g_cmp_ci_a: FADD2B
+        port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, 
+            B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, 
+            S1=>open);
+
+    g_cmp_0: AGEB2
+        port map (A0=>fcount_0, A1=>fcount_1, B0=>wren_i, B1=>wren_i, 
+            CI=>cmp_ci_1, GE=>co0_2);
+
+    g_cmp_1: AGEB2
+        port map (A0=>fcount_2, A1=>fcount_3, B0=>wren_i, B1=>wren_i, 
+            CI=>co0_2, GE=>co1_2);
+
+    g_cmp_2: AGEB2
+        port map (A0=>fcount_4, A1=>fcount_5, B0=>wren_i, B1=>wren_i, 
+            CI=>co1_2, GE=>co2_2);
+
+    g_cmp_3: AGEB2
+        port map (A0=>fcount_6, A1=>fcount_7, B0=>wren_i, B1=>wren_i, 
+            CI=>co2_2, GE=>co3_2);
+
+    g_cmp_4: AGEB2
+        port map (A0=>fcount_8, A1=>fcount_9, B0=>wren_i, B1=>wren_i, 
+            CI=>co3_2, GE=>co4_2);
+
+    g_cmp_5: AGEB2
+        port map (A0=>fcount_10, A1=>fcount_11, B0=>wren_i, 
+            B1=>wren_i_inv, CI=>co4_2, GE=>cmp_ge_d1_c);
+
+    a1: FADD2B
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, CI=>cmp_ge_d1_c, COUT=>open, S0=>cmp_ge_d1, 
+            S1=>open);
+
+    w_ctr_cia: FADD2B
+        port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, 
+            B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_ctr_ci, S0=>open, 
+            S1=>open);
+
+    w_ctr_0: CU2
+        port map (CI=>w_ctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0_3, 
+            NC0=>iwcount_0, NC1=>iwcount_1);
+
+    w_ctr_1: CU2
+        port map (CI=>co0_3, PC0=>wcount_2, PC1=>wcount_3, CO=>co1_3, 
+            NC0=>iwcount_2, NC1=>iwcount_3);
+
+    w_ctr_2: CU2
+        port map (CI=>co1_3, PC0=>wcount_4, PC1=>wcount_5, CO=>co2_3, 
+            NC0=>iwcount_4, NC1=>iwcount_5);
+
+    w_ctr_3: CU2
+        port map (CI=>co2_3, PC0=>wcount_6, PC1=>wcount_7, CO=>co3_3, 
+            NC0=>iwcount_6, NC1=>iwcount_7);
+
+    w_ctr_4: CU2
+        port map (CI=>co3_3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4_3, 
+            NC0=>iwcount_8, NC1=>iwcount_9);
+
+    w_ctr_5: CU2
+        port map (CI=>co4_3, PC0=>wcount_10, PC1=>wcount_11, CO=>co5_1, 
+            NC0=>iwcount_10, NC1=>iwcount_11);
+
+    scuba_vlo_inst: VLO
+        port map (Z=>scuba_vlo);
+
+    scuba_vhi_inst: VHI
+        port map (Z=>scuba_vhi);
+
+    r_ctr_cia: FADD2B
+        port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, 
+            B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_ctr_ci, S0=>open, 
+            S1=>open);
+
+    r_ctr_0: CU2
+        port map (CI=>r_ctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_4, 
+            NC0=>ircount_0, NC1=>ircount_1);
+
+    r_ctr_1: CU2
+        port map (CI=>co0_4, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_4, 
+            NC0=>ircount_2, NC1=>ircount_3);
+
+    r_ctr_2: CU2
+        port map (CI=>co1_4, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_4, 
+            NC0=>ircount_4, NC1=>ircount_5);
+
+    r_ctr_3: CU2
+        port map (CI=>co2_4, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_4, 
+            NC0=>ircount_6, NC1=>ircount_7);
+
+    r_ctr_4: CU2
+        port map (CI=>co3_4, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_4, 
+            NC0=>ircount_8, NC1=>ircount_9);
+
+    r_ctr_5: CU2
+        port map (CI=>co4_4, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_2, 
+            NC0=>ircount_10, NC1=>ircount_11);
+
+    Empty <= empty_i;
+    Full <= full_i;
+end Structure;
+
+-- synopsys translate_off
+library ecp3;
+configuration Structure_CON of fifo_9x2k_oreg is
+    for Structure
+        for all:AGEB2 use entity ecp3.AGEB2(V); end for;
+        for all:ALEB2 use entity ecp3.ALEB2(V); end for;
+        for all:AND2 use entity ecp3.AND2(V); end for;
+        for all:CU2 use entity ecp3.CU2(V); end for;
+        for all:CB2 use entity ecp3.CB2(V); end for;
+        for all:FADD2B use entity ecp3.FADD2B(V); end for;
+        for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for;
+        for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for;
+        for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for;
+        for all:INV use entity ecp3.INV(V); end for;
+        for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for;
+        for all:VHI use entity ecp3.VHI(V); end for;
+        for all:VLO use entity ecp3.VLO(V); end for;
+        for all:XOR2 use entity ecp3.XOR2(V); end for;
+        for all:DP16KC use entity ecp3.DP16KC(V); end for;
+    end for;
+end Structure_CON;
+
+-- synopsys translate_on

diff --git a/special/uart.vhd b/special/uart.vhd
new file mode 100644 (file)
index 0000000..9f86e9d
--- /dev/null
+++ b/special/uart.vhd
@@ -0,0 +1,164 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.trb_net_std.all;
+use work.version.all;
+
+library machxo2;
+use machxo2.all;
+
+
+entity uart is
+  port(
+    CLK     : in  std_logic;
+    RESET   : in  std_logic;
+    UART_RX : in  std_logic;
+    UART_TX : out std_logic;
+    
+    DATA_OUT  : out std_logic_vector(31 downto 0);
+    DATA_IN   : in  std_logic_vector(31 downto 0);
+    ADDR_IN   : in  std_logic_vector(15 downto 0);
+    WRITE_IN  : in  std_logic;
+    READ_IN   : in  std_logic;
+    ACK_OUT   : out std_logic;
+    EMPTY_OUT : out std_logic;
+    UNKWN_OUT : out std_logic;
+    DEBUG     : out std_logic_vector(15 downto 0)
+    );
+end entity;
+
+
+architecture uart_arch of uart is
+
+signal rx_data   : std_logic_vector(7 downto 0);
+signal rx_ready  : std_logic;
+signal tx_send   : std_logic;
+signal tx_ready  : std_logic;
+
+signal clk_div   : integer := 100000000/57600;
+
+signal tx_fifo_out   : std_logic_vector(8 downto 0);
+signal rx_fifo_out   : std_logic_vector(8 downto 0);
+signal tx_fifo_empty : std_logic;
+signal tx_fifo_full  : std_logic;
+signal rx_fifo_empty : std_logic;
+signal rx_fifo_full  : std_logic;
+signal rx_fifo_read  : std_logic;
+signal tx_fifo_read  : std_logic;
+signal tx_fifo_write : std_logic;
+
+signal next2_tx_send, next_tx_send : std_logic;
+signal last2_rx_read, last_rx_read : std_logic;
+
+begin
+
+
+THE_RX : entity work.uart_rec
+  port map(
+    CLK_DIV      => clk_div,
+    CLK          => CLK,
+    RST          => RESET,
+    RX           => UART_RX,
+    DATA_OUT     => rx_data,
+    DATA_WAITING => rx_ready
+    );
+
+THE_TX : entity work.uart_trans
+  port map(
+    CLK_DIV      => clk_div,
+    CLK          => CLK,
+    RST          => RESET,
+    DATA_IN      => tx_fifo_out(7 downto 0),
+    SEND         => tx_send,
+    READY        => tx_ready,
+    TX           => UART_TX
+    );
+
+    
+THE_RX_FIFO : entity work.fifo_9x2k_oreg
+  port map(
+    Clock => CLK,
+    Data(7 downto 0)  => rx_data,
+    Data(8)           => '0',
+    WrEn  => rx_ready,
+    RdEn  => rx_fifo_read,
+    Reset => RESET,
+    Q     => rx_fifo_out,
+    Empty => rx_fifo_empty,
+    Full  => rx_fifo_full
+    );
+
+THE_TX_FIFO : entity work.fifo_9x2k_oreg
+  port map(
+    Clock => CLK,
+    Data  => DATA_IN(8 downto 0),
+    WrEn  => tx_fifo_write,
+    RdEn  => tx_fifo_read,
+    Reset => RESET,
+    Q     => tx_fifo_out,
+    Empty => tx_fifo_empty,
+    Full  => tx_fifo_full
+    );
+
+PROC_REGS : process begin
+  wait until rising_edge(CLK);
+  UNKWN_OUT <= '0';
+  ACK_OUT   <= '0';
+  EMPTY_OUT <= '0';
+  DATA_OUT  <= (others => '0');
+  
+  tx_fifo_write <= '0';
+  rx_fifo_read  <= '0';
+  last_rx_read  <= rx_fifo_read;
+  last2_rx_read <= last_rx_read;
+  
+  if last2_rx_read = '1' then
+    DATA_OUT(8 downto 0) <= rx_fifo_out;
+    ACK_OUT              <= '1';
+  elsif WRITE_IN = '1' then
+    if ADDR_IN(3 downto 0) = x"0" then
+      tx_fifo_write <= not tx_fifo_full;
+      ACK_OUT       <= not tx_fifo_full;
+      EMPTY_OUT     <=     tx_fifo_full;
+    elsif ADDR_IN(3 downto 0) = x"1" then
+      clk_div  <= to_integer(unsigned(DATA_IN));
+      ACK_OUT  <= '1';
+    else
+      UNKWN_OUT     <= '1';
+    end if;
+  
+  elsif READ_IN = '1' then
+    if ADDR_IN(3 downto 0) = x"0" then
+      rx_fifo_read <= not rx_fifo_empty;
+      EMPTY_OUT    <=     rx_fifo_empty;
+    elsif ADDR_IN(3 downto 0) = x"1" then
+      DATA_OUT <= std_logic_vector(to_unsigned(clk_div,32));
+      ACK_OUT  <= '1';
+    else
+      UNKWN_OUT <= '1';
+    end if;
+  end if;
+  
+end process;
+    
+PROC_SEND : process begin
+  wait until rising_edge(CLK);
+  tx_fifo_read  <= '0';
+  next_tx_send  <= '0';
+  next2_tx_send <= next_tx_send;
+  tx_send       <= next2_tx_send;
+  
+  if tx_fifo_empty = '0' and tx_ready = '1' and next_tx_send = '0' and next2_tx_send = '0' then
+    next_tx_send <= '1';  
+    tx_fifo_read <= '1';
+  end if;
+  
+end process;
+    
+
+    
+end architecture;
+
+

diff --git a/special/uart_trans.vhd b/special/uart_trans.vhd
index c062f8160115bd2b41227e2c59e81d36dd156bf3..8ea2c0d6129df2a1aef84974316c1edc96733702 100644 (file)
--- a/special/uart_trans.vhd
+++ b/special/uart_trans.vhd
@@ -137,6 +137,7 @@ DEBUG(3) <= '0';
     if RST = '1' then
       state <= idle;
       ready_sig <= '1';
+      symbol <= '1';
     end if;
 
   end process;

diff --git a/trb_net16_api_ipu_streaming.vhd b/trb_net16_api_ipu_streaming.vhd
index f5debeef3574710fe46582cb1f4d62a85188ebd6..5a1d167c8969646b9087ff92534a4064ca410a84 100644 (file)
--- a/trb_net16_api_ipu_streaming.vhd
+++ b/trb_net16_api_ipu_streaming.vhd
@@ -69,7 +69,7 @@ end entity;
 architecture trb_net16_api_ipu_streaming_arch of trb_net16_api_ipu_streaming is
 
   attribute syn_hier : string;
-  attribute syn_hier of trb_net16_api_ipu_streaming_arch : architecture is "firm";
+  attribute syn_hier of trb_net16_api_ipu_streaming_arch : architecture is "hard, firm";
 
   signal APL_CTS_TARGET_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF";
   signal APL_CTS_DATA_OUT       : std_logic_vector(15 downto 0);