*** empty log message ***

diff --git a/trb_net16_hub_base.vhd b/trb_net16_hub_base.vhd
index 489b152149af8380dbd6a09a745f733b86740094..44c0721d3826e6eea0d52bab6d6dca71a6aaa7ef 100644 (file)
--- a/trb_net16_hub_base.vhd
+++ b/trb_net16_hub_base.vhd
@@ -19,6 +19,9 @@ entity trb_net16_hub_base is
     IBUF_SECURE_MODE        : integer range 0 to 1 := c_NO;
     INIT_ADDRESS            : std_logic_vector(15 downto 0) := x"F004";
     INIT_UNIQUE_ID          : std_logic_vector(95 downto 0) := (others => '0');
+    COMPILE_TIME       : std_logic_vector(31 downto 0) := x"00000000";
+    COMPILE_VERSION    : std_logic_vector(15 downto 0) := x"0001";
+    HARDWARE_VERSION   : std_logic_vector(31 downto 0) := x"12345678";
   --media interfaces
     MII_NUMBER              : integer range 2 to c_MAX_MII_PER_HUB := 4;
     MII_IBUF_DEPTH          : hub_iobuf_config_t := std_HUB_IBUF_DEPTH;
@@ -400,73 +403,83 @@ end component;
   end component;
 
   component trb_net16_regIO is
-    generic (
-      REGISTER_WIDTH     : integer range 32 to 32 := 32;
-      ADDRESS_WIDTH      : integer range 8 to 16 := 16;
-      NUM_STAT_REGS      : integer range 0 to 6 := 3; --log2 of number of status registers
-      NUM_CTRL_REGS      : integer range 0 to 6 := 3; --log2 of number of ctrl registers
-      --standard values for output registers
-      INIT_CTRL_REGS     : std_logic_vector(2**(3)*32-1 downto 0) :=
-              (others => '0');
-      --set to 0 for unused ctrl registers to save resources
-      USED_CTRL_REGS     : std_logic_vector(2**(3)-1 downto 0)   := "11111111";
-      --set to 0 for each unused bit in a register
-      USED_CTRL_BITMASK  : std_logic_vector(2**(3)*32-1 downto 0) :=
-              (others => '1');
-      --no data / address out?
-      NO_DAT_PORT        : std_logic := '0';
-      INIT_ADDRESS       : std_logic_vector(15 downto 0) := x"FFFF";
-      INIT_UNIQUE_ID     : std_logic_vector(95 downto 0) := (others => '0')
-      );
-    port(
-    --  Misc
-      CLK    : in std_logic;
-      RESET  : in std_logic;
-      CLK_EN : in std_logic;
-    -- Port to API
-      API_DATA_OUT           : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
-      API_PACKET_NUM_OUT     : out std_logic_vector (c_NUM_WIDTH-1  downto 0);
-      API_DATAREADY_OUT      : out std_logic;
-      API_READ_IN            : in  std_logic;
-      API_SHORT_TRANSFER_OUT : out std_logic;
-      API_DTYPE_OUT          : out std_logic_vector (3 downto 0);
-      API_ERROR_PATTERN_OUT  : out std_logic_vector (31 downto 0);
-      API_SEND_OUT           : out std_logic;
-      API_TARGET_ADDRESS_OUT : out std_logic_vector (15 downto 0);
-      -- Receiver port
-      API_DATA_IN         : in  std_logic_vector (c_DATA_WIDTH-1 downto 0);
-      API_PACKET_NUM_IN   : in  std_logic_vector (c_NUM_WIDTH-1  downto 0);
-      API_TYP_IN          : in  std_logic_vector (2 downto 0);
-      API_DATAREADY_IN    : in  std_logic;
-      API_READ_OUT        : out std_logic;
-      -- APL Control port
-      API_RUN_IN          : in  std_logic;
-      API_SEQNR_IN        : in  std_logic_vector (7 downto 0);
-
-      MY_ADDRESS_OUT      : out std_logic_vector(15 downto 0);
-      --Port to write Unique ID
-      IDRAM_DATA_IN       : in  std_logic_vector(15 downto 0);
-      IDRAM_DATA_OUT      : out std_logic_vector(15 downto 0);
-      IDRAM_ADDR_IN       : in  std_logic_vector(2 downto 0);
-      IDRAM_WR_IN         : in  std_logic;
-
-
-    --Register in / out
-      REGISTERS_IN        : in  std_logic_vector(REGISTER_WIDTH*2**(NUM_STAT_REGS)-1 downto 0);
-      REGISTERS_OUT       : out std_logic_vector(REGISTER_WIDTH*2**(NUM_CTRL_REGS)-1 downto 0);
-
-    --following ports only used when no internal register is accessed
-      DAT_ADDR_OUT        : out std_logic_vector(ADDRESS_WIDTH-1 downto 0);
-      DAT_READ_ENABLE_OUT : out std_logic;
-      DAT_WRITE_ENABLE_OUT: out std_logic;
-      DAT_DATA_OUT        : out std_logic_vector(REGISTER_WIDTH-1 downto 0);
-      --Data input can only be used as reaction on read or write access. write operation should return data
-      --if successful
-      DAT_DATA_IN         : in  std_logic_vector(REGISTER_WIDTH-1 downto 0);
-      DAT_DATAREADY_IN    : in std_logic;
-      DAT_NO_MORE_DATA_IN : in std_logic
-        --To finish transmission, when reading from a fifo and it got empty
-      );
+  generic (
+    REGISTER_WIDTH     : integer range 32 to 32 := 32;
+    ADDRESS_WIDTH      : integer range 8 to 16 := 16;
+    NUM_STAT_REGS      : integer range 0 to 6 := 3; --log2 of number of status registers
+    NUM_CTRL_REGS      : integer range 0 to 6 := 3; --log2 of number of ctrl registers
+    --standard values for output registers
+    INIT_CTRL_REGS     : std_logic_vector(2**(3)*32-1 downto 0) :=
+            (others => '0');
+    --set to 0 for unused ctrl registers to save resources
+    USED_CTRL_REGS     : std_logic_vector(2**(3)-1 downto 0)   := "00000001";
+    --set to 0 for each unused bit in a register
+    USED_CTRL_BITMASK  : std_logic_vector(2**(3)*32-1 downto 0) :=
+            (others => '1');
+    --no data / address out?
+    NO_DAT_PORT        : std_logic := '0';
+
+    INIT_ADDRESS       : std_logic_vector(15 downto 0) := x"FFFF";
+    INIT_UNIQUE_ID     : std_logic_vector(95 downto 0) := (others => '0');
+    COMPILE_TIME       : std_logic_vector(31 downto 0) := x"00000000";
+    COMPILE_VERSION    : std_logic_vector(15 downto 0) := x"0001";
+    HARDWARE_VERSION   : std_logic_vector(31 downto 0) := x"12345678"
+    );
+  port(
+  --  Misc
+    CLK    : in std_logic;
+    RESET  : in std_logic;
+    CLK_EN : in std_logic;
+  -- Port to API
+    API_DATA_OUT           : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
+    API_PACKET_NUM_OUT     : out std_logic_vector (c_NUM_WIDTH-1  downto 0);
+    API_DATAREADY_OUT      : out std_logic;
+    API_READ_IN            : in  std_logic;
+    API_SHORT_TRANSFER_OUT : out std_logic;
+    API_DTYPE_OUT          : out std_logic_vector (3 downto 0);
+    API_ERROR_PATTERN_OUT  : out std_logic_vector (31 downto 0);
+    API_SEND_OUT           : out std_logic;
+    API_TARGET_ADDRESS_OUT : out std_logic_vector (15 downto 0);
+    -- Receiver port
+    API_DATA_IN         : in  std_logic_vector (c_DATA_WIDTH-1 downto 0);
+    API_PACKET_NUM_IN   : in  std_logic_vector (c_NUM_WIDTH-1  downto 0);
+    API_TYP_IN          : in  std_logic_vector (2 downto 0);
+    API_DATAREADY_IN    : in  std_logic;
+    API_READ_OUT        : out std_logic;
+    -- APL Control port
+    API_RUN_IN          : in  std_logic;
+    API_SEQNR_IN        : in  std_logic_vector (7 downto 0);
+
+    --Port to write Unique ID
+    IDRAM_DATA_IN       : in  std_logic_vector(15 downto 0);
+    IDRAM_DATA_OUT      : out std_logic_vector(15 downto 0);
+    IDRAM_ADDR_IN       : in  std_logic_vector(2 downto 0);
+    IDRAM_WR_IN         : in  std_logic;
+
+
+    MY_ADDRESS_OUT      : out std_logic_vector(15 downto 0);
+
+  --Common Register in / out
+    COMMON_STAT_REG_IN   : in  std_logic_vector(std_COMSTATREG*32-1 downto 0);
+    COMMON_CTRL_REG_OUT  : out std_logic_vector(std_COMCTRLREG*32-1 downto 0);
+
+  --Custom Register in / out
+    REGISTERS_IN        : in  std_logic_vector(REGISTER_WIDTH*2**(NUM_STAT_REGS)-1 downto 0);
+    REGISTERS_OUT       : out std_logic_vector(REGISTER_WIDTH*2**(NUM_CTRL_REGS)-1 downto 0);
+
+  --following ports only used when no internal register is accessed
+    DAT_ADDR_OUT        : out std_logic_vector(ADDRESS_WIDTH-1 downto 0);
+    DAT_READ_ENABLE_OUT : out std_logic;
+    DAT_WRITE_ENABLE_OUT: out std_logic;
+    DAT_DATA_OUT        : out std_logic_vector(REGISTER_WIDTH-1 downto 0);
+    --Data input can only be used as reaction on read or write access. write operation should return data
+    --if successful
+    DAT_DATA_IN         : in  std_logic_vector(REGISTER_WIDTH-1 downto 0);
+    DAT_DATAREADY_IN    : in std_logic;
+    DAT_NO_MORE_DATA_IN : in std_logic;
+      --To finish transmission, when reading from a fifo and it got empty
+    STAT : out std_logic_vector(31 downto 0)
+    );
   end component;
   
   component trb_net16_term_buf is
@@ -1145,7 +1158,10 @@ HUB_MED_CONNECTED(31 downto MII_NUMBER) <= (others => '1');
                             x"FFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF",
       NO_DAT_PORT        => '1',
       INIT_ADDRESS       => INIT_ADDRESS,
-      INIT_UNIQUE_ID     => INIT_UNIQUE_ID
+      INIT_UNIQUE_ID     => INIT_UNIQUE_ID,
+      COMPILE_TIME       => COMPILE_TIME,
+      COMPILE_VERSION    => COMPILE_VERSION,
+      HARDWARE_VERSION   => HARDWARE_VERSION
       )
     port map(
       CLK    => CLK,
@@ -1173,6 +1189,8 @@ HUB_MED_CONNECTED(31 downto MII_NUMBER) <= (others => '1');
       MY_ADDRESS_OUT      => HUB_ADDRESS,
       REGISTERS_IN        => HC_STAT_REGS,
       REGISTERS_OUT       => HC_CTRL_REGS,
+      COMMON_STAT_REG_IN  => HC_STAT_REGS(63 downto 0),
+      COMMON_CTRL_REG_OUT => open,
       --Port to write Unique ID
       IDRAM_DATA_IN       => IDRAM_DATA_IN,
       IDRAM_DATA_OUT      => open,