add iD lines, I2C, update identification registers

diff --git a/DBO/config.vhd b/DBO/config.vhd
index 45bf24947b7b017e8ff00e4337057d22e1e99576..c7abcfdc0225f2cd9ee9f4f9aa4e1b00f03f9883 100644 (file)
--- a/DBO/config.vhd
+++ b/DBO/config.vhd
@@ -36,7 +36,6 @@ package config is
     constant INCLUDE_SPI            : integer  := c_NO; --300 slices
     constant INCLUDE_ADC            : integer  := c_NO; 
     constant INCLUDE_I2C            : integer  := c_NO; 
-    constant INCLUDE_LCD            : integer  := c_NO; --800 slices
     constant INCLUDE_DEBUG_INTERFACE: integer  := c_NO; --300 slices
 
     --input monitor and trigger generation logic
@@ -50,10 +49,6 @@ package config is
 --End of design configuration
 ------------------------------------------------------------------------------
 
-
-  type data_t is array (0 to 1023) of std_logic_vector(7 downto 0);
-  constant LCD_DATA : data_t := (others => x"00");
-
 ------------------------------------------------------------------------------
 --Select settings by configuration 
 ------------------------------------------------------------------------------
@@ -85,15 +80,13 @@ function generateIncludedFeatures return std_logic_vector is
     t(63 downto 56) := std_logic_vector(to_unsigned(2,8)); --table version 1
 
     t(7 downto 0)   := std_logic_vector(to_unsigned(1,8));
---     t(11 downto 8)  := std_logic_vector(to_unsigned(DOUBLE_EDGE_TYPE,4));
---     t(14 downto 12) := std_logic_vector(to_unsigned(RING_BUFFER_SIZE,3));
+    t(11 downto 8)  := std_logic_vector(to_unsigned(5,4));  --clock TDC double edge, same channel, no stretcher
+    t(14 downto 12) := std_logic_vector(to_unsigned(0,3));
     t(15)           := '1'; --TDC
-    t(17 downto 16) := "00";
-    
-    t(40 downto 40) := std_logic_vector(to_unsigned(INCLUDE_LCD,1));
     t(42 downto 42) := std_logic_vector(to_unsigned(INCLUDE_SPI,1));
     t(43 downto 43) := std_logic_vector(to_unsigned(INCLUDE_UART,1));
     t(44 downto 44) := std_logic_vector(to_unsigned(INCLUDE_STATISTICS,1));
+    t(47 downto 47) := std_logic_vector(to_unsigned(INCLUDE_I2C,1));
     t(51 downto 48) := std_logic_vector(to_unsigned(INCLUDE_TRIGGER_LOGIC,4));
     t(52 downto 52) := std_logic_vector(to_unsigned(USE_120_MHZ,1));
     t(53 downto 53) := std_logic_vector(to_unsigned(USE_RXCLOCK,1));

diff --git a/DBO/mdctdc.prj b/DBO/mdctdc.prj
index 2b7559d7c014555730f45c68a40295fd92bf1de9..30ace65ba61ee2275c789e808fa89e73df7b4931 100644 (file)
--- a/DBO/mdctdc.prj
+++ b/DBO/mdctdc.prj
@@ -148,7 +148,6 @@ add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd"
 add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd"
 add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd"
 add_file -vhdl -lib work "../../trb3sc/code/trb3sc_tools.vhd"
-add_file -vhdl -lib work "../../trb3sc/code/lcd.vhd"
 add_file -vhdl -lib work "../../trb3sc/code/debuguart.vhd"
 add_file -vhdl -lib work "../../trbnet/special/uart.vhd"
 add_file -vhdl -lib work "../../trbnet/special/uart_rec.vhd"

diff --git a/DBO/mdctdc.vhd b/DBO/mdctdc.vhd
index f6318e130580792f4ed30f56090850f6c5869c14..05194b973607be00854448518a2fc81e92638064 100644 (file)
--- a/DBO/mdctdc.vhd
+++ b/DBO/mdctdc.vhd
@@ -23,6 +23,7 @@ entity mdctdc is
     TEST : out std_logic_vector(3 downto 0);
     INJ  : out std_logic_vector(3 downto 0);
     PTEN : out std_logic_vector(2 downto 1);
+    ID   : in  std_logic_vector(1 downto 0);
 
     RSTN  : out std_logic_vector(2 downto 1);
     MISO  : in  std_logic_vector(2 downto 1);
@@ -171,6 +172,7 @@ begin
       REGIO_INIT_ENDPOINT_ID    => x"0001",
       REGIO_USE_1WIRE_INTERFACE => c_I2C,
       TIMING_TRIGGER_RAW        => c_YES,
+      REGIO_USE_VAR_ENDPOINT_ID => c_YES,
       --Configure data handler
       DATA_INTERFACE_NUMBER     => 2,
       DATA_BUFFER_DEPTH         => EVENT_BUFFER_SIZE,
@@ -209,6 +211,8 @@ begin
       ONEWIRE_INOUT => open,
       I2C_SCL       => I2C_SCL,
       I2C_SDA       => I2C_SDA,
+      REGIO_VAR_ENDPOINT_ID(15 downto 2) => (others => '0'),
+      REGIO_VAR_ENDPOINT_ID(1 downto 0)  => ID,
       --Timing registers
       TIMERS_OUT    => timer
       );

diff --git a/OEP/config.vhd b/OEP/config.vhd
index da98f267f491f17887b7e118ee24e8bf070c6065..76e637383ddaa486b23df541932da28fd6ca5486 100644 (file)
--- a/OEP/config.vhd
+++ b/OEP/config.vhd
@@ -28,7 +28,7 @@ package config is
     constant INCLUDE_UART           : integer  := c_NO;
     constant INCLUDE_SPI            : integer  := c_NO;
     constant INCLUDE_ADC            : integer  := c_YES;
-    constant INCLUDE_I2C            : integer  := c_NO; 
+    constant INCLUDE_I2C            : integer  := c_YES; 
     constant INCLUDE_DEBUG_INTERFACE: integer  := c_NO; 
 
     --input monitor and trigger generation logic
@@ -80,6 +80,7 @@ function generateIncludedFeatures return std_logic_vector is
     t(42 downto 42) := std_logic_vector(to_unsigned(INCLUDE_SPI,1));
     t(43 downto 43) := std_logic_vector(to_unsigned(INCLUDE_UART,1));
     t(44 downto 44) := std_logic_vector(to_unsigned(INCLUDE_STATISTICS,1));
+    t(47 downto 47) := std_logic_vector(to_unsigned(INCLUDE_I2C,1));
     t(51 downto 48) := std_logic_vector(to_unsigned(INCLUDE_TRIGGER_LOGIC,4));
     t(53 downto 53) := std_logic_vector(to_unsigned(USE_RXCLOCK,1));
     return t;

diff --git a/OEP/config_compile_frankfurt.pl b/OEP/config_compile_frankfurt.pl
index 310aee42a120a5f8cd6c0006f7d580f6d92573d3..de5e337a39d06cbe518b70f4390b79eb7688cbc0 100644 (file)
--- a/OEP/config_compile_frankfurt.pl
+++ b/OEP/config_compile_frankfurt.pl
@@ -10,7 +10,7 @@ lm_license_file_for_par      => "1702\@jspc29",
 lattice_path                 => '/d/jspc29/lattice/diamond/3.12',
 synplify_path                => '/d/jspc29/lattice/synplify/S-2021.09-SP2/',
 
-nodelist_file                => '../nodelist_frankfurt.txt',
+nodelist_file                => 'nodelist_frankfurt.txt',
 pinout_file                  => 'oep',
 par_options                  => '../par.p2t',
 

diff --git a/OEP/mdcoep.prj b/OEP/mdcoep.prj
index 3ac56e69fb1b1a3d48bee9a7b31461d320060268..4523d84b4caa0c8e6c9679b80d617447ac6f1a3e 100644 (file)
--- a/OEP/mdcoep.prj
+++ b/OEP/mdcoep.prj
@@ -103,7 +103,7 @@ add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd"
 add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd"
 add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd"
 add_file -vhdl -lib work "../../trb3sc/code/trb3sc_tools.vhd"
-
+add_file -vhdl -lib work "../../trb3sc/code/common_i2c.vhd"
 add_file -vhdl -lib work "../../trb3sc/code/debuguart.vhd"
 add_file -vhdl -lib work "../../trbnet/special/uart.vhd"
 add_file -vhdl -lib work "../../trbnet/special/uart_rec.vhd"
@@ -212,6 +212,9 @@ add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_gstart.vhd"
 add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_sendb.vhd"
 add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_slim.vhd"
 
+add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_gstart2.vhd"
+add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_sendb2.vhd"
+add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_slim2.vhd"
 
 add_file -vhdl -lib work "./mdcoep.vhd"
 #add_file -fpga_constraint "./synplify.fdc"

diff --git a/OEP/mdcoep.vhd b/OEP/mdcoep.vhd
index 1a97f6b5b6ffaaf23201f5dde5813e46aefbbc55..f2c9e479f8d0b80879aac04bd86008da5bdeccf5 100644 (file)
--- a/OEP/mdcoep.vhd
+++ b/OEP/mdcoep.vhd
@@ -38,6 +38,8 @@ entity mdcoep is
     SFP_LOS      : in    std_logic;
     SFP_TX_DIS   : out   std_logic;
     SFP_MOD0     : in    std_logic;
+    SFP_MOD1     : inout std_logic;
+    SFP_MOD2     : inout std_logic;
     
     ADC_MISO     : in    std_logic;
     ADC_MOSI     : out   std_logic;
@@ -216,7 +218,7 @@ begin
       USE_ONEWIRE         => c_I2C,
       HARDWARE_VERSION    => HARDWARE_INFO,
       INCLUDED_FEATURES   => INCLUDED_FEATURES,
-      INIT_ENDPOINT_ID    => x"0001",
+      INIT_ENDPOINT_ID    => x"0005",
       INIT_CTRL_REGS      => x"00000000_00000000_00000000_00000000" &
                              x"00000000_00000000_00000000_00000000" &
                              x"00000000_00000000_800a4000_00000000" &
@@ -343,13 +345,16 @@ begin
       SPI_MISO_IN       => open,
       SPI_CLK_OUT       => open,
       --Header
-      HEADER_IO         => open,
+      --HEADER_IO         => open,
       ADDITIONAL_REG    => additional_reg,
       --ADC
       ADC_CS            => ADC_CS,
       ADC_MOSI          => ADC_MOSI,
       ADC_MISO          => ADC_MISO,
       ADC_CLK           => ADC_SCK,
+      --I2C
+      HEADER_IO(7)      => SFP_MOD2,
+      HEADER_IO(8)      => SFP_MOD1,      
       --Trigger & Monitor 
       MONITOR_INPUTS    => monitor_inputs_i,
       TRIG_GEN_INPUTS   => trigger_inputs_i,

diff --git a/pinout/dbo.lpf b/pinout/dbo.lpf
index 05713326c63219d80aff6d4d5a55896f933bcafd..d32d6d04f0b93372509820bbbb56ed45d7f2f42c 100644 (file)
--- a/pinout/dbo.lpf
+++ b/pinout/dbo.lpf
@@ -31,6 +31,12 @@ LOCATE COMP "GPIO_3" SITE "B16";
 DEFINE PORT GROUP "GPIO_group" "GPIO*";\r
 IOBUF GROUP "GPIO_group" IO_TYPE=LVCMOS25 ;\r
 \r
+LOCATE COMP "ID_0" SITE "R1";\r
+LOCATE COMP "ID_1" SITE "T1";\r
+DEFINE PORT GROUP "ID_group" "ID*";\r
+IOBUF GROUP "ID_group" IO_TYPE=LVCMOS25 PULLMODE=UP;\r
+\r
+\r
 LOCATE COMP "I2C_SCL" SITE "A17";\r
 LOCATE COMP "I2C_SDA" SITE "A18";\r
 IOBUF PORT "I2C_SCL" IO_TYPE=LVCMOS25 ;\r

diff --git a/pinout/oep.lpf b/pinout/oep.lpf
index 655fa65d4fa0e0a45a1d6588aaa6d12e9e8af51e..7686d078a442eaef8fd7b64242bd8669b99e2353 100644 (file)
--- a/pinout/oep.lpf
+++ b/pinout/oep.lpf
@@ -88,6 +88,8 @@ IOBUF PORT "LONG_SHORT" IO_TYPE=LVCMOS25 PULLMODE=UP;
 LOCATE COMP "SFP_LOS" SITE "A7";\r
 LOCATE COMP "SFP_TX_DIS" SITE "A8";\r
 LOCATE COMP "SFP_MOD0" SITE "B9";\r
+LOCATE COMP "SFP_MOD1" SITE "A10";\r
+LOCATE COMP "SFP_MOD2" SITE "B11";\r
 DEFINE PORT GROUP "SFP_group" "SFP*";\r
 IOBUF GROUP "SFP_group" IO_TYPE=LVCMOS25 ;\r
 \r