entity shutdown_indv is
-
port(
clk_in : in std_logic;
signal_in : in std_logic;
int_time : in std_logic_vector (31 downto 0);
max_count : in std_logic_vector (31 downto 0);
current_hits_vctr : out std_logic_vector (31 downto 0);
+ reset_pulse : out std_logic;
processed_signal : out std_logic
);
end shutdown_indv;
signal finalout : std_logic;
-- signal temp_save2 : std_logic;
signal temp_out : std_logic;
-signal reset_pulse : std_logic;
+signal reset_pulse_i : std_logic;
signal reset_hitcounter : std_logic;
signal reset_timecounter : std_logic;
max_hitcount <= unsigned(max_count(31 downto 0));
current_hits_vctr <= std_logic_vector(hitteller);
-- hitsaver <= hitcounter;
-
+ reset_pulse <= reset_pulse_i;
PROC_SAFETYOFF: process begin -- stops the entity from sending signals before there are values recieved from the bussystem
wait until rising_edge(clk_in);
end if;
end process;
+
EDGEDETECT: process is
begin
wait until rising_edge(clk_in);
finalout <= '1';
else
finalout <='0';
-end if;
-
+end if;
end process;
+
HITCOUNT: process is
begin
wait until rising_edge(clk_in);
-if reset_pulse='1' then
+if reset_pulse_i='1' then
hitcounter <= x"00000000";
elsif temp_save1='1' and temp_save2='0' then
hitcounter<= hitcounter+1;
end if;
end process;
+
POC_OUTPUT: process begin
wait until rising_edge(clk_in);
-if reset_pulse='1' then
+if reset_pulse_i='1' then
hitteller <= hitsaver;
if temp_out = '1' then
-- temp_out<='0';
wait until rising_edge(clk_in);
if timecounter >= integration_time_int then -- changed from = so it doesnt softlock in between < and >
- reset_pulse <= '1';
+ reset_pulse_i <= '1';
timecounter <= x"00000000";
elsif timecounter < integration_time_int and ms_pulse='1' then
timecounter <= timecounter +1;
- reset_pulse <= '0';
+ reset_pulse_i <= '0';
else
- reset_pulse <= '0';
+ reset_pulse_i <= '0';
end if;
end process;
signal shutdown_signal: std_logic;
-- signal shutdown_signal:std_logic_vector(OUTPUTS-1 downto 0);
+-- Signals for the Monitoring/Fifo
+signal fifo_writesignal: std_logic_vector(INPUTS-1 downto 0);
+signal man_readFlag: std_logic_vector(31 downto 0);
+signal read_mem_Flag: std_logic_vector(INPUTS-1 downto 0);
+
+-- signal store_values : Array32bit:=(others => (others => '0'));
+signal plot_values : Array32bit:=(others => (others => '0'));
+
-- hand over the signals between entities
signal in_2_indiv :std_logic_vector(INPUTS-1 downto 0);
elsif BUS_RX.addr(11 downto 8) = x"6" then
BUS_TX.data <= register_onoff;
elsif BUS_RX.addr(11 downto 8) = x"7" then
- BUS_TX.data <= signal_register;
+ BUS_TX.data <= signal_register;
+
+ elsif BUS_RX.addr(11 downto 8) = x"8" then
+-- intersting stuff happening here
+ -- read Enable of FiFo set to '1'
+
+-- read_mem_Flag <= x"FFFFF"; -- do i need a whole vector, is 1 bit enugh ?
+ -- end of interesting stuff
+ if address_i < INPUTS then
+ BUS_TX.data <= plot_values(address_i);
+ read_mem_Flag(address_i) <= '1';
+ else
+ BUS_TX.ack <= '0'; BUS_TX.unknown <= '1' ;
+ end if;
+ elsif BUS_RX.addr(11 downto 8) = x"9" then
+ -- to set manually in order to stop all loading of the fifos
+ BUS_TX.data <= man_readFlag; -- 1 bit def. enough here
else BUS_TX.ack <= '0'; BUS_TX.unknown <= '1';
end if;
-
+
elsif BUS_RX.write = '1' then --WRITE
BUS_TX.ack <= '1';
if BUS_RX.addr(11 downto 8) = x"0" then
disableReg_compare <= BUS_RX.data;
elsif BUS_RX.addr(11 downto 8) = x"6" then -- write the preset Value of ON/OFF in the boards register
register_onoff <= BUS_RX.data;
+
+ elsif BUS_RX.addr(11 downto 8) = x"9" then
+ man_readFlag <= BUS_RX.data;
else BUS_TX.ack <= '0'; BUS_TX.unknown <= '1';
end if;
end if;
int_time => stretch_time(i),
max_count => max_count(i),
processed_signal => indiv_2_comp(i),
+ reset_pulse => fifo_writesignal(i),
current_hits_vctr => current_count(i)
);
end generate;
processed_signal => comp_2_out
);
+
+
+
+GEN_MONITOR: for i in 0 to INPUTS-1 generate
+THE_MONITOR: entity work.shutdown_mon
+
+ port map(
+ clk_in => CLK,
+-- disable_reg => disableReg_monitor,
+ reset => RESET,
+ hitvalue => current_count(i),
+ writeFlag => fifo_writesignal(i),
+ read_cmd => read_mem_Flag(i), -- automatic Read Flag
+ read_global => man_readFlag(i), -- manuell Read Flag
+ output_val => plot_values(i)
+
+ );
+end generate;
end architecture;
--- /dev/null
+library ieee;
+ use ieee.std_logic_1164.all;
+ use ieee.numeric_std.all;
+
+library work;
+ use work.trb_net_std.all;
+
+
+
+entity shutdown_mon is
+-- declade all incoming signals
+ port(
+ clk_in : in std_logic;
+-- disable_reg : in std_logic;
+ reset : in std_logic;
+ hitvalue : in std_logic_vector (31 downto 0);
+ writeFlag : in std_logic;
+ read_cmd : in std_logic; --coming from BUS_RX.read '1'
+ read_global : in std_logic; --coming from register/manually
+ output_val : out std_logic_vector (31 downto 0)
+ );
+end shutdown_mon;
+
+architecture behave of shutdown_mon is
+signal threshValue: std_logic_vector(9 downto 0):= "1111101000";
+signal data_2_fifo: std_logic_vector (31 downto 0);
+signal writesignal: std_logic;
+signal readsignal: std_logic:='0';
+signal amFull: std_logic;
+signal last_amFull: std_logic;
+signal allow_write: std_logic;
+signal waiter: std_logic;
+signal in_2_fifo: std_logic_vector (35 downto 0):= x"000000000";
+signal timer: unsigned(15 downto 0):= x"0000";
+-- signal reset_i: std_logic:='0';
+signal output_val_handler: std_logic_vector (35 downto 0);
+
+begin
+data_2_fifo <= hitvalue;
+output_val <= output_val_handler(31 downto 0);
+in_2_fifo(31 downto 0) <= hitvalue;
+
+
+PROC_FIFOREAD: process is
+-- stop everything if readflag is high
+begin
+ wait until rising_edge(clk_in);
+
+ if read_global='1' then
+ allow_write <= '0'; -- need to change
+
+ else
+ allow_write <= '1';
+
+end if;
+end process;
+
+
+
+PROC_FIFOWRTITE: process is
+-- only write if the write flag is active
+begin
+ wait until rising_edge(clk_in);
+
+ if allow_write = '1' then
+ if writeFlag='1' then
+ writesignal <= '1';
+-- in_2_fifo(31 downto 0) <= hitvalue;
+-- in_2_fifo(35 downto 32) <= x"0";
+ else
+ writesignal <= '0';
+ end if;
+
+
+ end if;
+end process;
+
+
+
+
+PROC_COMBINEDREAD: process is
+begin
+ wait until rising_edge(clk_in);
+ last_amFull <= amFull;
+ if allow_write = '0' then
+ if read_cmd ='1' then
+ readsignal <= '1';
+ elsif amFull ='1' and last_amFull='0' then
+ readsignal <='1';
+ else
+ readsignal <='0';
+ end if;
+ end if;
+end process;
+
+
+
+
+
+-- PROC_FIFOCLEAN: process is
+-- -- wenn Almost full is TRUE--> start to read once and then wait for a couple cycles
+-- begin
+-- wait until rising_edge(clk_in);
+-- if alertflag = '1' and waiter ='0' then
+-- readsignal <= '1';
+-- waiter <='1';
+-- else
+-- readsignal <= '0';
+-- end if;
+--
+-- end process;
+--
+--
+-- PROC_RESET: process is
+-- begin
+-- wait until rising_edge(clk_in);
+-- if waiter = '1' and timer = x"0100" then
+-- waiter <= '0';
+-- timer <= x"0000";
+-- elsif waiter ='1' and timer < x"0500" then
+-- timer <= timer + 1;
+-- end if;
+--
+-- end process;
+
+
+
+THE_FIFO: entity work.fifo_36x1k_oreg
+ port map(
+ Data => in_2_fifo, -- Data: in std_logic_vector(35 downto 0);
+ Clock => clk_in, -- Clock: in std_logic;
+ WrEn => writesignal, -- WrEn: in std_logic;
+ RdEn => readsignal, -- RdEn: in std_logic;
+ Reset => reset, -- Reset: in std_logic;
+ AmFullThresh=> threshValue, -- AmFullThresh: in std_logic_vector(9 downto 0);
+ Q => output_val_handler, -- Q: out std_logic_vector(35 downto 0);
+-- WCNT => -- WCNT: out std_logic_vector(10 downto 0);
+-- Empty =>-- Empty: out std_logic;
+-- Full =>-- Full: out std_logic;
+ AlmostFull => amFull -- AlmostFull: out std_logic);
+ );
+end behave;
+
+
+
+
+
+
add_file -vhdl -lib work "../../trb3sc/shutdownlogic/code/shutdown_logic.vhd"
add_file -vhdl -lib work "../../trb3sc/shutdownlogic/code/shutdown_individual.vhd"
add_file -vhdl -lib work "../../trb3sc/shutdownlogic/code/shutdown_compare.vhd"
+add_file -vhdl -lib work "../../trb3sc/shutdownlogic/code/shutdown_monitoring.vhd"
#TrbNet Endpoint
jspc29 / trb3sc.git / commitdiff