-- VHDL netlist generated by SCUBA Diamond_2.0_Production (151)
-- Module Version: 4.8
---/usr/local/opt/lattice_diamond/diamond/2.0/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 64 -width 32 -depth 64 -regout -no_enable -pe -1 -pf -1 -e
+--/usr/local/opt/lattice_diamond/diamond/2.0/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 1024 -width 32 -depth 1024 -regout -no_enable -pe -1 -pf -1 -e
--- Sun Dec 2 17:35:19 2012
+-- Thu Dec 6 21:58:22 2012
library IEEE;
use IEEE.std_logic_1164.all;
signal ifcount_5: std_logic;
signal co1: std_logic;
signal ifcount_6: std_logic;
+ signal ifcount_7: std_logic;
+ signal co2: std_logic;
+ signal ifcount_8: std_logic;
+ signal ifcount_9: std_logic;
signal co3: std_logic;
+ signal ifcount_10: std_logic;
+ signal co5: std_logic;
signal cnt_con: std_logic;
- signal co2: std_logic;
+ signal co4: std_logic;
signal cmp_ci: std_logic;
signal rden_i: std_logic;
signal co0_1: std_logic;
signal co1_1: std_logic;
signal co2_1: std_logic;
+ signal co3_1: std_logic;
+ signal co4_1: std_logic;
signal cmp_le_1: std_logic;
signal cmp_le_1_c: std_logic;
signal cmp_ci_1: std_logic;
signal fcount_2: std_logic;
signal fcount_3: std_logic;
signal co1_2: std_logic;
- signal wren_i: std_logic;
signal fcount_4: std_logic;
signal fcount_5: std_logic;
signal co2_2: std_logic;
- signal wren_i_inv: std_logic;
signal fcount_6: std_logic;
+ signal fcount_7: std_logic;
+ signal co3_2: std_logic;
+ signal wren_i: std_logic;
+ signal fcount_8: std_logic;
+ signal fcount_9: std_logic;
+ signal co4_2: std_logic;
+ signal wren_i_inv: std_logic;
+ signal fcount_10: std_logic;
signal cmp_ge_d1: std_logic;
signal cmp_ge_d1_c: std_logic;
signal iwcount_0: std_logic;
signal wcount_5: std_logic;
signal co1_3: std_logic;
signal iwcount_6: std_logic;
- signal co3_1: std_logic;
+ signal iwcount_7: std_logic;
signal wcount_6: std_logic;
+ signal wcount_7: std_logic;
signal co2_3: std_logic;
+ signal iwcount_8: std_logic;
+ signal iwcount_9: std_logic;
+ signal wcount_8: std_logic;
+ signal wcount_9: std_logic;
+ signal co3_3: std_logic;
+ signal iwcount_10: std_logic;
+ signal co5_1: std_logic;
+ signal wcount_10: std_logic;
+ signal co4_3: std_logic;
signal scuba_vhi: std_logic;
signal ircount_0: std_logic;
signal ircount_1: std_logic;
signal rcount_5: std_logic;
signal co1_4: std_logic;
signal ircount_6: std_logic;
- signal co3_2: std_logic;
+ signal ircount_7: std_logic;
signal rcount_6: std_logic;
- signal scuba_vlo: std_logic;
+ signal rcount_7: std_logic;
signal co2_4: std_logic;
+ signal ircount_8: std_logic;
+ signal ircount_9: std_logic;
+ signal rcount_8: std_logic;
+ signal rcount_9: std_logic;
+ signal co3_4: std_logic;
+ signal ircount_10: std_logic;
+ signal co5_2: std_logic;
+ signal rcount_10: std_logic;
+ signal scuba_vlo: std_logic;
+ signal co4_4: std_logic;
-- local component declarations
component AGEB2
component XOR2
port (A: in std_logic; B: in std_logic; Z: out std_logic);
end component;
- component PDPW16KC
- generic (GSR : in String; CSDECODE_R : in String;
- CSDECODE_W : in String; REGMODE : in String;
- DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer);
- port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic;
- DI3: in std_logic; DI4: in std_logic; DI5: in std_logic;
- DI6: in std_logic; DI7: in std_logic; DI8: in std_logic;
- DI9: in std_logic; DI10: in std_logic; DI11: in std_logic;
- DI12: in std_logic; DI13: in std_logic;
- DI14: in std_logic; DI15: in std_logic;
- DI16: in std_logic; DI17: in std_logic;
- DI18: in std_logic; DI19: in std_logic;
- DI20: in std_logic; DI21: in std_logic;
- DI22: in std_logic; DI23: in std_logic;
- DI24: in std_logic; DI25: in std_logic;
- DI26: in std_logic; DI27: in std_logic;
- DI28: in std_logic; DI29: in std_logic;
- DI30: in std_logic; DI31: in std_logic;
- DI32: in std_logic; DI33: in std_logic;
- DI34: in std_logic; DI35: in std_logic;
- ADW0: in std_logic; ADW1: in std_logic;
- ADW2: in std_logic; ADW3: in std_logic;
- ADW4: in std_logic; ADW5: in std_logic;
- ADW6: in std_logic; ADW7: in std_logic;
- ADW8: in std_logic; BE0: in std_logic; BE1: in std_logic;
- BE2: in std_logic; BE3: in std_logic; CEW: in std_logic;
- CLKW: in std_logic; CSW0: in std_logic;
- CSW1: in std_logic; CSW2: in std_logic;
- ADR0: in std_logic; ADR1: in std_logic;
- ADR2: in std_logic; ADR3: in std_logic;
- ADR4: in std_logic; ADR5: in std_logic;
- ADR6: in std_logic; ADR7: in std_logic;
- ADR8: in std_logic; ADR9: in std_logic;
- ADR10: in std_logic; ADR11: in std_logic;
- ADR12: in std_logic; ADR13: in std_logic;
- CER: in std_logic; CLKR: in std_logic; CSR0: in std_logic;
- CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic;
- DO0: out std_logic; DO1: out std_logic;
- DO2: out std_logic; DO3: out std_logic;
- DO4: out std_logic; DO5: out std_logic;
- DO6: out std_logic; DO7: out std_logic;
- DO8: out std_logic; DO9: out std_logic;
- DO10: out std_logic; DO11: out std_logic;
- DO12: out std_logic; DO13: out std_logic;
- DO14: out std_logic; DO15: out std_logic;
- DO16: out std_logic; DO17: out std_logic;
- DO18: out std_logic; DO19: out std_logic;
- DO20: out std_logic; DO21: out std_logic;
- DO22: out std_logic; DO23: out std_logic;
- DO24: out std_logic; DO25: out std_logic;
- DO26: out std_logic; DO27: out std_logic;
- DO28: out std_logic; DO29: out std_logic;
- DO30: out std_logic; DO31: out std_logic;
- DO32: out std_logic; DO33: out std_logic;
- DO34: out std_logic; DO35: out std_logic);
+ component DP16KC
+ generic (GSR : in String; WRITEMODE_B : in String;
+ WRITEMODE_A : in String; CSDECODE_B : in String;
+ CSDECODE_A : in String; REGMODE_B : in String;
+ REGMODE_A : in String; DATA_WIDTH_B : in Integer;
+ DATA_WIDTH_A : in Integer);
+ port (DIA0: in std_logic; DIA1: in std_logic;
+ DIA2: in std_logic; DIA3: in std_logic;
+ DIA4: in std_logic; DIA5: in std_logic;
+ DIA6: in std_logic; DIA7: in std_logic;
+ DIA8: in std_logic; DIA9: in std_logic;
+ DIA10: in std_logic; DIA11: in std_logic;
+ DIA12: in std_logic; DIA13: in std_logic;
+ DIA14: in std_logic; DIA15: in std_logic;
+ DIA16: in std_logic; DIA17: in std_logic;
+ ADA0: in std_logic; ADA1: in std_logic;
+ ADA2: in std_logic; ADA3: in std_logic;
+ ADA4: in std_logic; ADA5: in std_logic;
+ ADA6: in std_logic; ADA7: in std_logic;
+ ADA8: in std_logic; ADA9: in std_logic;
+ ADA10: in std_logic; ADA11: in std_logic;
+ ADA12: in std_logic; ADA13: in std_logic;
+ CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic;
+ WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic;
+ CSA2: in std_logic; RSTA: in std_logic;
+ DIB0: in std_logic; DIB1: in std_logic;
+ DIB2: in std_logic; DIB3: in std_logic;
+ DIB4: in std_logic; DIB5: in std_logic;
+ DIB6: in std_logic; DIB7: in std_logic;
+ DIB8: in std_logic; DIB9: in std_logic;
+ DIB10: in std_logic; DIB11: in std_logic;
+ DIB12: in std_logic; DIB13: in std_logic;
+ DIB14: in std_logic; DIB15: in std_logic;
+ DIB16: in std_logic; DIB17: in std_logic;
+ ADB0: in std_logic; ADB1: in std_logic;
+ ADB2: in std_logic; ADB3: in std_logic;
+ ADB4: in std_logic; ADB5: in std_logic;
+ ADB6: in std_logic; ADB7: in std_logic;
+ ADB8: in std_logic; ADB9: in std_logic;
+ ADB10: in std_logic; ADB11: in std_logic;
+ ADB12: in std_logic; ADB13: in std_logic;
+ CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic;
+ WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic;
+ CSB2: in std_logic; RSTB: in std_logic;
+ DOA0: out std_logic; DOA1: out std_logic;
+ DOA2: out std_logic; DOA3: out std_logic;
+ DOA4: out std_logic; DOA5: out std_logic;
+ DOA6: out std_logic; DOA7: out std_logic;
+ DOA8: out std_logic; DOA9: out std_logic;
+ DOA10: out std_logic; DOA11: out std_logic;
+ DOA12: out std_logic; DOA13: out std_logic;
+ DOA14: out std_logic; DOA15: out std_logic;
+ DOA16: out std_logic; DOA17: out std_logic;
+ DOB0: out std_logic; DOB1: out std_logic;
+ DOB2: out std_logic; DOB3: out std_logic;
+ DOB4: out std_logic; DOB5: out std_logic;
+ DOB6: out std_logic; DOB7: out std_logic;
+ DOB8: out std_logic; DOB9: out std_logic;
+ DOB10: out std_logic; DOB11: out std_logic;
+ DOB12: out std_logic; DOB13: out std_logic;
+ DOB14: out std_logic; DOB15: out std_logic;
+ DOB16: out std_logic; DOB17: out std_logic);
end component;
attribute MEM_LPC_FILE : string;
attribute MEM_INIT_FILE : string;
attribute RESETMODE : string;
attribute GSR : string;
- attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "fifo_32_data.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is "";
- attribute RESETMODE of pdp_ram_0_0_0 : label is "SYNC";
+ attribute MEM_LPC_FILE of pdp_ram_0_0_1 : label is "fifo_32_data.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_0_0_1 : label is "";
+ attribute RESETMODE of pdp_ram_0_0_1 : label is "SYNC";
+ attribute MEM_LPC_FILE of pdp_ram_0_1_0 : label is "fifo_32_data.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_0_1_0 : label is "";
+ attribute RESETMODE of pdp_ram_0_1_0 : label is "SYNC";
+ attribute GSR of FF_34 : label is "ENABLED";
+ attribute GSR of FF_33 : label is "ENABLED";
+ attribute GSR of FF_32 : label is "ENABLED";
+ attribute GSR of FF_31 : label is "ENABLED";
+ attribute GSR of FF_30 : label is "ENABLED";
+ attribute GSR of FF_29 : label is "ENABLED";
+ attribute GSR of FF_28 : label is "ENABLED";
+ attribute GSR of FF_27 : label is "ENABLED";
+ attribute GSR of FF_26 : label is "ENABLED";
+ attribute GSR of FF_25 : label is "ENABLED";
+ attribute GSR of FF_24 : label is "ENABLED";
+ attribute GSR of FF_23 : label is "ENABLED";
attribute GSR of FF_22 : label is "ENABLED";
attribute GSR of FF_21 : label is "ENABLED";
attribute GSR of FF_20 : label is "ENABLED";
port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i,
AD0=>full_i, DO0=>full_d);
- pdp_ram_0_0_0: PDPW16KC
- generic map (CSDECODE_R=> "0b001", CSDECODE_W=> "0b001", GSR=> "DISABLED",
- REGMODE=> "OUTREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36)
- port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
- DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
- DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11),
- DI12=>Data(12), DI13=>Data(13), DI14=>Data(14),
- DI15=>Data(15), DI16=>Data(16), DI17=>Data(17),
- DI18=>Data(18), DI19=>Data(19), DI20=>Data(20),
- DI21=>Data(21), DI22=>Data(22), DI23=>Data(23),
- DI24=>Data(24), DI25=>Data(25), DI26=>Data(26),
- DI27=>Data(27), DI28=>Data(28), DI29=>Data(29),
- DI30=>Data(30), DI31=>Data(31), DI32=>scuba_vlo,
- DI33=>scuba_vlo, DI34=>scuba_vlo, DI35=>scuba_vlo,
- ADW0=>wcount_0, ADW1=>wcount_1, ADW2=>wcount_2,
- ADW3=>wcount_3, ADW4=>wcount_4, ADW5=>wcount_5,
- ADW6=>scuba_vlo, ADW7=>scuba_vlo, ADW8=>scuba_vlo,
- BE0=>scuba_vhi, BE1=>scuba_vhi, BE2=>scuba_vhi,
- BE3=>scuba_vhi, CEW=>wren_i, CLKW=>Clock, CSW0=>scuba_vhi,
- CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo,
- ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>scuba_vlo,
- ADR4=>scuba_vlo, ADR5=>rcount_0, ADR6=>rcount_1,
- ADR7=>rcount_2, ADR8=>rcount_3, ADR9=>rcount_4,
- ADR10=>rcount_5, ADR11=>scuba_vlo, ADR12=>scuba_vlo,
- ADR13=>scuba_vlo, CER=>scuba_vhi, CLKR=>Clock, CSR0=>rden_i,
- CSR1=>scuba_vlo, CSR2=>scuba_vlo, RST=>Reset, DO0=>Q(18),
- DO1=>Q(19), DO2=>Q(20), DO3=>Q(21), DO4=>Q(22), DO5=>Q(23),
- DO6=>Q(24), DO7=>Q(25), DO8=>Q(26), DO9=>Q(27), DO10=>Q(28),
- DO11=>Q(29), DO12=>Q(30), DO13=>Q(31), DO14=>open,
- DO15=>open, DO16=>open, DO17=>open, DO18=>Q(0), DO19=>Q(1),
- DO20=>Q(2), DO21=>Q(3), DO22=>Q(4), DO23=>Q(5), DO24=>Q(6),
- DO25=>Q(7), DO26=>Q(8), DO27=>Q(9), DO28=>Q(10), DO29=>Q(11),
- DO30=>Q(12), DO31=>Q(13), DO32=>Q(14), DO33=>Q(15),
- DO34=>Q(16), DO35=>Q(17));
-
- FF_22: FD1P3DX
+ pdp_ram_0_0_1: DP16KC
+ generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000",
+ WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 18,
+ DATA_WIDTH_A=> 18)
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
+ DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
+ DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16),
+ DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi,
+ ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wcount_0,
+ ADA5=>wcount_1, ADA6=>wcount_2, ADA7=>wcount_3,
+ ADA8=>wcount_4, ADA9=>wcount_5, ADA10=>wcount_6,
+ ADA11=>wcount_7, ADA12=>wcount_8, ADA13=>wcount_9,
+ CEA=>wren_i, CLKA=>Clock, OCEA=>wren_i, WEA=>scuba_vhi,
+ CSA0=>scuba_vlo, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
+ RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
+ ADB2=>scuba_vlo, ADB3=>scuba_vlo, ADB4=>rcount_0,
+ ADB5=>rcount_1, ADB6=>rcount_2, ADB7=>rcount_3,
+ ADB8=>rcount_4, ADB9=>rcount_5, ADB10=>rcount_6,
+ ADB11=>rcount_7, ADB12=>rcount_8, ADB13=>rcount_9,
+ CEB=>rden_i, CLKB=>Clock, OCEB=>scuba_vhi, WEB=>scuba_vlo,
+ CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
+ RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
+ DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
+ DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
+ DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
+ DOA17=>open, DOB0=>Q(0), DOB1=>Q(1), DOB2=>Q(2), DOB3=>Q(3),
+ DOB4=>Q(4), DOB5=>Q(5), DOB6=>Q(6), DOB7=>Q(7), DOB8=>Q(8),
+ DOB9=>Q(9), DOB10=>Q(10), DOB11=>Q(11), DOB12=>Q(12),
+ DOB13=>Q(13), DOB14=>Q(14), DOB15=>Q(15), DOB16=>Q(16),
+ DOB17=>Q(17));
+
+ pdp_ram_0_1_0: DP16KC
+ generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000",
+ WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 18,
+ DATA_WIDTH_A=> 18)
+ port map (DIA0=>Data(18), DIA1=>Data(19), DIA2=>Data(20),
+ DIA3=>Data(21), DIA4=>Data(22), DIA5=>Data(23),
+ DIA6=>Data(24), DIA7=>Data(25), DIA8=>Data(26),
+ DIA9=>Data(27), DIA10=>Data(28), DIA11=>Data(29),
+ DIA12=>Data(30), DIA13=>Data(31), DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vhi, ADA1=>scuba_vhi, ADA2=>scuba_vlo,
+ ADA3=>scuba_vlo, ADA4=>wcount_0, ADA5=>wcount_1,
+ ADA6=>wcount_2, ADA7=>wcount_3, ADA8=>wcount_4,
+ ADA9=>wcount_5, ADA10=>wcount_6, ADA11=>wcount_7,
+ ADA12=>wcount_8, ADA13=>wcount_9, CEA=>wren_i, CLKA=>Clock,
+ OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>scuba_vlo,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>scuba_vlo, ADB4=>rcount_0, ADB5=>rcount_1,
+ ADB6=>rcount_2, ADB7=>rcount_3, ADB8=>rcount_4,
+ ADB9=>rcount_5, ADB10=>rcount_6, ADB11=>rcount_7,
+ ADB12=>rcount_8, ADB13=>rcount_9, CEB=>rden_i, CLKB=>Clock,
+ OCEB=>scuba_vhi, WEB=>scuba_vlo, CSB0=>scuba_vlo,
+ CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(18),
+ DOB1=>Q(19), DOB2=>Q(20), DOB3=>Q(21), DOB4=>Q(22),
+ DOB5=>Q(23), DOB6=>Q(24), DOB7=>Q(25), DOB8=>Q(26),
+ DOB9=>Q(27), DOB10=>Q(28), DOB11=>Q(29), DOB12=>Q(30),
+ DOB13=>Q(31), DOB14=>open, DOB15=>open, DOB16=>open,
+ DOB17=>open);
+
+ FF_34: FD1P3DX
port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_0);
- FF_21: FD1P3DX
+ FF_33: FD1P3DX
port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_1);
- FF_20: FD1P3DX
+ FF_32: FD1P3DX
port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_2);
- FF_19: FD1P3DX
+ FF_31: FD1P3DX
port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_3);
- FF_18: FD1P3DX
+ FF_30: FD1P3DX
port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_4);
- FF_17: FD1P3DX
+ FF_29: FD1P3DX
port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_5);
- FF_16: FD1P3DX
+ FF_28: FD1P3DX
port map (D=>ifcount_6, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_6);
- FF_15: FD1S3BX
+ FF_27: FD1P3DX
+ port map (D=>ifcount_7, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_7);
+
+ FF_26: FD1P3DX
+ port map (D=>ifcount_8, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_8);
+
+ FF_25: FD1P3DX
+ port map (D=>ifcount_9, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_9);
+
+ FF_24: FD1P3DX
+ port map (D=>ifcount_10, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_10);
+
+ FF_23: FD1S3BX
port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i);
- FF_14: FD1S3DX
+ FF_22: FD1S3DX
port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i);
- FF_13: FD1P3DX
+ FF_21: FD1P3DX
port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_0);
- FF_12: FD1P3DX
+ FF_20: FD1P3DX
port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_1);
- FF_11: FD1P3DX
+ FF_19: FD1P3DX
port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_2);
- FF_10: FD1P3DX
+ FF_18: FD1P3DX
port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_3);
- FF_9: FD1P3DX
+ FF_17: FD1P3DX
port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_4);
- FF_8: FD1P3DX
+ FF_16: FD1P3DX
port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_5);
- FF_7: FD1P3DX
+ FF_15: FD1P3DX
port map (D=>iwcount_6, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_6);
- FF_6: FD1P3DX
+ FF_14: FD1P3DX
+ port map (D=>iwcount_7, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_7);
+
+ FF_13: FD1P3DX
+ port map (D=>iwcount_8, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_8);
+
+ FF_12: FD1P3DX
+ port map (D=>iwcount_9, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_9);
+
+ FF_11: FD1P3DX
+ port map (D=>iwcount_10, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_10);
+
+ FF_10: FD1P3DX
port map (D=>ircount_0, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_0);
- FF_5: FD1P3DX
+ FF_9: FD1P3DX
port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_1);
- FF_4: FD1P3DX
+ FF_8: FD1P3DX
port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_2);
- FF_3: FD1P3DX
+ FF_7: FD1P3DX
port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_3);
- FF_2: FD1P3DX
+ FF_6: FD1P3DX
port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_4);
- FF_1: FD1P3DX
+ FF_5: FD1P3DX
port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_5);
- FF_0: FD1P3DX
+ FF_4: FD1P3DX
port map (D=>ircount_6, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_6);
+ FF_3: FD1P3DX
+ port map (D=>ircount_7, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_7);
+
+ FF_2: FD1P3DX
+ port map (D=>ircount_8, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_8);
+
+ FF_1: FD1P3DX
+ port map (D=>ircount_9, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_9);
+
+ FF_0: FD1P3DX
+ port map (D=>ircount_10, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_10);
+
bdcnt_bctr_cia: FADD2B
port map (A0=>scuba_vlo, A1=>cnt_con, B0=>scuba_vlo, B1=>cnt_con,
CI=>scuba_vlo, COUT=>bdcnt_bctr_ci, S0=>open, S1=>open);
CO=>co2, NC0=>ifcount_4, NC1=>ifcount_5);
bdcnt_bctr_3: CB2
- port map (CI=>co2, PC0=>fcount_6, PC1=>scuba_vlo, CON=>cnt_con,
- CO=>co3, NC0=>ifcount_6, NC1=>open);
+ port map (CI=>co2, PC0=>fcount_6, PC1=>fcount_7, CON=>cnt_con,
+ CO=>co3, NC0=>ifcount_6, NC1=>ifcount_7);
+
+ bdcnt_bctr_4: CB2
+ port map (CI=>co3, PC0=>fcount_8, PC1=>fcount_9, CON=>cnt_con,
+ CO=>co4, NC0=>ifcount_8, NC1=>ifcount_9);
+
+ bdcnt_bctr_5: CB2
+ port map (CI=>co4, PC0=>fcount_10, PC1=>scuba_vlo, CON=>cnt_con,
+ CO=>co5, NC0=>ifcount_10, NC1=>open);
e_cmp_ci_a: FADD2B
port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi,
B1=>scuba_vlo, CI=>co1_1, LE=>co2_1);
e_cmp_3: ALEB2
- port map (A0=>fcount_6, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>co2_1, LE=>cmp_le_1_c);
+ port map (A0=>fcount_6, A1=>fcount_7, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>co2_1, LE=>co3_1);
+
+ e_cmp_4: ALEB2
+ port map (A0=>fcount_8, A1=>fcount_9, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>co3_1, LE=>co4_1);
+
+ e_cmp_5: ALEB2
+ port map (A0=>fcount_10, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>co4_1, LE=>cmp_le_1_c);
a0: FADD2B
port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
CI=>co1_2, GE=>co2_2);
g_cmp_3: AGEB2
- port map (A0=>fcount_6, A1=>scuba_vlo, B0=>wren_i_inv,
- B1=>scuba_vlo, CI=>co2_2, GE=>cmp_ge_d1_c);
+ port map (A0=>fcount_6, A1=>fcount_7, B0=>wren_i, B1=>wren_i,
+ CI=>co2_2, GE=>co3_2);
+
+ g_cmp_4: AGEB2
+ port map (A0=>fcount_8, A1=>fcount_9, B0=>wren_i, B1=>wren_i,
+ CI=>co3_2, GE=>co4_2);
+
+ g_cmp_5: AGEB2
+ port map (A0=>fcount_10, A1=>scuba_vlo, B0=>wren_i_inv,
+ B1=>scuba_vlo, CI=>co4_2, GE=>cmp_ge_d1_c);
a1: FADD2B
port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
NC0=>iwcount_4, NC1=>iwcount_5);
w_ctr_3: CU2
- port map (CI=>co2_3, PC0=>wcount_6, PC1=>scuba_vlo, CO=>co3_1,
- NC0=>iwcount_6, NC1=>open);
+ port map (CI=>co2_3, PC0=>wcount_6, PC1=>wcount_7, CO=>co3_3,
+ NC0=>iwcount_6, NC1=>iwcount_7);
+
+ w_ctr_4: CU2
+ port map (CI=>co3_3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4_3,
+ NC0=>iwcount_8, NC1=>iwcount_9);
+
+ w_ctr_5: CU2
+ port map (CI=>co4_3, PC0=>wcount_10, PC1=>scuba_vlo, CO=>co5_1,
+ NC0=>iwcount_10, NC1=>open);
scuba_vhi_inst: VHI
port map (Z=>scuba_vhi);
port map (CI=>co1_4, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_4,
NC0=>ircount_4, NC1=>ircount_5);
+ r_ctr_3: CU2
+ port map (CI=>co2_4, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_4,
+ NC0=>ircount_6, NC1=>ircount_7);
+
+ r_ctr_4: CU2
+ port map (CI=>co3_4, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_4,
+ NC0=>ircount_8, NC1=>ircount_9);
+
scuba_vlo_inst: VLO
port map (Z=>scuba_vlo);
- r_ctr_3: CU2
- port map (CI=>co2_4, PC0=>rcount_6, PC1=>scuba_vlo, CO=>co3_2,
- NC0=>ircount_6, NC1=>open);
+ r_ctr_5: CU2
+ port map (CI=>co4_4, PC0=>rcount_10, PC1=>scuba_vlo, CO=>co5_2,
+ NC0=>ircount_10, NC1=>open);
Empty <= empty_i;
Full <= full_i;
for all:VHI use entity ecp3.VHI(V); end for;
for all:VLO use entity ecp3.VLO(V); end for;
for all:XOR2 use entity ecp3.XOR2(V); end for;
- for all:PDPW16KC use entity ecp3.PDPW16KC(V); end for;
+ for all:DP16KC use entity ecp3.DP16KC(V); end for;
end for;
end Structure_CON;
------------------------------------------------------------------------------
+----------------------------------------------------------------------------
--
-- One nXyter FEB
--
signal clk_256_o : std_logic;
-- Bus Handler
- signal slv_read : std_logic_vector(8-1 downto 0);
- signal slv_write : std_logic_vector(8-1 downto 0);
- signal slv_no_more_data : std_logic_vector(8-1 downto 0);
- signal slv_ack : std_logic_vector(8-1 downto 0);
- signal slv_addr : std_logic_vector(8*16-1 downto 0);
- signal slv_data_rd : std_logic_vector(8*32-1 downto 0);
- signal slv_data_wr : std_logic_vector(8*32-1 downto 0);
- signal slv_unknown_addr : std_logic_vector(8-1 downto 0);
-
- -- I2C Master
+ signal slv_read : std_logic_vector(10-1 downto 0);
+ signal slv_write : std_logic_vector(10-1 downto 0);
+ signal slv_no_more_data : std_logic_vector(10-1 downto 0);
+ signal slv_ack : std_logic_vector(10-1 downto 0);
+ signal slv_addr : std_logic_vector(10*16-1 downto 0);
+ signal slv_data_rd : std_logic_vector(10*32-1 downto 0);
+ signal slv_data_wr : std_logic_vector(10*32-1 downto 0);
+ signal slv_unknown_addr : std_logic_vector(10-1 downto 0);
+
+ -- TRB Register
signal i2c_sm_reset_o : std_logic;
+ signal nx_ts_reset_1 : std_logic;
+ signal nx_ts_reset_2 : std_logic;
+ signal nx_ts_reset_o : std_logic;
signal i2c_reg_reset_o : std_logic;
-- SPI Interface ADC
signal spi_sdi : std_logic;
signal spi_sdo : std_logic;
- -- FIFO Read
- signal nx_ts_reset_o : std_logic;
+ -- Timestamp FIFO Read
+ signal nx_timestamp : std_logic_vector(31 downto 0);
+ signal nx_new_timestamp : std_logic;
signal nx_frame_clock_o : std_logic;
- signal nx_frame_sync_o : std_logic;
-
- -- Timestamp Handlers
- signal nx_timestamp_o : std_logic_vector(31 downto 0);
- signal nx_new_frame : std_logic;
-
- -- FPGA Timestamp
- signal timestamp_latched : unsigned(13 downto 0);
- signal nx_timestamp_sync_o : std_logic;
+
+ -- Timestamp Decode Handlers
+ signal timestamp_data : std_logic_vector(31 downto 0);
+ signal timestamp_valid : std_logic;
+ signal nx_token_return : std_logic;
+ signal nx_nomore_data : std_logic;
+ -- FPGA Timestamp
+ signal timestamp_trigger : unsigned(11 downto 0);
+ signal nx_timestamp_sync : std_logic;
+
+ -- Trigger Handler
+ signal trigger_release : std_logic;
+ signal trigger_ack : std_logic;
+ signal timestamp_hold : std_logic;
+ signal trigger_busy : std_logic;
+
-- Testpulse Generator
signal nx_testpulse_o : std_logic;
begin
-
+ trigger_release <= '1';
-------------------------------------------------------------------------------
-- DEBUG
-------------------------------------------------------------------------------
- DEBUG_LINE_OUT(0) <= CLK_IN;
- DEBUG_LINE_OUT(1) <= NX_CLK128_IN;
- DEBUG_LINE_OUT(2) <= NX_RESET_OUT;
- DEBUG_LINE_OUT(3) <= NX_TESTPULSE_OUT;
- DEBUG_LINE_OUT(4) <= clk_256_o;
--- DEBUG_LINE_OUT(5) <= clk_lock;
-
-
-
-
--- DEBUG_LINE_OUT(4) <= ADC_DCLK_IN;
--- DEBUG_LINE_OUT(5) <= ADC_NX_IN;
--- DEBUG_LINE_OUT(6) <= ADC_A_IN;
--- DEBUG_LINE_OUT(7) <= ADC_B_IN;
--- DEBUG_LINE_OUT(8) <= ADC_D_IN;
---
--- DEBUG_LINE_OUT(15 downto 9) <= (others => '0');
---
- DEBUG_LINE_OUT(15 downto 8) <= NX_TIMESTAMP_IN;
--- DEBUG_LINE_OUT(8) <= i2c_sda_o;
--- DEBUG_LINE_OUT(9) <= i2c_sda_i;
--- DEBUG_LINE_OUT(10) <= i2c_scl_o;
--- DEBUG_LINE_OUT(11) <= i2c_scl_i;
--- DEBUG_LINE_OUT(15 downto 12) <= (others => '0');
-
--- DEBUG_LINE_OUT(0) <= CLK_IN;
--- DEBUG_LINE_OUT(1) <= I2C_SDA_INOUT;
--- DEBUG_LINE_OUT(2) <= I2C_SCL_INOUT;
--- DEBUG_LINE_OUT(3) <= i2c_sm_reset_o;
--- DEBUG_LINE_OUT(4) <= i2c_reg_reset_o;
---
--- DEBUG_LINE_OUT(5 downto 5) <= (others => '0');
+ DEBUG_LINE_OUT(0) <= CLK_IN;
+ DEBUG_LINE_OUT(1) <= trigger_ack;
+ DEBUG_LINE_OUT(2) <= nx_ts_reset_o;
+ DEBUG_LINE_OUT(3) <= nx_testpulse_o;
+ DEBUG_LINE_OUT(4) <= nx_new_timestamp;
+ DEBUG_LINE_OUT(5) <= timestamp_valid;
+ DEBUG_LINE_OUT(6) <= timestamp_hold;
+ DEBUG_LINE_OUT(7) <= nx_token_return;
+ DEBUG_LINE_OUT(8) <= nx_nomore_data;
+ DEBUG_LINE_OUT(9) <= trigger_busy;
+ DEBUG_LINE_OUT(15 downto 10) <= (others => '0');
-------------------------------------------------------------------------------
-- Port Maps
THE_BUS_HANDLER: trb_net16_regio_bus_handler
generic map(
- PORT_NUMBER => 6,
- PORT_ADDRESSES => ( 0 => x"0000", -- Control Register Handler
- 1 => x"0040", -- I2C master
- 2 => x"0100", -- Timestamp Fifo
- 3 => x"0200", -- Data Buffer
+ PORT_NUMBER => 8,
+
+ PORT_ADDRESSES => ( 0 => x"0100", -- Control Register Handler
+ 1 => x"0040", -- I2C Master
+ 2 => x"0500", -- Timestamp Fifo
+ 3 => x"0600", -- Data Buffer
4 => x"0060", -- SPI Master
- 5 => x"0080", -- Trigger Generator
+ 5 => x"0140", -- Trigger Generator
+ 6 => x"0120", -- Timestamp Decode
+ 7 => x"0160", -- Trigger Handler
others => x"0000"),
+
PORT_ADDR_MASK => ( 0 => 3, -- Control Register Handler
1 => 0, -- I2C master
2 => 1, -- Timestamp Fifo
- 3 => 1, -- Data Buffer
+ 3 => 0, -- Data Buffer
4 => 0, -- SPI Master
- 5 => 0, -- Trigger Generator
+ 5 => 3, -- Trigger Generator
+ 6 => 4, -- Timestamp Decode
+ 7 => 1, -- Trigger Handler
others => 0)
)
port map(
BUS_WRITE_ENABLE_OUT(2) => slv_write(2),
BUS_DATA_OUT(2*32+31 downto 2*32) => slv_data_wr(2*32+31 downto 2*32),
BUS_DATA_IN(2*32+31 downto 2*32) => slv_data_rd(2*32+31 downto 2*32),
--- BUS_ADDR_OUT(2*16+0 downto 2*16) => slv_addr(2*16+0 downto 0*16),
BUS_ADDR_OUT(2*16+0) => slv_addr(2*16+0),
BUS_ADDR_OUT(2*16+15 downto 2*16+1) => open,
BUS_TIMEOUT_OUT(2) => open,
BUS_WRITE_ENABLE_OUT(3) => slv_write(3),
BUS_DATA_OUT(3*32+31 downto 3*32) => slv_data_wr(3*32+31 downto 3*32),
BUS_DATA_IN(3*32+31 downto 3*32) => slv_data_rd(3*32+31 downto 3*32),
--- BUS_ADDR_OUT(3*16+0 downto 2*16) => slv_addr(3*16+0 downto 0*16),
BUS_ADDR_OUT(3*16+0) => slv_addr(3*16+0),
BUS_ADDR_OUT(3*16+15 downto 3*16+1) => open,
BUS_TIMEOUT_OUT(3) => open,
BUS_WRITE_ENABLE_OUT(5) => slv_write(5),
BUS_DATA_OUT(5*32+31 downto 5*32) => slv_data_wr(5*32+31 downto 5*32),
BUS_DATA_IN(5*32+31 downto 5*32) => slv_data_rd(5*32+31 downto 5*32),
- BUS_ADDR_OUT(5*16+15 downto 5*16) => open,
+ BUS_ADDR_OUT(5*16+2 downto 5*16) => slv_addr(5*16+2 downto 5*16),
+ BUS_ADDR_OUT(5*16+15 downto 5*16+3) => open,
BUS_TIMEOUT_OUT(5) => open,
BUS_DATAREADY_IN(5) => slv_ack(5),
BUS_WRITE_ACK_IN(5) => slv_ack(5),
BUS_NO_MORE_DATA_IN(5) => slv_no_more_data(5),
BUS_UNKNOWN_ADDR_IN(5) => slv_unknown_addr(5),
- ---- SPI control registers
- --BUS_READ_ENABLE_OUT(4) => slv_read(4),
- --BUS_WRITE_ENABLE_OUT(4) => slv_write(4),
- --BUS_DATA_OUT(4*32+31 downto 4*32) => slv_data_wr(4*32+31 downto 4*32),
- --BUS_DATA_IN(4*32+31 downto 4*32) => slv_data_rd(4*32+31 downto 4*32),
- --BUS_ADDR_OUT(4*16+15 downto 4*16) => slv_addr(4*16+15 downto 4*16),
- --BUS_TIMEOUT_OUT(4) => open,
- --BUS_DATAREADY_IN(4) => slv_ack(4),
- --BUS_WRITE_ACK_IN(4) => slv_ack(4),
- --BUS_NO_MORE_DATA_IN(4) => slv_no_more_data(4),
- --BUS_UNKNOWN_ADDR_IN(4) => '0',
-
- ---- SPI data memory
- --BUS_READ_ENABLE_OUT(5) => slv_read(5),
- --BUS_WRITE_ENABLE_OUT(5) => slv_write(5),
- --BUS_DATA_OUT(5*32+31 downto 5*32) => slv_data_wr(5*32+31 downto 5*32),
- --BUS_DATA_IN(5*32+31 downto 5*32) => slv_data_rd(5*32+31 downto 5*32),
- --BUS_ADDR_OUT(5*16+15 downto 5*16) => slv_addr(5*16+15 downto 5*16),
- --BUS_TIMEOUT_OUT(5) => open,
- --BUS_DATAREADY_IN(5) => slv_ack(5),
- --BUS_WRITE_ACK_IN(5) => slv_ack(5),
- --BUS_NO_MORE_DATA_IN(5) => slv_no_more_data(5),
- --BUS_UNKNOWN_ADDR_IN(5) => '0',
+ -- Timestamp Decode
+ BUS_READ_ENABLE_OUT(6) => slv_read(6),
+ BUS_WRITE_ENABLE_OUT(6) => slv_write(6),
+ BUS_DATA_OUT(6*32+31 downto 6*32) => slv_data_wr(6*32+31 downto 6*32),
+ BUS_DATA_IN(6*32+31 downto 6*32) => slv_data_rd(6*32+31 downto 6*32),
+ BUS_ADDR_OUT(6*16+4 downto 6*16) => slv_addr(6*16+4 downto 6*16),
+ BUS_ADDR_OUT(6*16+15 downto 6*16+5) => open,
+ BUS_TIMEOUT_OUT(6) => open,
+ BUS_DATAREADY_IN(6) => slv_ack(6),
+ BUS_WRITE_ACK_IN(6) => slv_ack(6),
+ BUS_NO_MORE_DATA_IN(6) => slv_no_more_data(6),
+ BUS_UNKNOWN_ADDR_IN(6) => slv_unknown_addr(6),
+
+ -- Trigger Handler
+ BUS_READ_ENABLE_OUT(7) => slv_read(7),
+ BUS_WRITE_ENABLE_OUT(7) => slv_write(7),
+ BUS_DATA_OUT(7*32+31 downto 7*32) => slv_data_wr(7*32+31 downto 7*32),
+ BUS_DATA_IN(7*32+31 downto 7*32) => slv_data_rd(7*32+31 downto 7*32),
+ BUS_ADDR_OUT(7*16+0) => slv_addr(7*16+0),
+ BUS_ADDR_OUT(7*16+15 downto 7*16+1) => open,
+ BUS_TIMEOUT_OUT(7) => open,
+ BUS_DATAREADY_IN(7) => slv_ack(7),
+ BUS_WRITE_ACK_IN(7) => slv_ack(7),
+ BUS_NO_MORE_DATA_IN(7) => slv_no_more_data(7),
+ BUS_UNKNOWN_ADDR_IN(7) => slv_unknown_addr(7),
---- debug
STAT_DEBUG => open
SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(0),
I2C_SM_RESET_OUT => i2c_sm_reset_o,
I2C_REG_RESET_OUT => i2c_reg_reset_o,
- NX_TS_RESET_OUT => nx_ts_reset_o,
+ NX_TS_RESET_OUT => nx_ts_reset_1,
--DEBUG_OUT(7 downto 0) => DEBUG_LINE_OUT(15 downto 8)
DEBUG_OUT => open
);
SLV_ACK_OUT => slv_ack(1),
SLV_NO_MORE_DATA_OUT => slv_no_more_data(1),
SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(1),
+ -- DEBUG_OUT => DEBUG_LINE_OUT
DEBUG_OUT => open
);
NX_TIMESTAMP_CLK_IN => NX_CLK128_IN,
NX_TIMESTAMP_IN => NX_TIMESTAMP_IN,
NX_FRAME_CLOCK_OUT => nx_frame_clock_o,
- NX_FRAME_SYNC_OUT => nx_frame_sync_o,
- NX_TIMESTAMP_OUT => nx_timestamp_o,
- NX_NEW_FRAME_OUT => nx_new_frame,
+ NX_TIMESTAMP_OUT => nx_timestamp,
+ NX_NEW_TIMESTAMP_OUT => nx_new_timestamp,
SLV_READ_IN => slv_read(2),
SLV_WRITE_IN => slv_write(2),
SLV_DATA_OUT => slv_data_rd(2*32+31 downto 2*32),
SLV_NO_MORE_DATA_OUT => slv_no_more_data(2),
SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(2),
- --DEBUG_OUT(7 downto 0) => DEBUG_LINE_OUT(7 downto 0)
+ -- DEBUG_OUT => DEBUG_LINE_OUT
DEBUG_OUT => open
);
nx_timestamp_decode_1: nx_timestamp_decode
port map (
- CLK_IN => CLK_IN,
- RESET_IN => RESET_IN,
- NX_NEW_FRAME_IN => nx_new_frame,
- NX_TIMESTAMP_IN => nx_timestamp_o,
- TIMESTAMP_DATA_OUT => open,
- TIMESTAMP_VALID_OUT => open,
+ CLK_IN => CLK_IN,
+ RESET_IN => RESET_IN,
+ NX_NEW_TIMESTAMP_IN => nx_new_timestamp,
+ NX_TIMESTAMP_IN => nx_timestamp,
+ TIMESTAMP_REF_IN => timestamp_trigger,
+ TIMESTAMP_DATA_OUT => timestamp_data,
+ TIMESTAMP_VALID_OUT => timestamp_valid,
+ NX_TOKEN_RETURN => nx_token_return,
+ NX_NOMORE_DATA => nx_nomore_data,
+
+ SLV_READ_IN => slv_read(6),
+ SLV_WRITE_IN => slv_write(6),
+ SLV_DATA_OUT => slv_data_rd(6*32+31 downto 6*32),
+ SLV_DATA_IN => slv_data_wr(6*32+31 downto 6*32),
+ SLV_ADDR_IN => slv_addr(6*16+15 downto 6*16),
+ SLV_ACK_OUT => slv_ack(6),
+ SLV_NO_MORE_DATA_OUT => slv_no_more_data(6),
+ SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(6),
- -- DEBUG_OUT => DEBUG_LINE_OUT
+ -- DEBUG_OUT(14 downto 0) => DEBUG_LINE_OUT(14 downto 0)
DEBUG_OUT => open
);
+-- DEBUG_LINE_OUT(15) <= nx_testpulse_o;
-------------------------------------------------------------------------------
-- Data Buffer FIFO
-------------------------------------------------------------------------------
-
- nx_data_buffer_2: nx_data_buffer
+ nx_data_buffer_1: nx_data_buffer
port map (
- CLK_IN => CLK_IN,
- RESET_IN => RESET_IN,
- DATA_IN => nx_timestamp_o,
- NEW_DATA_IN => nx_new_frame,
+ CLK_IN => CLK_IN,
+ RESET_IN => RESET_IN,
+ DATA_IN => timestamp_data,
+ NEW_DATA_IN => timestamp_valid,
- FIFO_WRITE_ENABLE_IN => '1',
- FIFO_READ_ENABLE_IN => '1',
-
- SLV_READ_IN => slv_read(3),
- SLV_WRITE_IN => slv_write(3),
- SLV_DATA_OUT => slv_data_rd(3*32+31 downto 3*32),
- SLV_DATA_IN => slv_data_wr(3*32+31 downto 3*32),
- SLV_ADDR_IN => slv_addr(3*16+15 downto 3*16),
- SLV_ACK_OUT => slv_ack(3),
- SLV_NO_MORE_DATA_OUT => slv_no_more_data(3),
- SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(3),
-
- -- DEBUG_OUT => DEBUG_LINE_OUT
- DEBUG_OUT => open
+ FIFO_WRITE_ENABLE_IN => '1',
+ FIFO_READ_ENABLE_IN => '1',
+
+ SLV_READ_IN => slv_read(3),
+ SLV_WRITE_IN => slv_write(3),
+ SLV_DATA_OUT => slv_data_rd(3*32+31 downto 3*32),
+ SLV_DATA_IN => slv_data_wr(3*32+31 downto 3*32),
+ SLV_ADDR_IN => slv_addr(3*16+15 downto 3*16),
+ SLV_ACK_OUT => slv_ack(3),
+ SLV_NO_MORE_DATA_OUT => slv_no_more_data(3),
+ SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(3),
+
+ --DEBUG_OUT => DEBUG_LINE_OUT
+ DEBUG_OUT => open
);
-------------------------------------------------------------------------------
nx_fpga_timestamp_1: nx_fpga_timestamp
port map (
- CLK_IN => CLK_IN,
+ CLK_IN => clk_256_o,
RESET_IN => RESET_IN,
- TIMESTAMP_CLK_IN => clk_256_o,
- TIMESTAMP_SYNC_IN => RESET_IN,
- LATCH_IN => nx_testpulse_o,
- TIMESTAMP_OUT => timestamp_latched,
- NX_TIMESTAMP_SYNC_OUT => nx_timestamp_sync_o,
+ TIMESTAMP_SYNC_IN => nx_ts_reset_o,
+ TRIGGER_IN => timestamp_hold,
+ TIMESTAMP_OUT => timestamp_trigger,
+ NX_TIMESTAMP_SYNC_OUT => nx_timestamp_sync,
SLV_READ_IN => open,
SLV_WRITE_IN => open,
SLV_DATA_OUT => open,
SLV_NO_MORE_DATA_OUT => open,
SLV_UNKNOWN_ADDR_OUT => open,
-- DEBUG_OUT => DEBUG_LINE_OUT
- DEBUG_OUT => open
+ DEBUG_OUT => open
+ );
+
+-------------------------------------------------------------------------------
+-- Trigger Handler
+-------------------------------------------------------------------------------
+
+ nx_trigger_handler_1: nx_trigger_handler
+ port map (
+ CLK_IN => CLK_IN,
+ RESET_IN => RESET_IN,
+ TRIGGER_IN => nx_testpulse_o,
+ TRIGGER_RELEASE_IN => trigger_release,
+ TRIGGER_OUT => trigger_ack,
+ TIMESTAMP_HOLD_OUT => timestamp_hold,
+ TRIGGER_BUSY_OUT => trigger_busy,
+ SLV_READ_IN => slv_read(7),
+ SLV_WRITE_IN => slv_write(7),
+ SLV_DATA_OUT => slv_data_rd(7*32+31 downto 7*32),
+ SLV_DATA_IN => slv_data_wr(7*32+31 downto 7*32),
+ SLV_ADDR_IN => slv_addr(7*16+15 downto 7*16),
+ SLV_ACK_OUT => slv_ack(7),
+ SLV_NO_MORE_DATA_OUT => slv_no_more_data(7),
+ SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(7),
+ -- DEBUG_OUT(14 downto 0) => DEBUG_LINE_OUT(14 downto 0)
+ DEBUG_OUT => open
);
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
nx_trigger_generator_1: nx_trigger_generator
- generic map (
- TRIGGER_SPEED => x"ffff"
- )
port map (
CLK_IN => CLK_IN,
RESET_IN => RESET_IN,
TRIGGER_OUT => nx_testpulse_o,
+ TS_RESET_OUT => nx_ts_reset_2,
SLV_READ_IN => slv_read(5),
SLV_WRITE_IN => slv_write(5),
SLV_DATA_OUT => slv_data_rd(5*32+31 downto 5*32),
SLV_DATA_IN => slv_data_wr(5*32+31 downto 5*32),
+ SLV_ADDR_IN => slv_addr(5*16+15 downto 5*16),
SLV_ACK_OUT => slv_ack(5),
SLV_NO_MORE_DATA_OUT => slv_no_more_data(5),
SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(5),
-------------------------------------------------------------------------------
-- nXyter Signals
-------------------------------------------------------------------------------
- NX_RESET_OUT <= '1';--nx_ts_reset_o;
- NX_TESTPULSE_OUT <= nx_testpulse_o;
+ nx_ts_reset_o <= nx_ts_reset_1 or nx_ts_reset_2;
+ NX_RESET_OUT <= not nx_ts_reset_o;
+ NX_TESTPULSE_OUT <= not nx_testpulse_o;
+
-------------------------------------------------------------------------------
-- I2C Signals
-------------------------------------------------------------------------------
ADC_SC_CLK32_OUT <= nx_frame_clock_o;
-
-
-
-
-------------------------------------------------------------------------------
-- END
jspc29 / trb3.git / commitdiff