\subsubsection{FPGA design}
The optical link, activated for the Slow Control over GbE is the one labelled SFP8.
-After loading the design, TRB3 will automatically start to send control packets once per second. With any network monitoring tools (ex. Wireshark) one have to capture such packet and check the source MAC address. This address has to be added to the DHCP configuration on Slow Control server PC. MAC address is generated basing on the unique ID assigned to each FPGA and a constant part: 02:00:BE:UNIQUE_ID(31 downto 8)
+After loading the design, TRB3 will automatically start to send control packets once per second. With any network monitoring tools (ex. Wireshark) one have to capture such packet and check the source MAC address. This address has to be added to the DHCP configuration on Slow Control server PC. MAC address is generated basing on the unique ID assigned to each FPGA and a constant part: 02:00:BE:UNIQUE$\_$ID(31 downto 8)
\begin{itemize*}
\item Open /etc/dhcpd.conf and add an entry specifing hostname and MAC address
\begin{figure}[htp]
\centering
- \includegraphics[width=0.8\textwidth]{figures/Calibration_2.pdf}
+ \includegraphics[width=0.6\textwidth]{figures/Calibration_2.pdf}
\caption[An example of a LUT created by the bin-by-bin calibration method]{An example of a LUT created by the bin-by-bin calibration method (Adapted from \cite{tdcWuWaveunion})}
\label{fig:calibration}
\end{figure}
The data format of the \textbf{\textit{header}} word is shown below:
-\begin{table}[h]
+\begin{table}[ht]
\centering
\begin{tabular}{|W{1.2cm}|W{2cm}|W{3.2cm}|W{6.3cm}|}
\hline
0xc0 - bit 4
\end{verbatim}
-The data format of the \textbf{\textit{debug}} word is shown below:
+The data format of the \textbf{\textit{debug}} word is shown in Table~\ref{tab:tdcDebugWord}:
\begin{table}[h]
\centering
\begin{table}[h]
\centering
- \begin{tabular}{|W{1.275cm}|W{1.275cm}|W{11.05cm}|}
+ \begin{tabular}{|W{1.23cm}|W{2.05cm}|W{9.87cm}|}
\hline
3 bits & 1 bit & 28 bits\\
"011" & reserved & EPOCH Counter\\
\hline
\end{tabular}
\caption{The data format of the \textit{EPOCH Counter} word.}
- \label{tab:tdcReservedWord}
+ \label{tab:tdcEpochCounte}
\end{table}
The EPOCH counter is designed with 28 bits increasing the total
\hline
0xc3 & Channel enable 2 & 31-0 & Enable signals for the channels 33-64.\\
\hline
- \multirow{3}{*}{0xc4} & \multirow{3}{*}{Channel hit scaler control} & 7-0 & Defines the channel number of the scaler register (Status register 0x90).\\
+ \multirow{3}{*}{0xc4} & \multirow{3}{*}{Channel hit scaler control} & 7-0 & Defines the channel number of the scaler register (Status register 0x91).\\
& & 31-8 & reserved.\\
\hline
\end{tabularx}
& & 31-24 & reserved\\ \hline
\multirow{3}{*}{0x90} & \multirow{3}{3.5cm}{Readout Time} & 23-0 & Total time length, that the readout occured (with granularity of 10~ns)\\
& & 31-24 & reserved\\ \hline
- \multirow{3}{*}{0x91} & \multirow{3}{3.5cm}{Channel Scaler} & 23-0 & Number of hits detected by a channel. Channel number is controlled with register 0xc4\\
+ \multirow{3}{*}{0x91} & \multirow{3}{3.5cm}{Timeout Number} & 23-0 & Number of timeouts detected (too long delay after the timing trigger)\\
& & 31-24 & reserved\\ \hline
\end{tabularx}
\caption{The status registers of the TDC. (Continue)}
\end{table}
The status registers of the TDC are explained in Table \ref{tab:tdcStatusReg1} and Table \ref{tab:tdcStatusReg2}.
+
+\newpage
+\subsubsection{Hit Scaler Registers}
+
+In order to automatise the threshold level settings the number of hits detected by each channel can be reached via slow control as well as the current LVDS input level state. The bit mask for these registers is x"c0". The very least 8~bits are used for the channel number, e.g. \verb|trbcmd r 0xc001| would give the hits detected by channel 1. In the same register the MSB shows the logic level of the output of the input LVDS buffers. This bit is useful for the designs, which use the LVDS buffers as discriminators, e.g. cbmrich and padiwa projects. The data format of the register is shown below:
+
+\begin{table}[ht]
+ \centering
+ \begin{tabular}{|W{1.2cm}|W{2.8cm}|W{9.1cm}|}
+ \hline
+ 1 bit & 7 bits & 24 bits\\
+ LVDS level & reserved & number of hits detected\\
+ \hline
+ \end{tabular}
+ \caption{The data format of the \textit{Hit Registers}.}
+ \label{tab:tdcHitRegister}
+\end{table}
\ No newline at end of file
\input{TdcDataFormat}
\subsection{Slow Control Registers}
\input{TdcSlowControl}
- \newpage
\subsection{DAC Programming}
\input{DacProgramming}