Changing name of media interface for backplane master for better placement

diff --git a/backplanemaster/trb3sc_master.vhd b/backplanemaster/trb3sc_master.vhd
index 0adf5fd8969d53487b34843e372e3f2b767841ba..5dc04b941f6810125239977921cb96ed5215f826 100644 (file)
--- a/backplanemaster/trb3sc_master.vhd
+++ b/backplanemaster/trb3sc_master.vhd
@@ -201,7 +201,7 @@ THE_CLOCK_RESET :  entity work.clock_reset_handler
 ---------------------------------------------------------------------------
 -- TrbNet Uplink
 ---------------------------------------------------------------------------
-THE_MEDIA_INTERFACE : entity work.med_ecp3_sfp_sync_4_slave3  --PCSB
+THE_MEDIA_INT_MIXED : entity work.med_ecp3_sfp_sync_4_slave3  --PCSB
   generic map(
     IS_SYNC_SLAVE   => (c_NO,  c_NO,  c_NO,  c_YES),
     IS_USED         => (c_YES, c_YES, c_YES ,c_YES)

diff --git a/pinout/basic_constraints.lpf b/pinout/basic_constraints.lpf
index a2fb24de016741b29f5c6f5887f233479a3f8265..033e461aae42c7194d6cc02ced0e38f6140bbbf3 100644 (file)
--- a/pinout/basic_constraints.lpf
+++ b/pinout/basic_constraints.lpf
@@ -32,26 +32,33 @@ MULTICYCLE FROM CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" 30 ns;
 GSR_NET NET "GSR_N"; 
 
 
-MULTICYCLE TO CELL   "THE_MEDIA_INTERFACE/sci*" 20 ns;
-MULTICYCLE FROM CELL "THE_MEDIA_INTERFACE/sci*" 20 ns;
-MULTICYCLE TO CELL   "THE_MEDIA_INTERFACE/PROC_SCI_CTRL.wa*" 20 ns;
-BLOCK PATH TO   CLKNET "THE_MEDIA_INTERFACE/sci_write_i";
-BLOCK PATH FROM CLKNET "THE_MEDIA_INTERFACE/sci_write_i";
-BLOCK PATH TO   CLKNET "THE_MEDIA_INTERFACE/sci_read_i";
-BLOCK PATH FROM CLKNET "THE_MEDIA_INTERFACE/sci_read_i";
+MULTICYCLE TO CELL   "THE_MEDIA_INT*/sci*" 20 ns;
+MULTICYCLE FROM CELL "THE_MEDIA_INT*/sci*" 20 ns;
+MULTICYCLE TO CELL   "THE_MEDIA_INT*/PROC_SCI_CTRL.wa*" 20 ns;
+BLOCK PATH TO   CLKNET "THE_MEDIA_INT*/sci_write_i";
+BLOCK PATH FROM CLKNET "THE_MEDIA_INT*/sci_write_i";
+BLOCK PATH TO   CLKNET "THE_MEDIA_INT*/sci_read_i";
+BLOCK PATH FROM CLKNET "THE_MEDIA_INT*/sci_read_i";
 
-FREQUENCY NET "THE_MEDIA_INTERFACE/clk_rx_full" 200 MHz; # HOLD_MARGIN 500 ps 
-FREQUENCY NET "THE_MEDIA_INTERFACE/clk_tx_full" 200 MHz; # HOLD_MARGIN 500 ps 
+FREQUENCY NET "THE_MEDIA_INT*/clk_rx_full" 200 MHz; # HOLD_MARGIN 500 ps 
+FREQUENCY NET "THE_MEDIA_INT*/clk_tx_full" 200 MHz; # HOLD_MARGIN 500 ps 
 
 # REGION "REGION_SPI" "R19C150D" 20 20 DEVSIZE;
 # LOCATE UGROUP "THE_TOOLS/THE_SPI_RELOAD/THE_SPI_MASTER/SPI_group" REGION "REGION_SPI" ;
 # LOCATE UGROUP "THE_TOOLS/THE_SPI_RELOAD/THE_SPI_MEMORY/SPI_group" REGION "REGION_SPI" ;
 
+#main serdes is PCSB for stand-along or PCSA for crate operation
 LOCATE COMP          "THE_MEDIA_INTERFACE/gen_pcs0.THE_SERDES/PCSD_INST" SITE "PCSA" ;
 LOCATE COMP          "THE_MEDIA_INTERFACE/gen_pcs3.THE_SERDES/PCSD_INST" SITE "PCSB" ;
 REGION               "MEDIA_UPLINK" "R96C107D" 19 24;
 LOCATE UGROUP        "THE_MEDIA_INTERFACE/media_interface_group" REGION "MEDIA_UPLINK" ;
 
+#more space for media interface on backplane master
+LOCATE COMP          "THE_MEDIA_INT_MIXED/gen_pcs0.THE_SERDES/PCSD_INST" SITE "PCSA" ;
+REGION               "MEDIA_MIXED" "R95C50D" 20 70;
+LOCATE UGROUP        "THE_MEDIA_INT_MIXED/media_interface_group" REGION "MEDIA_MIXED" ;
+
+
 BLOCK PATH TO   PORT "LED*";
 BLOCK PATH TO   PORT "SFP*";
 BLOCK PATH FROM PORT "SFP*";